JPS615579A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS615579A JPS615579A JP12611384A JP12611384A JPS615579A JP S615579 A JPS615579 A JP S615579A JP 12611384 A JP12611384 A JP 12611384A JP 12611384 A JP12611384 A JP 12611384A JP S615579 A JPS615579 A JP S615579A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- thin film
- gas
- layer
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 34
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 36
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 7
- 239000011574 phosphorus Substances 0.000 claims abstract description 7
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 13
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 8
- 229910000077 silane Inorganic materials 0.000 abstract description 8
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 6
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 229910000073 phosphorus hydride Inorganic materials 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021529 ammonia Inorganic materials 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000009125 cardiac resynchronization therapy Methods 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000005546 reactive sputtering Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 229910001339 C alloy Inorganic materials 0.000 description 1
- OTMSDBZUPAUEDD-UHFFFAOYSA-N Ethane Chemical compound CC OTMSDBZUPAUEDD-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000808 amorphous metal alloy Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発−は水素化非晶質シリコンを用いた薄膜トランジス
タに関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a thin film transistor using hydrogenated amorphous silicon.
（従来技術とその問題点）
最近、、パーソナルコンビーータや各種情報処理機器を
小型化することが望まれてい斧が、−この中で最も小型
化しにくいものの１つにディスブレイカ忰げられる。現
在ディス−プレイの大部分はＣＲＴであるが、ＣＲＴは
真空中で電子銃から照射された電子線を電界等の手段に
より制御して螢光体に照射し、発光させるため、電子線
を走査する部分だけ装置が厚くなり、薄、型化が困難で
ある。(Prior Art and its Problems) Recently, there has been a desire to downsize personal computer beaters and various information processing equipment, and among these, the disk breaker is one of the items that is most difficult to downsize. Currently, most displays are CRTs, but CRTs scan electron beams in a vacuum to control the electron beam emitted from an electron gun using means such as an electric field to irradiate a phosphor and cause it to emit light. The device is thicker in the area where it is attached, making it difficult to make it thinner and more compact.
ディスプレイを薄型化にすることを目的とした液晶を用
いた薄型のディスプレイの開発が注目されている。この
液晶ディ、スプレィは電極が付いた２枚のガラス板の間
に１０μｍ厚程度０液晶をはさみ、該電極に印加した電
圧番こよって液晶の動きを制御するために、真空中の電
子の走行を制御する・ＣＲＴと比較して非常に薄いディ
スプレイが可能になる。2. Description of the Related Art The development of thin displays using liquid crystals is attracting attention for the purpose of making displays thinner. In this liquid crystal display, a liquid crystal about 10 μm thick is sandwiched between two glass plates with electrodes attached, and the movement of the liquid crystal is controlled by the voltage applied to the electrodes, which controls the movement of electrons in a vacuum.・Available for extremely thin displays compared to CRT.
液晶を動作させる場合、例えば電圧平均化法では、単純
なＸＹマトリクス動作では解像度を上げるために絵票数
を増加させる時フン、トラストが低下する問題があった
。このコントラスト低下を解決する方法として薄膜トラ
ンジスタを用いたアクティブマトリクス動作法が研究さ
れている。ここで用いられる薄膜材料には多結晶シリコ
ンやテルル、非晶質シリコンなどがあるが、低温プロセ
スで低価格の基板が使えることや安定で量産しやすいと
いう特徴を有する非晶質シリコンが最も適している。When operating a liquid crystal, for example, in the voltage averaging method, there is a problem in that the trust deteriorates when the number of picture slips is increased in order to increase the resolution in a simple XY matrix operation. An active matrix operation method using thin film transistors is being researched as a method to solve this contrast reduction. The thin film materials used here include polycrystalline silicon, tellurium, and amorphous silicon, but amorphous silicon is the most suitable because it can be used in low-temperature processes, uses low-cost substrates, and is stable and easy to mass-produce. ing.
非晶質シリコンを用いた薄膜トランジスタを平面ディス
プレイ等に応用する場合、歩留り良く、かつ低価格な薄
膜トランジスタアレイを形成する場合にはなるべく単純
な構造で少ないプロセス数であるのが望ましい。When applying a thin film transistor using amorphous silicon to a flat display or the like, it is desirable to have a structure as simple as possible and a small number of processes in order to form a thin film transistor array with high yield and low cost.
従来の薄膜トランジスタは第１図）こ示す様にゲート金
属が付いたガラス等の絶縁性基板上にプラズマＣＶＤ法
あるいは反応性スパッタ法を用いて例えば窒化シリコン
、非晶質シリコン層、りん等の不純物を含んだｎ＋非晶
質シリコンオーミック層を形成し、その後ソース・ドレ
イン両全属′電極を形成した後、ゲート金属上部のｎ＋
非晶質シリコンオーミック層をエツチングして逆スタガ
ード型薄膜トランジスタ構造にしていた。この時ｎ＋非
晶質シリコン層はソース・ドレイン電極のオーミック層
として働く、このｎ子弁晶質シリコン層−をエツチング
する時に例えばプラズマエツチングを用いると、プラズ
マのダメージによって暗電流が増加したり、あるいはエ
ツチングむらによって部分的に暗電流が増加したりして
、素子欠陥の原因や歩留り低下の一因となっていた。As shown in Figure 1, a conventional thin film transistor is formed using a plasma CVD method or a reactive sputtering method on an insulating substrate such as glass with a gate metal attached, for example, silicon nitride, an amorphous silicon layer, impurities such as phosphorus, etc. After forming an n+ amorphous silicon ohmic layer containing a
The amorphous silicon ohmic layer was etched to form an inverted staggered thin film transistor structure. At this time, the n+ amorphous silicon layer acts as an ohmic layer for the source/drain electrodes.If plasma etching is used to etch this n-type crystalline silicon layer, dark current may increase due to plasma damage. Alternatively, dark current may increase locally due to etching unevenness, contributing to device defects and a decrease in yield.
そこで、このエツチング工程をなくす方法としてｎ子弁
晶質シリコン層の厚さを薄くする方法が考えられるが、
この場合ソース・ドレイン間に。Therefore, one possible method to eliminate this etching step is to reduce the thickness of the n-cell crystalline silicon layer.
In this case, between source and drain.
ｎ＋非晶質シリコンが付いているため１例えばオフ抵抗
を１０９Ω以上とするためにはｎ＋層の厚さを数十へと
する必要があり、厚さの制御が困難であるばかりか、薄
膜トランジスタアレイのオフ抵抗のばらつきにあられれ
、かえって歩留りが低下する。Because n+ amorphous silicon is attached, the thickness of the n+ layer must be several tens of tens of ohms, for example, in order to increase the off-resistance to 109Ω or more, which not only makes it difficult to control the thickness, but also makes thin film transistor arrays difficult to control. This results in variations in off-resistance, which actually reduces yield.
（発明の目的） 本発明はこのような歩留り低下の原因をなくシ。(Purpose of the invention) The present invention eliminates this cause of yield decline.
均一な特性の薄膜トランジスタを提供することにある。The object of the present invention is to provide a thin film transistor with uniform characteristics.
１（発明の構成）
１本発明によれば、水素化非晶質
シリコン膜が絶縁層とオーミック層とでサンドイッチ状
に積層された構造を備えた薄膜トランジスタにおいて、
前記オーミック層が砒素、りんのうち少なくとも１種以
上を不純物として含ませた水素化非晶質シリコン炭素か
らなることを特徴とする薄膜トランジスタが得られる、
（発明の概要と効果）
本発明は上述の構造をとることにより、従来の薄膜トラ
ンジスタのｎ＋非晶質シリコンノーをエツチングすると
きに生ずる薄膜トランジスタの特性のばらつきを軽減さ
せた。すなわち、シリコンと炭素の非晶質合金である非
晶質゛シリコン炭素は。
1 (Structure of the invention)
1. According to the present invention, in a thin film transistor having a structure in which a hydrogenated amorphous silicon film is laminated in a sandwiched manner with an insulating layer and an ohmic layer,
A thin film transistor is obtained in which the ohmic layer is made of hydrogenated amorphous silicon carbon containing at least one of arsenic and phosphorus as an impurity. By adopting this structure, variations in characteristics of thin film transistors that occur when etching the n+ amorphous silicon layer of conventional thin film transistors are reduced. In other words, amorphous silicon carbon is an amorphous alloy of silicon and carbon.
炭素濃度が増加すると共に禁止帯幅が増加し、抵抗率が
増加する。この非晶質シリコン炭素に不純物である砒素
やりんをドーピングしたときの抵抗率と不純物濃度との
関係を第２図に実線で示す。As the carbon concentration increases, the forbidden band width increases and the resistivity increases. The solid line in FIG. 2 shows the relationship between resistivity and impurity concentration when this amorphous silicon carbon is doped with impurities such as arsenic and phosphorus.
非晶質シリコンの抵抗率と不純物濃度との関係（破線）
の場合に比べて、非晶質シリコン炭素では薄膜トランジ
スタのオフ抵抗を１０１０Ω以上にすることにできる１
φ〜ＩＱ’ ＱＣ１ｒＬ以上の抵抗率を有する不純物濃
度範囲が広くとれる。これは、第３図に示す様な逆スタ
ガード型薄膜トランジスタにおいて、オーミック層を砒
素またはりんのうち少なくとも１種類以上の不純物を含
ませた非晶質シリコン炭素で構成し、ソースドレイン間
の該オーミック層をエツチングしないでも安定して高い
オフ抵抗が得ら′れることを示す、このようにしてプロ
セスを簡単化し、低価格な薄膜トランジスタを供給する
ことができる。′この場合、非晶質シリコン中に含まれ
る炭素の量は１チ以上７０％までが、抵抗率を高くする
ことができて有効であるが、最も望ましい炭素濃度は５
％以上５０俤である。Relationship between resistivity and impurity concentration of amorphous silicon (dashed line)
Compared to the case of
A wide impurity concentration range having a resistivity of φ to IQ' QC1rL or more can be obtained. In an inverted staggered thin film transistor as shown in FIG. 3, the ohmic layer is made of amorphous silicon carbon containing at least one impurity of arsenic or phosphorus, and the ohmic layer is formed between the source and drain. This shows that a stable high off-resistance can be obtained without etching. In this way, the process can be simplified and low-cost thin film transistors can be provided. 'In this case, it is effective to increase the resistivity if the amount of carbon contained in the amorphous silicon is 1 to 70%, but the most desirable carbon concentration is 5%.
% or more is 50 yen.
また、第１図に示す様な従来構造においても。Also, in the conventional structure as shown in FIG.
オーミック層に非晶質シリコン炭素を用いることにより
、エツチングむらがたとえ起って、オーミック層が薄膜
トランジスタのソース曇ドレイン電極間に残ったとして
も、該オーミック層の抵抗率が高いため、均一性良くオ
フ抵抗の高い薄膜トランジスタが得られる。By using amorphous silicon carbon for the ohmic layer, even if etching unevenness occurs and the ohmic layer remains between the source and drain electrodes of the thin film transistor, the resistivity of the ohmic layer is high, resulting in good uniformity. A thin film transistor with high off-resistance can be obtained.
さらに、第４図に示す様なスタガード型薄膜トランリス
タにおいても、非晶質シリコン炭素オーミック層、非晶
質シリコン層、ゲート絶縁膜と連続的に形成して、オフ
抵抗の高い薄膜トランジスタが形成できる。従来、スタ
ガード型薄膜トランジスタを形成する時には、非晶質シ
リコンオーミック層を付け、これをエツチング処理して
ソース・ドレイン間のオーミック層を除去した後、非晶
質シリコン層ゲート絶縁層を付けていたが、本発明にお
いてはプロセスが簡単化し、低価格の薄膜トランジスタ
が供給できる。Furthermore, even in a staggered thin film transistor as shown in FIG. 4, an amorphous silicon carbon ohmic layer, an amorphous silicon layer, and a gate insulating film can be successively formed to form a thin film transistor with high off-resistance. Conventionally, when forming a staggered thin film transistor, an amorphous silicon ohmic layer was attached, this was etched to remove the ohmic layer between the source and drain, and then an amorphous silicon gate insulating layer was attached. In the present invention, the process is simplified and a low-cost thin film transistor can be provided.
（実施例１）
以下、本発明の実施例について図面を参照して説明する
。第３図は本発明の一実施例を示す断面図である。ガラ
ス基板１上にゲート金属であるクロム電極２を１０００
＾真空蒸着し、フォトリングラフィにより幅２０μｍに
加工する。続いてシランガスとアンモニアガスの混合ガ
スをソースとし、プラズマＣＶＤ装置を用い、グロー放
電分解により窒化シリコン層３を３００ＯＡ形成する１
次ｌこシランガスのグロー放電分解により非晶質シリコ
ン層４を３００ＯＡ形成する。さらにシランガスにメタ
ンガスを４０憾、ドーピングガスとしてホスフィンを１
．０００ｐｐｍ混合したガスをグロー放電分解してｎ型
非晶質シリコン炭素（ａ ８ ’ ｘ Ｃｔ−ｘ
Ｘ＝＝Ｑ、Ｑ５ ）層６を２００Ａ形成する。最後にソ
ースΦドレイン電極７であるモリブデンを２００ＯＡ形
成し、フォトリングラフィによりゲート長が８０μｍ、
ゲート幅が２０μｍになるように電極金属を加工し、ト
ランジスタ構造にする。さらにパッシベーション膜や遮
光膜の形成やトランジスタを島状にエツチングしトラン
ジスタマトリクスアレイを形成する。(Example 1) Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 3 is a sectional view showing one embodiment of the present invention. A chromium electrode 2, which is a gate metal, is placed on a glass substrate 1 at a thickness of 1000 nm.
^Vacuum evaporated and processed into a width of 20 μm using photolithography. Next, using a mixed gas of silane gas and ammonia gas as a source, a silicon nitride layer 3 with a thickness of 300 OA is formed by glow discharge decomposition using a plasma CVD device.
Next, an amorphous silicon layer 4 having a thickness of 300 OA is formed by glow discharge decomposition of silane gas. Furthermore, 40 ml of methane gas was added to the silane gas, and 1 ton of phosphine was added as a doping gas.
．． 000ppm mixed gas is decomposed by glow discharge to produce n-type amorphous silicon carbon (a8' x Ct-x
X==Q, Q5) Layer 6 is formed to a thickness of 200A. Finally, 200 OA of molybdenum which is the source Φ drain electrode 7 is formed, and the gate length is 80 μm by photolithography.
The electrode metal is processed so that the gate width is 20 μm to form a transistor structure. Furthermore, a passivation film and a light shielding film are formed, and transistors are etched into island shapes to form a transistor matrix array.
非晶質シリコン炭素を形成する手段としてはガスとして
ジシランやエタンガス、プロパンガスを使用することも
可能であり１反応性スパッタ法も使用することが可能で
ある。As a means for forming amorphous silicon carbon, it is also possible to use disilane, ethane gas, or propane gas as a gas, and it is also possible to use a one-reactive sputtering method.
上記の方法で得られた１２８ Ｘ ６４素子の薄膜トラ
ンジスタマトリクスアレイの静特性を評価した結果、ゲ
ート電圧１０Ｖ、ソース・ドレイン間電圧ｌＯ■での平
均オン電流は７ＸｌＯ＝Ａ平均オフ電流は１．２ Ｘ１
Ｏ＝” Ａであった。この値は従来素子に比べ 。As a result of evaluating the static characteristics of the thin film transistor matrix array of 128 x 64 elements obtained by the above method, the average on current at a gate voltage of 10 V and a source-drain voltage of lO is 7X lO = A average off current is 1.2 X1
O = "A. This value is lower than that of the conventional element.
平均オフ電流が２倍に増加しているものの画像欠陥の恐
れとなる１Ｏ−１ＯＡにくらべ著しく小さく画素欠陥を
大幅ｔこ減らすことができる。このように本発明は従来
よりプロセスが簡単化することができる。Although the average off-current is doubled, it is significantly smaller than 1O-1OA, which poses a risk of image defects, and pixel defects can be significantly reduced. In this way, the present invention can simplify the process compared to the conventional method.
また、上記薄膜トランジスタのソース・ドレイン間のｎ
型非晶質シリコン炭素６をＣＦ４を用いたドライエツチ
ングで除去し、特性を調べたところ平均オフ電流が６Ｘ
１０−１２Ａに改善され、しかも画像欠陥の恐れのある
Ｉ Ｘｌ０−１０Ａ以上のオフ電流を示す素子が全体の
０．３％以下と従来技術に比べ半分以下とすることがで
き安定してオフ抵抗の高い薄膜トランジスタが得られる
。Furthermore, n between the source and drain of the thin film transistor is
When the type amorphous silicon carbon 6 was removed by dry etching using CF4 and the characteristics were investigated, the average off-state current was 6X.
The off-state resistance has been improved to 10-12A, and moreover, the number of elements exhibiting an off-state current of I A thin film transistor with high
（実施例２）
第４図に示すスタガード型薄膜トランジスタについても
本発明を実施できる。即ち、ガラス基板１上にソース・
ドレイン電極であるモリブデン７を１５００＾形成し、
フォトリングラフィによりゲート長和μｍ、ゲート幅１
０μｍにな、るように形成する。その後、シランガスに
メタンガスを８０％。(Example 2) The present invention can also be practiced with respect to the staggered thin film transistor shown in FIG. That is, a source is placed on the glass substrate 1.
1500^ of molybdenum 7 which is a drain electrode is formed,
Gate length sum μm, gate width 1 by photolithography
It is formed to have a thickness of 0 μm. After that, add 80% methane gas to silane gas.
ドーピングガスとしてホスフィンを］０００ｆｌ！ｍ混
合したガスをグロー放電分解してｎ型非晶質シリコン炭
素（ａ”’ＸＣＩ−ｘ ＋ Ｘ ＝０．１５ ）層６を
１００＾形成し、次ｌこシランガスをグロー放電分解し
て非晶質シリコン層４を３０００λ、形成し、さらｌこ
シランガスとＮ、Ｏガスの混合ガスをグロー放電分解し
て酸化シリコン層３を２０００＾形成する６最後にゲー
ト電極２であるアルミニウムを２０００大形成し、た後
フォトリングラフィにより２０μｍ幅に加工してトラン
ジスタ構造にする。次に遮光膜の形成やパッシベーショ
ン用絶縁膜の形成を形成して薄膜トランジスタマトリク
スアレイを形成する。このように形成したスタガード構
造薄膜トランジスタにおいても平均オン電流５ＸＩＦ’
Ａ、平均オフ電流８ ＸＩＯ”’ Ａがゲート電圧１０
Ｖ、ソース・ドレイン電圧１０ｖで得られ、本発明が低
価格で安定にオフ電流の小さい薄膜トランジスタを提供
することができることを示した。Phosphine as doping gas]000fl! The mixed gas is decomposed by glow discharge to form 100 layers of n-type amorphous silicon carbon (a"'XCI-x + Form a crystalline silicon layer 4 with a thickness of 3000λ, and then decompose a mixed gas of silane gas, N, and O gas by glow discharge to form a silicon oxide layer 3 of 2000λ. After forming, it is processed into a width of 20 μm by photolithography to form a transistor structure.Next, a light shielding film and a passivation insulating film are formed to form a thin film transistor matrix array.The staggered structure formed in this way is Even in structural thin film transistors, the average on-current is 5XIF'
A, average off-current 8 XIO”' A is gate voltage 10
V and a source-drain voltage of 10 V, indicating that the present invention can stably provide a thin film transistor with low off-state current at a low cost.
（以 トゴｊ〈自）(hereinafter ``togoj〈self'')
第１図は従来の逆スタガード型薄膜トランジスタの断面
図、茅２図は非晶質シリコン炭素の抵抗率と不純物濃度
との関係を示す図。第３図は本発明による逆スタガード
型薄膜トランジスタの断面図、第４図は本発明によるズ
タガート型薄膜トランジスタの断面図である。
図において、
１・・・絶縁性基板、２・・・ゲート金属、３・・絶縁
体層、４・・・非晶質シリコン半導体層、５・・・ｎ＋
非晶質シリコンオーミック層、６・・・ｎ−非晶質シリ
コン炭素オーミックノー、７・・・ソース・ドレイン醒
極である。Fig. 1 is a cross-sectional view of a conventional inverted staggered thin film transistor, and Fig. 2 is a diagram showing the relationship between resistivity and impurity concentration of amorphous silicon carbon. FIG. 3 is a cross-sectional view of an inverted staggered thin film transistor according to the present invention, and FIG. 4 is a cross-sectional view of a staggered thin film transistor according to the present invention. In the figure, 1... insulating substrate, 2... gate metal, 3... insulator layer, 4... amorphous silicon semiconductor layer, 5... n+
Amorphous silicon ohmic layer, 6...n-amorphous silicon carbon ohmic layer, 7... source/drain awakening pole.
Claims (1)
ンドイッチ状に積層された構造を備えた薄膜トランジス
タにおいて、前記オーミック層が、砒素、りんのうち少
なくとも１種以上を不純物として含ませた水素化非晶質
シリコン炭素からなることを特徴とする薄膜トランジス
タ。In a thin film transistor having a structure in which a hydrogenated amorphous silicon film is laminated in a sandwiched manner with an insulating layer and an ohmic layer, the ohmic layer is hydrogenated and contains at least one of arsenic and phosphorus as an impurity. A thin film transistor characterized by being made of amorphous silicon carbon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12611384A JPS615579A (en) | 1984-06-19 | 1984-06-19 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12611384A JPS615579A (en) | 1984-06-19 | 1984-06-19 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS615579A true JPS615579A (en) | 1986-01-11 |
Family
ID=14926951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12611384A Pending JPS615579A (en) | 1984-06-19 | 1984-06-19 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615579A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2601801A1 (en) * | 1986-07-16 | 1988-01-22 | Morin Francois | ACTIVE MATRIX DISPLAY SCREEN USING HYDROGENIC AMORPHOUS SILICON CARBIDE AND METHOD OF MANUFACTURING THE SAME |
| JPS63178559A (en) * | 1987-01-19 | 1988-07-22 | Sanyo Electric Co Ltd | Thin-film transistor |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5114869A (en) * | 1988-05-30 | 1992-05-19 | Seikosha Co., Ltd. | Method for producing reverse staggered type silicon thin film transistor |
| US5399387A (en) * | 1993-01-28 | 1995-03-21 | Applied Materials, Inc. | Plasma CVD of silicon nitride thin films on large area glass substrates at high deposition rates |
| US5510631A (en) * | 1991-02-25 | 1996-04-23 | Canon Kabushiki Kaisha | Non-monocrystalline silicon carbide semiconductor and semiconductor device employing the same |
-
1984
- 1984-06-19 JP JP12611384A patent/JPS615579A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2601801A1 (en) * | 1986-07-16 | 1988-01-22 | Morin Francois | ACTIVE MATRIX DISPLAY SCREEN USING HYDROGENIC AMORPHOUS SILICON CARBIDE AND METHOD OF MANUFACTURING THE SAME |
| JPS63178559A (en) * | 1987-01-19 | 1988-07-22 | Sanyo Electric Co Ltd | Thin-film transistor |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5114869A (en) * | 1988-05-30 | 1992-05-19 | Seikosha Co., Ltd. | Method for producing reverse staggered type silicon thin film transistor |
| US5510631A (en) * | 1991-02-25 | 1996-04-23 | Canon Kabushiki Kaisha | Non-monocrystalline silicon carbide semiconductor and semiconductor device employing the same |
| US5399387A (en) * | 1993-01-28 | 1995-03-21 | Applied Materials, Inc. | Plasma CVD of silicon nitride thin films on large area glass substrates at high deposition rates |
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