JPS63178559A - Thin-film transistor - Google Patents

Thin-film transistor

Info

Publication number
JPS63178559A
JPS63178559A JP1118887A JP1118887A JPS63178559A JP S63178559 A JPS63178559 A JP S63178559A JP 1118887 A JP1118887 A JP 1118887A JP 1118887 A JP1118887 A JP 1118887A JP S63178559 A JPS63178559 A JP S63178559A
Authority
JP
Japan
Prior art keywords
electrode
thin film
film
semiconductor thin
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1118887A
Other languages
Japanese (ja)
Inventor
Tatsuro Usuki
臼杵 辰朗
Kaneo Watanabe
渡邉 金雄
Saburo Nakajima
三郎 中島
Shoichi Nakano
中野 昭一
Yukinori Kuwano
桑野 幸徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1118887A priority Critical patent/JPS63178559A/en
Publication of JPS63178559A publication Critical patent/JPS63178559A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent the deterioration, etc., of element characteristics, and to improve heat resistance by adding a substance except a semiconductor thin- film and an electrode material difficult to be ionized to one parts or the whole region of a source region and a drain region in the semiconductor thin-film being in contact with a source electrode and a drain electrode. CONSTITUTION:A gate electrode 12 is formed onto an insulating substrate 11 consisting of glass, etc. A gate insulating film 13 is shaped onto the substrate 11, coating the electrode 12, and non-doped amorphous Si14 is formed onto the gate insulating film 13 as a semiconductor film. A not more than 20 at. % substance except a semiconductor thin film and an electrode material difficult to be ionized is contained onto the film 14, and N<+> layers 15, 16 to which nitrogen is added are shaped according to predetermined patterns as an example, and a source electrode 17 and a drain electrode 18 are formed onto the layers 15, 16. Accordingly, the deterioration of element characteristics and the instability of characteristics are eliminated, thus improving heat resistance.

Description

【発明の詳細な説明】 産慮上二丑尻分団 本発明は非晶質シリコン薄膜トランジスタ等の薄膜トラ
ンジスタ(T F T : Th1n Film Tr
an−sistor)の素子構造の改良に関する。
[Detailed Description of the Invention] The present invention relates to thin film transistors (TFT: Th1n Film Tr) such as amorphous silicon thin film transistors.
The present invention relates to an improvement in the element structure of an-sister.

従来生茨歪 薄膜トランジスタの一例としてスタガ形の非晶質シリコ
ン薄膜トランジスタ(以下、単に薄膜トランジスタ又は
TPTという。)の従来構造を第4図に示す。lはガラ
スなどの絶縁基板、2はOrなどのゲート電極、3はゲ
ート絶縁膜、4は半導体薄膜としてノンドープシリコン
膜、5.6は該シリコン膜上面に所定パターンで形成さ
れたn1層、7はAIlなどのソース電極、8はドレイ
ン電極で、ソース電極7と同じ<AN材で形成される。
FIG. 4 shows a conventional structure of a staggered amorphous silicon thin film transistor (hereinafter simply referred to as a thin film transistor or TPT) as an example of a conventional strained thin film transistor. l is an insulating substrate such as glass, 2 is a gate electrode such as Or, 3 is a gate insulating film, 4 is a non-doped silicon film as a semiconductor thin film, 5.6 is an n1 layer formed in a predetermined pattern on the upper surface of the silicon film, 7 8 is a source electrode such as Al, and 8 is a drain electrode, which is made of the same <AN material as the source electrode 7.

この構成において、n+層5,6を形成しているのは、
ソース領域、ドレイン領域と電極7,8とのオーミック
コンタクトをとるためである。
In this configuration, the n+ layers 5 and 6 are formed by:
This is to establish ohmic contact between the source and drain regions and the electrodes 7 and 8.

n゛層の形成はシリコン膜4の形成時にリン等を不純物
として添加したり、ノンドープの膜を形成した後にイオ
ン注入若しくは拡散によって形成する。このように電極
とのオーミックコンタクトをとるためにn1層を形成す
ることは例えば、「第41回応用物理学会講演会予稿集
、1980年秋、2.408.19P−Y−1、“耐熱
性ゲートをもつa−3iFET”用品、松材」といった
刊行物においても開示されている。
The n' layer is formed by adding phosphorus or the like as an impurity when forming the silicon film 4, or by ion implantation or diffusion after forming a non-doped film. Forming the n1 layer in order to make ohmic contact with the electrode is explained in, for example, ``41st Japan Society of Applied Physics Conference Proceedings, Fall 1980, 2.408.19P-Y-1, ``Heat-resistant gate It is also disclosed in publications such as "A-3iFET Supplies, Pine Wood" with

また、上記したn″層を形成する以外にソース領域、ド
レイン領域と電極とを接触させる方法として、チャンネ
ルとなるi層に直接電極を接触させる方法も知られてい
る。
Furthermore, in addition to forming the above-mentioned n'' layer, as a method of bringing the source region and the drain region into contact with the electrode, there is also known a method of bringing the electrode into direct contact with the i-layer, which becomes the channel.

日が解゛ しようとする間 占 ところで、上記のようにA1等の電極と例えばn゛層と
を接触させると、素子を比較的高温に保った場合電極材
料である金属がソース領域、ドレイン領域に拡散するた
めに、素子特性を劣化させたり、特性を不安定にしたり
するといった問題がある。また、電極形成後のプロセス
に熱処理工程がある場合には耐熱性に問題を生じるし、
更に信頬性試験における温度試験においても、TPT特
性に変化をもたらすものである。
By the way, if an electrode such as A1 is brought into contact with, for example, an n layer as described above, if the element is kept at a relatively high temperature, the metal that is the electrode material will leak into the source and drain regions. This causes problems such as deterioration of device characteristics and destabilization of characteristics. Additionally, if there is a heat treatment step in the process after electrode formation, problems may arise with heat resistance.
Furthermore, it also brings about changes in TPT characteristics in the temperature test in the reliability test.

本発明はこのような問題点に鑑み、素子特性の劣化や特
性の不安定さ、耐熱性を改善することを目的としている
In view of these problems, the present invention aims to improve the deterioration of element characteristics, instability of characteristics, and heat resistance.

、 声を”するための手 上記目的を達成するため本発明に係る薄膜トランジスタ
はソース電極、ドレイン電極に接する半導体薄膜のソー
ス領域、ドレイン領域の一部若しくは全域に、前記半導
体薄膜及び電極材料以外の物質でイオン化しにくい物質
が添加されていることを特徴としている。
In order to achieve the above object, the thin film transistor according to the present invention includes a thin film transistor containing a material other than the semiconductor thin film and the electrode material in a part or the entire region of the semiconductor thin film in contact with the source electrode and the drain electrode. It is characterized by the addition of a substance that is difficult to ionize.

作−一一里 半導体薄膜に半導体薄膜及び電極材料以外の物質でイオ
ン化しにくい物質を添加すると、この物質はイオン化傾
向が低いので、半導体薄膜中で他の物質と結合しにクク
、単独で存在する。そのため、半導体薄膜中に電極材料
が拡散しようとする場合に前記物質が拡散を抑制する働
きをなす。そして、この物質は電極材料とも異なるので
、素子特性や耐熱性に悪影響を及ぼすことはない。尚、
前記半導体薄膜及び電極材料以外の物質でイオン化しに
(い物質を大量に半導体薄膜中に添加すると活性な半導
体としての特性に影響を及ぼすので、適量に限る必要が
ある。
When a substance other than the semiconductor thin film and electrode material that is difficult to ionize is added to the semiconductor thin film, this substance has a low tendency to ionize, so it does not combine with other substances in the semiconductor thin film and exists alone. do. Therefore, when the electrode material tries to diffuse into the semiconductor thin film, the substance acts to suppress the diffusion. Since this substance is different from the electrode material, it does not adversely affect the device characteristics or heat resistance. still,
If a large amount of a substance other than the semiconductor thin film and electrode material is added to the semiconductor thin film, it will affect its properties as an active semiconductor, so it is necessary to limit the amount to an appropriate amount.

大−族一斑 〔実施例1〕 第1図は本発明の一実施例として、スタガ形の非晶質シ
リコン薄膜トランジスタの構造を示している。1)はガ
ラス若しくはセラミクス等の絶縁性基板で、その上に所
定のパターンでゲート電極12が形成されている。この
ゲート電極12を覆って絶縁性基板1)上にゲート絶縁
膜13が形成され、その上に半導体膜として例えばノン
ドープの非晶質シリコン14が形成されている。シリコ
ン膜14の上には半導体薄膜及び電極材料以外の物質で
イオン化しにくい物質の一例として窒素を添加したn゛
層15,16が所定パターンで形成され、このn゛層1
5,16の上にソース電極17、ドレイン電極18が形
成されている。
Large Group One Spot [Example 1] FIG. 1 shows the structure of a staggered amorphous silicon thin film transistor as an example of the present invention. 1) is an insulating substrate made of glass or ceramics, on which a gate electrode 12 is formed in a predetermined pattern. A gate insulating film 13 is formed on the insulating substrate 1) covering the gate electrode 12, and a non-doped amorphous silicon 14, for example, is formed thereon as a semiconductor film. On the silicon film 14, n' layers 15 and 16 doped with nitrogen, which is an example of a substance other than the semiconductor thin film and electrode material that is difficult to ionize, are formed in a predetermined pattern.
A source electrode 17 and a drain electrode 18 are formed on the electrodes 5 and 16.

前記ゲート電極12は例えばクロム若しくは金/クロム
等を電子ビーム蒸着法にて蒸着し、バターニングを行な
うことにより形成される。ゲート絶縁膜13は、例えば
窒化シリコン膜をプラズマCVD法にて成長することに
より形成される。ノンドープ非晶質シリコン膜14も同
じくプラズマCVD法により形成する。n“層15,1
6は先ずプラズマCVD法でシリコン膜14の全面に形
成した後、電極17.18と共にエツチングによりパタ
ーニングすることにより所定パターンに形成する。n3
層15.16をプラズマCVD法で形成する際、反応ガ
スとしてシランガスに1〜2%のホスフィン(PH3)
、1〜20%のアンモニア(NHs)を混入したものを
使用する。ソース電極17、ドレイン電極18は、バタ
ーニングされていないn1層15.16全面に例えばA
I材を抵抗加熱蒸着法にて蒸着した後、バターニングす
ることにより形成する。パターニングはn′″層15.
16と併せて行なう。即ち、先ず、上の層であるAI!
、膜をエツチングし、更にn″層をエツチングするとい
う順序で行なう。n″層のエツチングはノンドープ層が
露出するまで行なう。尚、エツチングはドライエツチン
グ、ウェットエツチングのいずれも実施できる。
The gate electrode 12 is formed by depositing, for example, chromium or gold/chromium by electron beam evaporation and patterning. The gate insulating film 13 is formed, for example, by growing a silicon nitride film using a plasma CVD method. The non-doped amorphous silicon film 14 is also formed by the plasma CVD method. n" layer 15,1
6 is first formed on the entire surface of the silicon film 14 by the plasma CVD method, and then patterned together with the electrodes 17 and 18 by etching to form a predetermined pattern. n3
When forming layers 15 and 16 by plasma CVD, 1 to 2% phosphine (PH3) is added to silane gas as a reactive gas.
, mixed with 1 to 20% ammonia (NHs) is used. The source electrode 17 and the drain electrode 18 are formed on the entire surface of the unpatterned N1 layer 15.
It is formed by depositing the I material by a resistance heating deposition method and then patterning it. Patterning is performed on the n''' layer 15.
This will be done in conjunction with 16. That is, first, the upper layer, AI!
, the film, and then the n'' layer. The n'' layer is etched until the non-doped layer is exposed. Incidentally, the etching can be performed by either dry etching or wet etching.

下表に上記薄膜トランジスタの各層、領域の材料、膜厚
、作成方法の代表的なものを掲げる。
The table below lists typical materials, film thicknesses, and manufacturing methods for each layer and region of the thin film transistor.

c以下、余白〕 作製したTPTのソース領域とドレイン領域の間のチャ
ンネル部分の代表的な大きさはチャンネル幅50μm、
チャンネル長20μmである。
Below c, blank space] The typical size of the channel portion between the source region and drain region of the fabricated TPT is a channel width of 50 μm,
The channel length is 20 μm.

第2図にソース領域或いはドレイン領域における電極材
料(AI)の濃度分布を示す。実線が本発明の例、破線
が従来の例である。同図より、本発明の場合ソース、ド
レイン領域への電極材料の拡散が大幅に抑制されている
のがわかる。
FIG. 2 shows the concentration distribution of the electrode material (AI) in the source region or drain region. The solid line is an example of the present invention, and the broken line is a conventional example. From the figure, it can be seen that in the case of the present invention, diffusion of electrode material into the source and drain regions is significantly suppressed.

第3図に上記実施例で作製したTPTを150℃の雰囲
気中に放置したときのOFF電流の時間的変化を示す。
FIG. 3 shows the temporal change in the OFF current when the TPT manufactured in the above example was left in an atmosphere at 150°C.

図かられかるように、n″層に窒素を添加しない従来の
TPTはOFF電流が経時的に10−”  (A)から
10−1° (A)へと変化するが、本実施例のように
n″層に窒素を添加したものはOFF電流は10−” 
 (A)からほとんど変化しなかった。このことから、
n″層に窒素を添加したものは耐熱性等の信頬性を上げ
ることができるといえる。
As can be seen from the figure, in the conventional TPT without nitrogen added to the n'' layer, the OFF current changes from 10-'' (A) to 10-1° (A) over time, but as in this example, the OFF current changes from 10-'' (A) to 10-1° (A). In the case where nitrogen is added to the n'' layer, the OFF current is 10-''
There was almost no change from (A). From this,
It can be said that adding nitrogen to the n'' layer can improve reliability such as heat resistance.

尚、上記実施例では、ゲート絶縁膜13、ノンドープ非
晶質シリコン層14及びn゛層15.16はプラズマC
VD法を用いて作製しているが、スパッタリングなどの
他の方法で作製してもよいことは勿論である。また、窒
素の添加方法としてアンモニアを混入しているが、窒素
ガスを使っても実施できる。更に、窒素の添加方法とし
てイオン注入技術によることができる。
In the above embodiment, the gate insulating film 13, the non-doped amorphous silicon layer 14, and the n' layers 15 and 16 are exposed to plasma C.
Although the VD method is used for manufacturing, it goes without saying that other methods such as sputtering may be used. Further, although ammonia is mixed in as a method of adding nitrogen, it can also be carried out using nitrogen gas. Furthermore, ion implantation technology can be used as a method for adding nitrogen.

また、n゛層における窒素の濃度は高ければ高い程電極
材料の拡散を抑制する効果が大きいが、反面あまり高(
すると活性な半導体の特性に影響を及ぼすようになるの
で、濃度の上限は自ずと定まる。実験によれば、窒素濃
度は20at%以下に押さえるべきであることが確認さ
れた。
In addition, the higher the concentration of nitrogen in the n layer, the greater the effect of suppressing the diffusion of the electrode material;
This will affect the properties of the active semiconductor, so the upper limit of the concentration will be determined automatically. Experiments have confirmed that the nitrogen concentration should be kept below 20 at%.

〔実施例2〕 実施例1において、n゛層に添加する窒素の濃度をソー
ス、ドレイン電極に近づくにつれて漸次大きくする。こ
れは、n+層の作製時に、アンモニア濃度を徐々に増加
することによって実現できる。このように電極材料の拡
散の大きい電極の近くを最大濃度となるよう窒素濃度に
勾配をもたせれば、非常に効果的に電極材料の拡散を抑
制できる。
[Example 2] In Example 1, the concentration of nitrogen added to the n' layer is gradually increased as it approaches the source and drain electrodes. This can be achieved by gradually increasing the ammonia concentration during the fabrication of the n+ layer. In this way, by creating a gradient in the nitrogen concentration so that the concentration is highest near the electrode where the electrode material diffuses greatly, the diffusion of the electrode material can be suppressed very effectively.

〔その他の実施可能な例〕[Other possible examples]

n+層に添加する物質は窒素に限らず、半導体薄膜材料
及び電極材料以外の物質でイオン化しにくい物質であれ
ば使用できる。そのような物質は周期律表第III族、
IV族、V族、VI族の中から選択でき、特に炭素、ボ
ロン、酸素から選ぶのが望ましい。また、前記物質は、
炭素、ボロン、酸素及び窒素の中の1種類に限らず、2
種類以上を選択して使用することができる。
The substance added to the n+ layer is not limited to nitrogen, but any substance other than semiconductor thin film materials and electrode materials that is difficult to ionize can be used. Such substances belong to group III of the periodic table,
It can be selected from Group IV, Group V, and Group VI, and is particularly preferably selected from carbon, boron, and oxygen. Furthermore, the substance is
Not limited to one type among carbon, boron, oxygen and nitrogen, but two
You can select and use more than one type.

又、上記物質はソース領域、ドレイン領域の全域に添加
してもよいし、一部の領域のみに添加してもよい。その
場合はなるべく電極の近くに高い濃度で存在するよう添
加するのがよい。
Further, the above substance may be added to the entire source region and drain region, or may be added to only a part of the region. In that case, it is preferable to add it so that it exists at a high concentration as close to the electrode as possible.

上記いずれの実施例も非晶質シリコンTPTへの適用例
であるが、非晶質シリコンTPTの他に、多結晶シリコ
ンTPT等、現在知られている他の種類のTPTへの適
用も可能であることはいうまでもない。また、TPTの
構造も、実施例で示したスタガ形に限らず、コプラナ(
coplarnar)形であっても本発明の適用を妨げ
るものではない。
All of the above embodiments are examples of application to amorphous silicon TPT, but in addition to amorphous silicon TPT, it is also possible to apply to other currently known types of TPT such as polycrystalline silicon TPT. It goes without saying that there is. In addition, the structure of TPT is not limited to the staggered structure shown in the example, but also coplanar (
The application of the present invention is not hindered even in the case of a coplarnar type.

又里■四困 以上説明したように本発明に係るTPTによれば、ソー
ス領域、ドレイン領域の一部若しくは全域に窒素等のイ
オン化しにくい物質を適量添加することにより電極材料
の拡散を抑制できるので、OFF電流の安定化、耐熱性
の向上が図れるといった効果がある。TPTはEL表示
装置や液晶表示装置の駆動回路として使用されるので、
大きなON10 F F電流比が要求され、広い保存温
度、動作温度が必要であることを考えれば、本発明のT
PTは、屋外での使用や、高信頼性の要求されるデバイ
スへの適用等が可能になるといった多大な効果をもたら
すものである。
As explained above, according to the TPT according to the present invention, diffusion of the electrode material can be suppressed by adding an appropriate amount of a substance that is difficult to ionize, such as nitrogen, to part or all of the source region and drain region. Therefore, it is possible to stabilize the OFF current and improve heat resistance. TPT is used as a drive circuit for EL display devices and liquid crystal display devices, so
Considering that a large ON10 F F current ratio is required and a wide storage temperature and operating temperature are required, the T of the present invention
PT brings about great effects such as being able to be used outdoors and applied to devices that require high reliability.

加えて、本発明により電極材料の拡散が抑制されるので
、電極としてAA材のような安価なものを使用でき、多
数のTPTを組込んだEL表示装置等のデバイスの低コ
スト化が実現する。
In addition, since diffusion of the electrode material is suppressed by the present invention, an inexpensive material such as AA material can be used as the electrode, and the cost of devices such as EL display devices incorporating a large number of TPTs can be reduced. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例としてスタガ形の非晶質シリ
コンTPTの構造を示す図、第2図はソース、ドレイン
領域における電極材料(AA)の濃度分布を示す図、第
3図は150℃で放置したTPTのOFF電流の時間的
変化を示す図、第4図は従来の非晶質シリコンTPTの
構造を示す図である。 1)・・・絶縁基板、12・・・ゲート電極、13・・
・ゲート絶縁膜、14・・・ノンドープ非晶質シリコン
膜、15.16・・・n゛層、17・・・ソース電極、
18・・・ドレイン電極。 特許出願人 :  三洋電機株式会社 代理人   : 弁理士  中島 司朗第1図 第2図 ソースあるい喰ドレイン金良よ\ のAQ宅本−からの糸さ 第3図 吟唱 第4図
FIG. 1 is a diagram showing the structure of a staggered amorphous silicon TPT as an example of the present invention, FIG. 2 is a diagram showing the concentration distribution of electrode material (AA) in the source and drain regions, and FIG. FIG. 4 is a diagram showing the temporal change in the OFF current of a TPT left at 150° C., and FIG. 4 is a diagram showing the structure of a conventional amorphous silicon TPT. 1)...Insulating substrate, 12...Gate electrode, 13...
・Gate insulating film, 14... Non-doped amorphous silicon film, 15.16... n layer, 17... Source electrode,
18...Drain electrode. Patent Applicant: Sanyo Electric Co., Ltd. Agent: Patent Attorney Shiro Nakajima Figure 1 Figure 2 Sauce Or Ikui Drain Kinryo\'s AQ Takumoto-kara no Itosa Figure 3 Chorus Figure 4

Claims (1)

【特許請求の範囲】 (1)ソース電極、ドレイン電極に接する半導体薄膜の
ソース領域、ドレイン領域の一部若しくは全域に、前記
半導体薄膜及び電極材料以外の物質でイオン化しにくい
物質が添加されていることを特徴とする薄膜トランジス
タ。 (2)前記半導体薄膜が非晶質シリコンの薄膜であるこ
とを特徴とする特許請求の範囲第(1)項に記載の薄膜
トランジスタ。 (3)前記半導体薄膜及び電極材料以外の物質でイオン
化しにくい物質は20at%以下の濃度でソース領域、
ドレイン領域の一部若しくは全域に添加されていること
を特徴とする特許請求の範囲第(1)項若しくは第(2
)項のいずれかに記載の薄膜トランジスタ。(4)前記
ソース電極、ドレイン電極はAl材で形成されているこ
とを特徴とする特許請求の範囲第(1)項乃至第(3)
項のいずれかに記載の薄膜トランジスタ。 (5)前記半導体薄膜及び電極材料以外の物質でイオン
化しにくい物質は周期律表III族、IV族、V族、VI族の
うちの少なくとも1つから選択されることを特徴とする
特許請求の範囲第(1)項乃至第(4)項のいずれかに
記載の薄膜トランジスタ。 (6)前記半導体薄膜及び電極材料以外の物質でイオン
化しにくい物質として、ボロン、炭素、窒素、酸素のう
ち少なくとも1つが選択されることを特徴とする特許請
求の範囲第(1)項乃至第(4)項のいずれかに記載の
薄膜トランジスタ。 (7)前記半導体薄膜及び電極材料以外の物質でイオン
化しにくい物質の少なくとも1つが電極に近づくにつれ
て増加させてあることを特徴とする特許請求の範囲第(
1)項乃至第(6)項のいずれかに記載の薄膜トランジ
スタ。
[Claims] (1) A substance other than the semiconductor thin film and electrode material that is difficult to ionize is added to a part or the entire region of the source region and drain region of the semiconductor thin film in contact with the source electrode and drain electrode. A thin film transistor characterized by: (2) The thin film transistor according to claim (1), wherein the semiconductor thin film is an amorphous silicon thin film. (3) Substances other than the semiconductor thin film and electrode materials that are difficult to ionize are contained in the source region at a concentration of 20 at% or less.
Claim (1) or (2) characterized in that the compound is added to a part or the entire region of the drain region.
) The thin film transistor according to any one of the items. (4) Claims (1) to (3) characterized in that the source electrode and the drain electrode are formed of an Al material.
2. The thin film transistor according to any one of paragraphs. (5) The substance other than the semiconductor thin film and electrode material that is difficult to ionize is selected from at least one of Group III, Group IV, Group V, and Group VI of the periodic table. The thin film transistor according to any one of ranges (1) to (4). (6) At least one of boron, carbon, nitrogen, and oxygen is selected as the substance other than the semiconductor thin film and electrode material that is difficult to ionize. The thin film transistor according to any one of (4). (7) At least one substance other than the semiconductor thin film and the electrode material that is difficult to ionize increases as it approaches the electrode.
The thin film transistor according to any one of items 1) to (6).
JP1118887A 1987-01-19 1987-01-19 Thin-film transistor Pending JPS63178559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1118887A JPS63178559A (en) 1987-01-19 1987-01-19 Thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1118887A JPS63178559A (en) 1987-01-19 1987-01-19 Thin-film transistor

Publications (1)

Publication Number Publication Date
JPS63178559A true JPS63178559A (en) 1988-07-22

Family

ID=11771090

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1118887A Pending JPS63178559A (en) 1987-01-19 1987-01-19 Thin-film transistor

Country Status (1)

Country Link
JP (1) JPS63178559A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065202A (en) * 1988-02-26 1991-11-12 Seikosha Co., Ltd. Amorphous silicon thin film transistor array substrate and method for producing the same
US5114869A (en) * 1988-05-30 1992-05-19 Seikosha Co., Ltd. Method for producing reverse staggered type silicon thin film transistor
WO2008018478A1 (en) * 2006-08-09 2008-02-14 Mitsui Mining & Smelting Co., Ltd. Junction structure of device
JP2010177621A (en) * 2009-02-02 2010-08-12 Mitsubishi Electric Corp Semiconductor device, production process of the same, and display

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS615579A (en) * 1984-06-19 1986-01-11 Nec Corp Thin film transistor
JPS61188969A (en) * 1985-02-18 1986-08-22 Matsushita Electric Ind Co Ltd Thin film transistor
JPS6237920B2 (en) * 1981-10-23 1987-08-14 Hitachi Chemical Co Ltd

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6237920B2 (en) * 1981-10-23 1987-08-14 Hitachi Chemical Co Ltd
JPS615579A (en) * 1984-06-19 1986-01-11 Nec Corp Thin film transistor
JPS61188969A (en) * 1985-02-18 1986-08-22 Matsushita Electric Ind Co Ltd Thin film transistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065202A (en) * 1988-02-26 1991-11-12 Seikosha Co., Ltd. Amorphous silicon thin film transistor array substrate and method for producing the same
US5114869A (en) * 1988-05-30 1992-05-19 Seikosha Co., Ltd. Method for producing reverse staggered type silicon thin film transistor
WO2008018478A1 (en) * 2006-08-09 2008-02-14 Mitsui Mining & Smelting Co., Ltd. Junction structure of device
JPWO2008018478A1 (en) * 2006-08-09 2009-12-24 三井金属鉱業株式会社 Device junction structure
JP2010177621A (en) * 2009-02-02 2010-08-12 Mitsubishi Electric Corp Semiconductor device, production process of the same, and display

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