JPS60198864A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS60198864A JPS60198864A JP5563784A JP5563784A JPS60198864A JP S60198864 A JPS60198864 A JP S60198864A JP 5563784 A JP5563784 A JP 5563784A JP 5563784 A JP5563784 A JP 5563784A JP S60198864 A JPS60198864 A JP S60198864A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistance
- thin film
- amorphous silicon
- amorphous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 36
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052796 boron Inorganic materials 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 6
- 238000001312 dry etching Methods 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 238000011109 contamination Methods 0.000 abstract 1
- 230000007423 decrease Effects 0.000 description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 229910000077 silane Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- JCXJVPUVTGWSNB-UHFFFAOYSA-N Nitrogen dioxide Chemical compound O=[N]=O JCXJVPUVTGWSNB-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 238000009125 cardiac resynchronization therapy Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RFSDQDHHBKYQOD-UHFFFAOYSA-N 6-cyclohexylmethyloxy-2-(4'-hydroxyanilino)purine Chemical compound C1=CC(O)=CC=C1NC1=NC(OCC2CCCCC2)=C(N=CN2)C2=N1 RFSDQDHHBKYQOD-UHFFFAOYSA-N 0.000 description 1
- 238000012935 Averaging Methods 0.000 description 1
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- 241000219122 Cucurbita Species 0.000 description 1
- 235000009852 Cucurbita pepo Nutrition 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- GQPLMRYTRLFLPF-UHFFFAOYSA-N nitrous oxide Inorganic materials [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は薄膜トランジスタに関し、特ＫＯＦＦ抵抗の高
い非晶質シリコンを用いた薄膜トランジスタに関すふ−
（従来技術と問題点）
最近、パーソナルコンピュータや各種情報処理機器の小
型化が望まれているが、この中で小型化の困難なものの
１つにディスプレイがある。現在、ディスプレイは大部
分がＣＲＴであるが、このＣＲＴは真空中で電子線が電
界等で制御されて螢光体に照射されて発光するため、こ
の電子線を走査させる部分の装置が大きくなυ小型化が
困難となる。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to thin film transistors, and particularly relates to thin film transistors using amorphous silicon with high KOFF resistance. (Prior Art and Problems) Recently, personal computers and various There is a desire to downsize information processing equipment, and one of the items that is difficult to downsize is a display. Currently, most displays are CRTs, but in a CRT, an electron beam is controlled by an electric field in a vacuum and illuminates a phosphor to emit light, so the device that scans the electron beam has to be large. υIt becomes difficult to downsize.
このディスプレイの小型化のために液晶を用いた薄型の
ディスプレイが注目されている。この液晶ディスプレイ
は電極が付いた２枚のガラス板の間に１０μｍ厚程度０
液晶を挾み、これら２枚のガラス板に付いた電極によっ
て液晶に電界を印加し液晶の動きを制御するため薄いデ
ィスプレイが可能になる。しかし、この液晶を動作させ
る場合、例えば電圧平均化法によると単純なＸＹマトリ
クス動作において絵素数が増加した時、コントラスト等
が低下する問題があった。In order to reduce the size of these displays, thin displays using liquid crystals are attracting attention. This liquid crystal display has a thickness of about 10 μm between two glass plates with electrodes.
A thin display is made possible by sandwiching the liquid crystal and applying an electric field to the liquid crystal using electrodes attached to these two glass plates to control the movement of the liquid crystal. However, when this liquid crystal is operated, for example, when the voltage averaging method is used, there is a problem that when the number of picture elements increases in a simple XY matrix operation, the contrast etc. decrease.
このコントラストの低下を解決する方法として、薄膜ト
ランジスタを用いたアクティブマトリクス動作法が研究
されており、その薄膜としては多結晶Ｓｌやテルル、非
晶質シリコンを用いたものがあるが、低温プロセスで低
価格の基板を使用でき、安定で゛量産しやすいという特
徴をもつ非晶質シリコンが最も適している。As a method to solve this decrease in contrast, active matrix operation methods using thin film transistors are being researched, and some of these thin films use polycrystalline Sl, tellurium, and amorphous silicon, but they can be Amorphous silicon is most suitable because it can use inexpensive substrates, is stable, and is easy to mass produce.
この非晶質シリコンを用いた薄膜トランジスタをこのよ
うな平面ディスプレイに応用する場合、画素欠陥のない
ディスプレイを得るためにＯＮ抵抗とＯＦＦ抵抗の比が
十分高い薄膜トランジスタ素子を大面積に均一に形成す
ることが必要となる。When applying a thin film transistor using this amorphous silicon to such a flat display, it is necessary to uniformly form thin film transistor elements over a large area with a sufficiently high ratio of ON resistance to OFF resistance in order to obtain a display without pixel defects. Is required.
従来の薄膜トランジスタは、第１図の断面図に示す様に
、ゲート金属２が付いたガラス等の絶縁性基板上１に、
プラズマＣＶＤ法を用いて、例えば窒化シリコン３．ｎ
−非晶質シリコン層４．＃）ん等を０．１〜１チ程度の
濃度にドープしたｎ＋非晶質シリコン層６を順次形成し
、その後ソース７゜ドレイン８電極を形成し、ゲート金
属部に対応する上部のｎ＋非晶質シリコンをエツチング
して薄膜トランジスタを構成にしていた。また、この薄
膜のトランジスタの表面を安定化させるために、窒化シ
リコン等からなる絶縁層９を設置している。As shown in the cross-sectional view of FIG. 1, a conventional thin film transistor has a gate metal 2 on an insulating substrate 1 such as glass.
Using a plasma CVD method, for example, silicon nitride 3. n
-Amorphous silicon layer 4. An n+ amorphous silicon layer 6 doped with #) etc. to a concentration of about 0.1 to 1 is sequentially formed, and then source 7 and drain 8 electrodes are formed, and the upper n+ amorphous silicon layer 6 corresponding to the gate metal part is formed. Thin film transistors were constructed by etching crystalline silicon. Further, in order to stabilize the surface of this thin film transistor, an insulating layer 9 made of silicon nitride or the like is provided.
しかし、とのｎ＋非晶質シリコン（６）ヲエッチングす
る工程や、窒化シリコン等のバッシペーシラン膜（４）
全形成する時に、ｎ−非晶質シリコン層４表面の抵抗値
が減少し、薄膜トランジスタのＯＦＦ抵抗が小さくなり
、平面ディスプレイに用いた時に画像欠陥となって歩留
りを低下させるという欠点があった。However, there is a process of etching the n+ amorphous silicon (6), and a process of etching the n+ amorphous silicon (4)
When completely formed, the resistance value of the surface of the n-amorphous silicon layer 4 decreases, the OFF resistance of the thin film transistor decreases, and when used in a flat display, image defects occur and the yield decreases.
例えば、従来の薄膜トランジスタを用いた場合、平均Ｏ
Ｎ電流３．４ｘｌＯ’Ａ、平均ＯＦＦ電流２．３ＸＩＯ
”Ａであり、平均的な０ＮＯＦＦ比は十分あるものの、
ＯＦＦ電流１Ｏ−１０Ａ以上の素子が全体の４チも含ま
れていた。For example, when using conventional thin film transistors, the average O
N current 3.4xlO'A, average OFF current 2.3XIO
“A, and although the average 0NOFF ratio is sufficient,
A total of four devices had an OFF current of 10-10A or more.
（発明の目的）
本発明の目的は、このような従来の欠点を除き、ＯＦＦ
抵抗が高く、安定に製造できる薄膜トランジスタを提供
することにある。(Object of the Invention) The object of the present invention is to eliminate such conventional drawbacks and to
An object of the present invention is to provide a thin film transistor that has high resistance and can be manufactured stably.
（発明の構成）
本発明の構成は、ゲート金属層を上面に設けた絶縁性基
板上にゲート絶縁膜と非晶質シリコンを基体とした半導
体層とを積層しこの積層上にオーミック層、ソース電極
およびドレイン電極を配設した薄膜トランジスタにおい
て、前記半導体層に９．１１）Ｐｍ以上１１０００ｐｐ
以下の濃度の硼素を含みかつ窒素または酸素を含む非晶
質シリコン層とが含まれることを特徴とする。(Structure of the Invention) The structure of the present invention is such that a gate insulating film and a semiconductor layer based on amorphous silicon are laminated on an insulating substrate having a gate metal layer on the top surface, and an ohmic layer and a source layer are formed on this laminated layer. In a thin film transistor in which an electrode and a drain electrode are provided, the semiconductor layer contains 9.11) Pm or more of 11,000 ppp or more.
It is characterized by containing an amorphous silicon layer containing boron at the following concentration and containing nitrogen or oxygen.
（実施例） 以下本発明を図面によシ詳細に説明する。(Example) The present invention will be explained in detail below with reference to the drawings.
第２図は本発明の実施例を示す断面図である。FIG. 2 is a sectional view showing an embodiment of the present invention.
本実施例は、まずガラス基板１上にゲート金属であるモ
リブデン電極２を１０００人真空蒸着し、フォトリソグ
ラフィによって幅１５μｍに加工する。In this example, first, a molybdenum electrode 2, which is a gate metal, is vacuum-deposited by 1000 people on a glass substrate 1, and then processed into a width of 15 μm by photolithography.
続いて、シランガスとアンモニア、窒素ガスの混合ガス
をプラズマＣＶＤ装置を用いてグロー放電分解させＳ
ｉ Ｎ、絶縁層３を５０００人形成する。次に、同じ装
置内で連続してシランガスのグロー放電分解によυｎ−
非晶質シリコン層４を１５００人形成し、窒素とシラン
とを１対１に混合したガスにディボランを５０ ｐｐｍ
ドープした混合ガスをグロー放電分解し非晶質シリコン
層５ｉ８００人形成し、シランにホスフィンｆ２０００
ｐｐｍドープしたｎ＋非晶質シリコン層６’１８００人
形成する。続いて、ソース電極７．ドレイン電極８とな
るモリブデン層を２０００人形成し、ゲート長が４０μ
ｍ１ ゲート幅が１０μｍになるようにドライエツチン
グしてソース、ドレイン電極７，８およびｎ＋非晶質シ
リコン層６を形成しトランジスタを完成させる。Next, a mixed gas of silane gas, ammonia, and nitrogen gas is decomposed by glow discharge using a plasma CVD device.
iN, 5000 people formed the insulating layer 3. Next, υn-
1,500 layers of amorphous silicon layer 4 were formed, and 50 ppm of diborane was added to a gas containing a 1:1 mixture of nitrogen and silane.
The doped mixed gas was decomposed by glow discharge to form an amorphous silicon layer of 5i800m, and phosphine f2000 was added to the silane.
A 1800 ppm doped n+ amorphous silicon layer 6' is formed. Next, source electrode 7. 2000 molybdenum layers were formed to become the drain electrode 8, and the gate length was 40μ.
m1 Dry etching is performed so that the gate width is 10 μm to form source and drain electrodes 7 and 8 and an n+ amorphous silicon layer 6 to complete the transistor.
サラニ、パッジペイジオン膜９となる酸化シリコンをス
パッタ法によって形成する。Silicon oxide, which will become the SaraniPudgeon film 9, is formed by sputtering.
なお、こζでは高抵抗非晶質シリコンの形成において非
晶質Ｓ ｉ Ｎｘ を用いているが、シランと酸素、シ
ランとＮＯ２あるいはシランとＮ２０、シランとＣＯ２
等の混合ガスによって形成される高抵抗非晶質シリコン
層でおってもかまわない。Note that in this ζ, amorphous Si Nx is used to form high-resistance amorphous silicon, but silane and oxygen, silane and NO2, silane and N20, silane and CO2
A high-resistance amorphous silicon layer formed by a mixed gas such as the like may also be used.
従来の薄膜トランジスタのＯＦＦ抵抗低下の原因は、抵
抗率１０８〜１０９Ω−αのｎ−非晶質シリコン層４が
、ドライエツチング時のプラズマ損傷やよごれ等により
その抵抗率が１桁から２桁程度小さくなってしまったも
のと考えられる。このため本発明においては、非晶質シ
リコン層（４，６） 内に、硼素と窒素または酸素のう
ちの一元素とを含みｎ−非晶質シリコンの抵抗率よシ１
桁以上大きい１０９〜１０１４Ω−備の高抵抗非晶質Ｓ
ｉｎ、層（５）を設けることによシ、ドライエツチング
や汚れなどによυその抵抗率が１〜２桁小さくなったと
しても十分な抵抗率を維持させるようにしたものである
。The reason for the decrease in OFF resistance of conventional thin film transistors is that the resistivity of the n-amorphous silicon layer 4, which has a resistivity of 108 to 109 Ω-α, decreases by about one to two orders of magnitude due to plasma damage and dirt during dry etching. It is thought that this has happened. Therefore, in the present invention, the amorphous silicon layer (4, 6) contains boron and one element of nitrogen or oxygen, which increases the resistivity of n-amorphous silicon.
High resistance amorphous S with an order of magnitude higher 109~1014Ω
By providing the layer (5), a sufficient resistivity can be maintained even if the resistivity decreases by one to two orders of magnitude due to dry etching, dirt, etc.
通常、硼素をドープした非晶質シリコンを薄膜トランジ
スタに用いる時に電子の走向性を阻害することがあるが
、本発明においては、ゲート絶縁膜３と接し、チャネル
部を形成する非晶質シリコンには電子の走向性の良いｎ
−非晶質シリコン層（一般的にはドープしない非晶質シ
リコン層）４を用い、ソース、ドレイン電極とのオーミ
ックコンタクトにはｎ＋非晶質シリコン層６を用いてい
るため、電子の走向性が阻害されずＯＮ抵抗が低く、か
つＯＮ、ＯＦＦ比の高い薄膜トランジスタが得られる。Normally, when amorphous silicon doped with boron is used in a thin film transistor, electron mobility may be inhibited, but in the present invention, the amorphous silicon that is in contact with the gate insulating film 3 and forms the channel portion n with good electron transportability
- Since an amorphous silicon layer (generally an undoped amorphous silicon layer) 4 is used, and an n+ amorphous silicon layer 6 is used for ohmic contact with the source and drain electrodes, the electron trajectory is A thin film transistor with low ON resistance and high ON/OFF ratio without being inhibited can be obtained.
また、酸素や窒素を非晶質シリコン層に含ませることは
、硼素をドープすることによって低下した電子の走向性
を回復させる働きもあるのでその特性が改善される。Furthermore, the inclusion of oxygen or nitrogen in the amorphous silicon layer has the effect of restoring the electron transport properties that have been reduced by doping with boron, thereby improving its properties.
このようにして形成された薄膜トランジスタを用いて、
１２８Ｘ６４素子の液晶駆動用薄膜トランジスタアレイ
を試作してその静特性合評価した。Using the thin film transistor formed in this way,
A prototype thin film transistor array for driving a liquid crystal with 128×64 elements was fabricated and its static characteristics were evaluated.
その結果、ゲート電圧１５ｖ１ ソースドレイン間電圧
１５ＶでＯ平均ＯＮ電流ｔｉ２．２Ｘ１０ ’Ａ。As a result, when the gate voltage is 15v1 and the source-drain voltage is 15V, the average ON current is 2.2x10'A.
平均ＯＦＦ電流は１．Ｉ Ｘ １０ ”Ａであシ、画像
欠陥のおそれのあるｌＸｌ０−”Ａ以上のＯＦＦ電流が
流れる素子は全体の０．１チ以下であシ、従来の薄膜ト
ランジスタの割合（４％）に対して大幅に歩留シを改善
している。The average OFF current is 1. IX10"A, and the elements that flow an OFF current of 1X10-"A or more, which may cause image defects, must be less than 0.1 inch of the total, compared to the proportion of conventional thin film transistors (4%). Yield has been significantly improved.
（発明の効果）
以上説明したように１本発明によれば、ＯＦＦ電流の小
さい薄膜トランジスタを安定に製造することが出来、こ
の薄膜トランジスタを多数用いたディスプレイ装置の歩
留ｂｔ−上げることが出来る。(Effects of the Invention) As described above, according to the present invention, thin film transistors with small OFF current can be stably manufactured, and the yield of display devices using a large number of these thin film transistors can be increased.
第１図は従来の薄膜トランジスタの断面図、第２図は本
発明の一実施例の断面図である。図において、
■・・・・・・絶縁性基板、２・・・・・・ゲート電極
、３・・・・・・絶縁体層、４・・・・・・ｎ−非晶質
シリコン半導体層、５・・・・・・硼素と酸素または窒
素とを含む非晶質シリコン半導体層、６・・・・・・ｎ
＋非晶質シリコン半導体層、７・・・・・・ソース電極
、８・・・・・・ドレイン電極、９６．１０１．バ、シ
ペイション膜、
である。
゛ぐ−、７′
卒１瓢FIG. 1 is a sectional view of a conventional thin film transistor, and FIG. 2 is a sectional view of an embodiment of the present invention. In the figure, ■...Insulating substrate, 2...Gate electrode, 3...Insulator layer, 4...N-amorphous silicon semiconductor layer , 5...Amorphous silicon semiconductor layer containing boron and oxygen or nitrogen, 6...n
+Amorphous silicon semiconductor layer, 7...source electrode, 8...drain electrode, 96.101. It is a cypation membrane.゛gu-, 7' graduation 1 gourd
Claims (1)
膜と非晶質シリコンを基体とした半導体層とを積層しこ
の積層上にオーミック層、ソース電極およびドレイン電
極を配設した薄膜トランジスタにおいて、前記半導体層
内に０． ｌｐｐｍ以上１１０００ｐｐ以下の硼素を含
みかつ窒素または酸素を含む非晶質シリコン層が含まれ
ることをＩｒｆｇ、とじた薄膜トランジスタ。In a thin film transistor, a gate insulating film and a semiconductor layer based on amorphous silicon are laminated on an insulating substrate having a gate metal layer on the top surface, and an ohmic layer, a source electrode, and a drain electrode are disposed on this laminated layer. 0.0 within the semiconductor layer. A thin film transistor defined by Irfg to include an amorphous silicon layer containing 1 ppm to 11000 ppm of boron and nitrogen or oxygen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5563784A JPS60198864A (en) | 1984-03-23 | 1984-03-23 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5563784A JPS60198864A (en) | 1984-03-23 | 1984-03-23 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60198864A true JPS60198864A (en) | 1985-10-08 |
Family
ID=13004313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5563784A Pending JPS60198864A (en) | 1984-03-23 | 1984-03-23 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60198864A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02275672A (en) * | 1989-03-30 | 1990-11-09 | Nippon Steel Corp | Thin film transistor |
| JP2009212497A (en) * | 2007-03-27 | 2009-09-17 | Fujifilm Corp | Thin film field effect transistor and display using the same |
-
1984
- 1984-03-23 JP JP5563784A patent/JPS60198864A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02275672A (en) * | 1989-03-30 | 1990-11-09 | Nippon Steel Corp | Thin film transistor |
| JP2009212497A (en) * | 2007-03-27 | 2009-09-17 | Fujifilm Corp | Thin film field effect transistor and display using the same |
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