JPH01144682A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To prevent the contamination and deterioration of the surface of an i-layer, and to improve the stability of TFT characteristics and reliability by etching a back channel section a-Si film and forming a modified layer onto the surface of the i-layer by plasma discharge in an atmosphere in which there is one kind or more of N, O, C and B. CONSTITUTION:A gate electrode 20 composed of NiCr is shaped onto a borosilicate glass substrate 10. An silicon nitride film and a gate insulating film 30 are formed onto the gate electrode 20 through plasma CVD. An i-layer 40 as an a-Si hydride film and an n<+> layer 50 are shaped simultaneously through plasma CVD, and ITO and Cr are shaped onto the layer 50 as source-drain electrode materials 670. Cr and ITO are wet-etched, using a resist 500 as a mask, thus forming a source electrode 60 and a drain electrode 70. The n<+> layer 50 is dry-etched by employing a gas in which O2 is added to CCl4 gas, the i-layer 40 is also etched slightly, and the surface 803 of the i-layer is exposed. Plasma discharge is conducted by using O2 gas, and the surface 803 is exposed and an oxidized surface modified layer 80 is shaped. Accordingly, the resist 500 is peeled, thus finishing a TFT.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an inverted staggered structure using amorphous silicon;
Regarding the manufacturing method of channel-grooved thin film transistors,
In particular, the present invention relates to a method for manufacturing a thin film transistor, including a back channel processing method that provides good stability and high reliability.

[Conventional technology]

Thin film transistors (TF'T) using hydrogenated amorphous silicon (a-8i) can be formed on large-area substrates at low temperatures, so they are used as switching elements in long image sensors and large-area, large-capacity liquid crystal display devices. is being put into practical use in the form of a large number of integrated elements on low-cost substrates such as glass.

For a-8i TFTs, conformal structures such as forward staggered and reverse staggered structures are known based on the difference in the order of stacking thin films on the substrate. Among these, the inverted staggered structure is relatively often adopted due to its manufacturing advantages and the stability of TPT characteristics, and the channel digging type is more popular than the terminal digging type, which has different ohmic contact formation methods. It is widely adopted.

An outline of the manufacturing process of the channel dug inverted staggered A-3i TFT is shown in FIGS. 5(I) to (III).

A step of patterning a Ct gate electrode 20 on a glass substrate 10, and a step of patterning a Ct gate electrode 20 on the glass substrate 10, and then patterning a Ct gate electrode 20 on it.
gate insulating film 30, one layer 40 of a-8i film, and n+ layer 5
A process of decomposing and stacking SiH4 etc. by plasma CVD, a process of forming a source/drain electrode material 670 such as ITO or C1 thereon, and a process of forming a resist 500 for patterning the source/drain electrodes.
FIG. 5(1) shows the product that has gone through the process of applying the .

After that, as shown in (II), after the process of etching ITO and C2 and removing the source/drain electrode material 670 of the back channel part 90, the n+ layer 5 of the a-8i film is removed.
0 is exposed on the surface.

In the case of a channel digging type TPT, in addition to separating the source/drain electrodes 670 as shown in (II), the N+ layer 50 of the a-8i film exposed in the back channel part 90 is dug out by etching, as shown in FIG. The removal process is performed as shown in III). Dry etching is often used to etch the n+ layer 50, and it is often a process of digging down to just one layer 40.

In the conventional TPT manufacturing method, after the process shown in (III), the process is completed by removing the resist 500, and the structure shown in FIG. 6 is obtained.

[Problem that the invention seeks to solve]

As shown in FIG. 6, the method for manufacturing the above-described inverted staggered A-8i TFT with channel trenching is a manufacturing method in which the back channel portion 90 between the source electrode 60 and the drain electrode 70 is the uppermost surface.

As a result, the back channel portion 90 has the i-layer a-8i surface 8
03 is exposed. Therefore, surface contamination directly causes contamination of the i-layer a-8i surface 803, and becomes a factor that causes a change in the potential of the back channel 90. Therefore, the conventional channel digging reverse staggered a-
It has been difficult to produce a reliable device with stable TPT characteristics using the 8i TFT manufacturing method.

As an example of a solution to this problem, it may be possible to form a SiOx or SiN film to have a passivation effect on the back channel portion to prevent contamination and stabilize the device. However, in the boat fishing manufacturing process, the process of forming the source electrode and drain electrode, the process of etching the n+ layer of the a-8i film to form the back channel part, and the process of forming the above-mentioned passivation film are different. It must be done using completely different manufacturing equipment and is a separate process.

Therefore, before forming the passivation film, a-8i
This results in the i-layer of the membrane being exposed to the outside air and working environment.
These effects are incorporated into the interface between the i-layer and the passivation film, making it difficult to obtain a complete passivation effect.

For example, as shown in FIG. 7(b), compared to the initial TPT characteristics 42, the conventional product has TPT characteristics after forming a passivation film after forming a back channel, or for example, after disassembling and inspecting a liquid crystal display element after assembling it. The TPT characteristic 44 at the time had a drawback that the current value in the OFF region increased significantly, resulting in insufficient switching characteristics of a display element.

Therefore, an object of the present invention is to provide a method for manufacturing TPT having good stability and reproducibility of characteristics and high reliability.

[Means for solving problems]

The method for manufacturing a thin film transistor of the present invention includes forming a gate electrode, a gate insulating film, an amorphous silicon film, and a gate electrode on an insulating substrate.
During the process of manufacturing an inverted staggered amorphous silicon thin film transistor in which source and drain electrodes are formed in this order, after a channel digging process in which the n+ layer of the amorphous silicon film in the back channel area between the source and drain electrodes is etched, By plasma discharge in an atmosphere containing at least one of N, O%C, and B,
The method includes a step of exposing the i-layer surface of the etched amorphous silicon film to form a degraded layer.

−6= Compared to the conventional thin film transistor manufacturing method described above,
In the present invention, the surface of the amorphous silin film i-layer in the back channel part is exposed to plasma discharge to actively
It has a step of altering the quality so that at least one component of B is present. For this reason, unlike conventional passivation films, which are laminated in a post-process, there is a step in which the i-layer itself of the TPT channel active layer is made into an altered layer.
The interface is not contaminated and is a step in which the interface is created in the i-layer. Also, as a back channel process, n+
The layer is also easier than the process of making an oxide film, and furthermore,
This method is simpler than the doping process by ion implantation, causes less damage, does not cause characteristic deterioration, and can be more effective.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram showing a process order for explaining a manufacturing method according to an embodiment of the present invention.

In FIG. 1(I), N is applied on the borosilicate glass substrate 10.
A gate electrode 20 made of iC is provided with a thickness of 1500 nm. Plasma CVD on this
A gate insulating film 30 is provided by etching a silicon nitride (SiN) film to a thickness of 3000 nm. At the same time, one layer of hydrogenated a-Si film 40 20
00 layers and 100 layers of n+ layer 50 are sequentially formed, and 10 layers of ITO are formed as source/drain electrode material 670 thereon.
00 people and 2000 C7 people have been formed.

A resist 500 is provided thereon for performing butter coating of the source/drain electrodes.

In the next step, as shown in FIG. 1(II), C1 and ITO are wet-etched using the resist 500 as a mask to form a source electrode 60 and a drain electrode 70.

As a subsequent step, as shown in FIG. 1 (III), using the same resist 500 as it is, the back channel portion 9 is
Dry etching is performed on the a-8in+ layer 5o present at 0.0. This dry etching is performed using (l-based gas, e.g.
A gas obtained by adding 02 to Cfl h gas is used. Further, etching is performed until one layer 40 of a-Si is slightly etched, including a margin. Therefore, in the back channel section 90, the a-8i surface 803 of the i layer is exposed.

In the present invention, the next step is as shown in FIG.
As shown in V), the following plasma treatment step is added.

After the etching gas used for dry etching is completely exhausted, a plasma discharge is generated using 0□ gas to expose the i-layer a-8i surface 803 of the back channel portion 90 immediately after the etching for about 10 to 15 minutes. Through this plasma treatment, the back channel portion 90 becomes a surface-altered layer 80 in which the a-8i surface is oxidized.

Through the above steps, the resist 500 is separated, and finally a TPT having a cross-sectional shape as shown in FIG. 3 is completed.

As mentioned above, following dry etching, plasma processing can be performed by switching the gas without taking it out to the atmosphere.
iDoes not stain the surface. Even if manufacturing equipment in which etching and plasma processing are separated is used, the interface between the i-layer of a-8i and the surface-altered layer should be provided inside the etched surface in the depth direction after plasma processing. ℃, the impact can be significantly reduced.

Note that the gas used for this plasma treatment is ML
Acid L N2O, ammonia, methane, ethane, propane, diborane gas, etc. may be used alone, or a mixed gas using nitrogen or oxygen gas as a carrier gas may be used.

When these were used, the above process order was the same, but the resulting surface altered layer 80 was different, and N, O, C, B, etc. were detected in each of them as a result of Ouch analysis.

A TPT having such a surface-altered layer 80 is shown in FIG.
As shown in a), the TPT characteristics hardly changed between the initial manufacturing stage 42 and when disassembled and inspected 41 after assembly into a liquid crystal display device, making it extremely stable. This is because in the embodiment of the present invention, even if the back channel portion 90 is not provided with a passivation film, the surface-altered layer 80 is formed, so it has a characteristic that it will not deteriorate in the next process or the display device assembly process. .

This example shows another example of the present invention, and is the same as the previous example up to the middle of the manufacturing process.

It was manufactured in the same manner as in the previous examples shown in FIGS. 1 (I) to (IV). Thereafter, the steps shown in FIG. 2 were added in this example. In FIG. 2(V), after performing the steps up to FIG. 1(IV), the resist 500 is peeled off and a Sin or Si film is formed by sputtering or P-CVD.
An interlayer insulating film 100 was formed by forming a film such as Nx or polyimide using a coater. After that process, as shown in FIG. 2 (Vl), a light shielding film 110 such as C1 or Aρ is formed by 1500 to 2000 people, and a resist 500 is formed to form a desired pattern.

As described above, in this example, the step of forming the interlayer insulating film 10O and the light shielding film 11O after forming the surface-altered layer 80 (similar to Example 1) is added. As a result, the final form of the TP has the structure shown in Figure 4.
T can be manufactured.

As in the conventional case, the i-layer a-3i surface (803 in FIG. 5(I))
), if these interlayer insulating films and light shielding films are provided, TPT
Although the manufacturing method caused variations in characteristics and was poor in reproducibility, according to the manufacturing method including the step of forming the surface-altered layer 80 as in the example of the present invention, the seventh As shown in Figure (a), it had the characteristic that the stability of TPT characteristics was maintained.

This is considered to be the effect of protecting the back channel portion with the surface-altered layer before the step of forming the interlayer insulating film. In the case where no light shielding film is provided and only an interlayer insulating film is provided, this interlayer insulating film is equivalent to a commonly-called passivation film, and the same effect is obtained in this case as well.

〔Effect of the invention〕

As explained above, the present invention adds a step of forming a surface-altered layer in the back channel part of TPT,
The surface of the i-layer, which is the active layer of a-8i, was not contaminated or deteriorated, and a manufacturing method with high stability and reliability of TPT characteristics could be achieved. Further, similar effects can be obtained in a TPT manufacturing method in which a passivation film or a light shielding film is provided.

[Brief explanation of the drawing]

Figures 1 (1) to (IV) are cross-sectional views showing the process order for explaining a manufacturing method according to an embodiment of the present invention, and Figure 2 (I
), (It) is a cross-sectional view showing the process order for explaining another embodiment of the manufacturing method of the present invention, FIG. 3 is a cross-sectional view showing the final structure after the steps in FIG. 1, and FIG. Figures 1 and 2
Cross-sectional view showing the final structure after going through the steps shown in the figure, Figure 5 (1) -
(III) is a sectional view showing the process order for explaining the conventional manufacturing method, FIG. 6 is a sectional view showing the final structure by the conventional manufacturing method, and FIGS. 7(a) and (b) are FIG. 3 is a characteristic diagram for explaining changes in TPT characteristics of the conventional and the present invention. 50-n”a-8i membrane, 803-i, a-8i surface, 9
0... Back channel part, 80... Surface altered layer, 100... Interlayer insulating film, 110...
...Light-shielding film. Agent Patent Attorney Shinsuke Uchihara 7 (α), (b) Gate Denjin

Claims (1)

[Claims] In a method for manufacturing an inverted staggered amorphous silicon thin film transistor in which a gate electrode, a gate insulating film, an amorphous silicon film, a source and a drain electrode are formed in this order on an insulating substrate, an amorphous silicon film is formed in the back channel region between the source electrode and the drain electrode. After the channel digging process that etches the high impurity concentration layer of the film, N
A method for manufacturing a thin film transistor, comprising the step of exposing the i-layer surface of an etched amorphous silicon film to form an altered layer by plasma discharge in an atmosphere containing at least one of O, C, and B. .