JPH02295132A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To make the dimensions of opening at source/drain electrode film smaller than the width of a channel protection film by using different resist films when etching the channel protection film and when forming a pattern of the source/drain electrode film. CONSTITUTION:After etching a channel protection film 4 with a first resist film 5 as a mask, the above first resist film 5 is eliminated, a positive type resist is applied, and rear-surface exposure is performed to it, thus forming a second resist film 5' which is self-aligned to a gate electrode G. At that time, exposure strength is made larger than the exposure for forming the first resist film 5 used for etching the channel protection film 4 and introduction of light is increased, thus forming the second resist film 5' with smaller width than that of the first resist film 5. As a result, the edge parts of a source electrode S and a drain electrode D can be overlapped onto the edge part of a channel protection film 4, thus preventing crack from occurring at an operation semiconductor film and a gate insulation film and hence producing TFT with high voltage resistance and improved characteristics.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a thin film transistor for driving a liquid crystal. A first aspect of the present invention aims to provide a manufacturing method in which the ends of the drain electrode D overlap with each other, and a first aspect of the present invention is to provide a manufacturing method in which a gate electrode, a gate insulating film, an active semiconductor film, and a channel protective film are formed on an insulating substrate. Then, a first resist film self-aligned with the gate electrode is sequentially formed on the channel protection crotch, and the exposed portion of the channel protection film is removed using the first resist film as a mask. After removing the first resist film, a second resist film is formed on the channel protective film to expose the end portions of the channel protective film, and then, after forming a source/drain electroplating film, The configuration includes a step of removing the second resist film and lifting off the source/drain electrode film deposited thereon.
An active semiconductor film and a channel protective film are formed, and then a first resist film self-aligned to the gate electrode is formed on the channel protective film, and the exposed portion of the channel protective film is formed using the first resist film as a mask. and then the first
After removing the resist film, a source/drain electrode film is formed on the insulating substrate including on the channel protective film, and then a second electrode film having an opening on a region excluding the end of the channel protective film is formed. The second resist film is used as a mask to remove the source/drain electrode film exposed in the opening of the second resist film.

[Industrial application field]

The present invention relates to a method of manufacturing a thin film transistor for driving a liquid crystal.

2. Description of the Related Art In recent years, flat display devices capable of full-color display have been in demand for everything from pocket TVs to office automation terminal devices.

However, in a liquid crystal display device, hundreds of thousands of thin film transistors (TPTs) are formed on a single glass substrate, and all of them must operate without defects. Therefore, TPT
There is an urgent need to develop a manufacturing method that can reduce short circuits and disconnection defects between each electrode.

? Conventional technology] FIG. 4 shows a conventional method for manufacturing a self-aligned TPT.

A gate electrode G made of a Ti film is placed on a transparent insulating substrate L.
After forming the SiN film 2 with a thickness of about 3000, the thickness i
Plasma chemical vapor deposition (P-CVD) to form a-Si:H film 3 with a thickness of less than 1,000 μm and a SiO film 4 with a thickness of less than 1,000 μm.
The film is continuously formed by the method (see figure (a)).

Next, a positive photoresist is applied on the Sing film 4 to form a resist film 5, and this resist film 5 is irradiated with ultraviolet rays from the back surface of the insulating substrate l. As a result, the portion masked by the gate electrode G becomes the unexposed portion 11. The other part becomes the exposed part 12 [see figure (b)], and the exposed part 12 is removed by development processing, and the unexposed part 1
1 remains.

Using this resist film 5 as a mask, the Sin. The film 4 is etched, and the exposed portion of the Sin2 film 4 is removed [see figure (C)].

As the source/drain electrode film 10, n”a-Si:H
The film 6 and the Ti film 7 are successively formed by the P-CVD method [see figure (d)].

Next, the resist film 5 is removed and the source/drain electrode film 10 attached thereon is lifted off [see t in the same figure.
see el].

? [Problems to be Solved by the Invention] In the conventional method for manufacturing a self-aligned TPT described above, as shown in FIG.
■Membrane 4 and source electrode S. A minute gap 8 is formed at the boundary with the drain electrode D.

If such a gap 8 is formed, the reliability or manufacturing yield of the TPT will be reduced as described below.

Starting from the gap 8, the underlying a-Si:H film 3 and Si
The N film 2 becomes easily cracked. As a result, the gate electrode G and the source electrode S. The electrical breakdown voltage between the drain electrodes D decreases.

Also, to reduce the photocurrent of TPT, aSt
It is effective to reduce the thickness of the :H film 3 to a thickness of 100 layers or less, but if the gap 8 is present, the a-Si:H film 3 will be thinned in the subsequent process.
The membrane 3 may be attacked and the TPT properties deteriorate.

In the conventional manufacturing method, such a gap 8 is created by using the resist film 5 used as a mask when forming the channel protection film 4 to form the source electrode S. This occurs because the width of the channel protective film 4 and the distance between the source electrode S and the drain electrode D are the same since the drain electrode D is used as is for lift-off when forming the drain electrode D.

In the present invention, the distance between the source electrode S and the drain electrode D is
It is an object of the present invention to provide a manufacturing method that allows the width to be made narrower than the width of a channel protective film.

[Means to solve the problem]

The present invention is shown in FIG. 1(a). (b) and (Cl), by making the resist film 5 when etching the channel protection film 4 different from the resist film 5 when patterning the source/drain electrode film 10, the source/drain electrode film 10 can be patterned. The opening dimension of the drain electrode film IO is made smaller than the width of the channel protective film 4.

That is, the first aspect of the present invention is to form a first resist film 5 that is self-aligned to the gate electrode G by irradiating ultraviolet rays from the back surface of the insulating substrate L, as shown in FIGS. death,
After etching the channel protective film 4 using this first resist film 5 as a mask, the first resist film 5 is removed, and then a positive resist is applied and back exposed. A self-aligned second resist film 5' is formed.

At this time, the exposure intensity is set higher than that used for the exposure for forming the first resist film 5 used for etching the channel protection 11#4, and the light wraparound is increased, so that the first resist film 5 is Second resist Jl with smaller width!
5', a source/drain electrode film 10 is formed, and lift-off is performed to overlap the ends of the source electrode S and the drain electrode D with the ends of the channel protective film 4.

Further, the second aspect of the present invention is as shown in FIG.
The resist film 5 is removed, and then the source/drain electrode film 10 is formed, and the edges of the channel protection film 4 are removed.
A third resist film 5'' having an opening in the region is formed, and using the third resist film 5'' as a mask, the source/drain electrode film exposed within the opening is removed.

By the above manufacturing method, the source electrode S, the drain electrode D
The end of the channel protective film 4 is overlapped with the end of the channel protective film 4.

[For production]

As described above, the resist film serving as a mask during etching of the channel protective film 4 and the source electrode S. By making a separate resist film that serves as a mask when forming the drain electrode D, and making the width or opening width of the resist film that defines the distance between the source electrode S and the drain electrode D smaller than the width of the channel protective film. , the ends of the source electrode S and drain electrode D can not overlap the ends of the channel protective film 4.

As a result, there are no cracks in the operating semiconductor film and gate insulating film, and therefore, TPT with high breakdown voltage and good characteristics can be obtained.
can be created.

(Example) A first example of the present invention will be described below with reference to FIGS. 2(a) to (el).

The same figure (al, (bl is the above-mentioned figure 1 (bl, (Cl
This is the same diagram as in the previous figure, and the manufacturing process up to this point is no different from the conventional one.

That is, a gate electrode G (
The thickness is approximately 800 people or less).

On this gate electrode G, a SiN film 2 is formed as a gate insulating film and an a-Si film is formed as an active semiconductor film by P-CVD method.
A H film and a Sing film 4 serving as a channel protection film are successively formed. The thickness of each of the above films may be set to a normal value, with the thickness of the SiN film 2 being about 3000 or less, and the thickness of the a-34:H film 3 being about 100 to 1
000 people, Sin. Membrane 4 is about too thick.

Next, a positive photoresist is applied onto the SiOz film 4, and ultraviolet rays are irradiated from the back surface of the glass substrate using the gate electrode G as a mask. As a result, the exposed portion l2 other than the unexposed portion l1 masked by the gate electrode G is removed by the development process, and the unexposed portion 11 is replaced by the first resist film 5.
remain as.

Next, using this first resist film 5 as a mask, a
, the film 4 is etched and the exposed portion thereof is removed as shown in FIG.
b) is obtained.

In this embodiment, the first resist film 5 is then removed, a positive type photoresist is applied again, and this is irradiated with ultraviolet light from the back side of the insulating substrate l using the gate electrode G as a mask. Unexposed area 11 masked by G
The exposed areas 12' other than '' are removed by a development process, and a second resist film 5' consisting of the unexposed areas 11' is formed.

In this step, the exposure intensity when forming the second resist film 5 is set to 3 times the exposure intensity when forming the first resist film 5.
~4 times. When the thickness of the resist film is approximately 1.5 μm, when the first resist film 5 is formed? Exposure energy density is approximately 9
0mJ/cm", and the exposure energy density when forming the second resist film 5" in this step is 270-3, which is 3 to 4 times that.
60mJ/cm".

The energy density of the incident light on the substrate during the above exposure is
:H film 3 absorbs light, so the value must be greater than the above value. For example, when the thickness of the aSi:H film 3 is 200 people, it needs to be about 20 times the above-mentioned value.

To increase the exposure intensity, the exposure time may be increased;
Alternatively, the light intensity may be increased.

By increasing the energy given to the photoresist in this way, the amount of light that passes through the a-Si:H film 3, enters the resist film, and wraps around inside the end of the gate electrode G is reduced by the first resist film 5. It increases from the time of exposure. Therefore, the exposed portion 12' is located inside the end of the gate electrode G compared to the previous time.
The unexposed portion 11' becomes smaller by that amount, and a second resist film 5' having a width narrower than the SiO2 film 4 is formed as shown in FIG. 2 (Cl).

? After performing a development process on the surface of the a-Si:H film 3, the natural oxide film on the surface of the a-Si:H film 3 is removed, and a n″a-Si:}{film 6 (thickness approximately ~500 mm) is formed as the source/drain electrode film 10. Then, a Ti film 7 (approximately ~too thick) is formed (see figure d+).

Since the second resist film 5' is narrower than the Sin film 4, the end portion of the stow film 4 is exposed.

Therefore, the source/drain electrode film 10 has a Sin. A film is also formed on the exposed end surface of the film 4, and both ends overlap.

After that, the second resist film 5' is removed, the source/drain electrode film lO attached thereon is lifted off, and the second resist film 5' is removed.
As shown in FIG. 1, a structure is obtained in which the ends of the source electrode S and the drain electrode D are overlapped on the ends of the SiO2 film 4.

As described above, in the thin film transistor manufactured in this example, there is no gap 8 at the boundary between the channel protective film and the source electrode S and drain electrode D.

Therefore, there are no cracks in the active semiconductor film 3 and the gate insulating film 2, and a thin film transistor with high breakdown voltage and high reliability can be provided. In addition, in this example, a large area can be achieved without sacrificing the advantages of the self-alignment method. It is possible to form high-definition patterns. Next, a second embodiment of the present invention will be described with reference to FIGS. 3(a) to (el).

The same figure (al, (bl) is the above-mentioned figure 2 (a). (bl
This figure is the same as that of the first embodiment, and in this embodiment, the steps up to etching the channel protective film of Sin and the film 4 are the same as in the first embodiment. Therefore, Sin. The explanation up to patterning of the film 4 is omitted, and FIGS. 3(C) to (e)
) will explain the subsequent steps.

As shown in the same figure (Cl), after patterning the SiOz film 4, an n″a-Si film 6 as a contact layer and a Ti film 7 as a conductive film are formed on it as a source/drain electrode film 10.
Deposit a film.

Next, as shown in FIG. Therefore, this third resist ?5'' has an opening 13 above the channel for separating the source/drain electrode film 10.

In this embodiment, the width of this opening 13 is
② Form narrower than the width of the film 4.

Using this third resist film 5'' as a mask, the source/drain electrode film 10 and the underlying a-Si:H film 3 are etched to remove the exposed portions.

As mentioned above, the width of the opening 13 is narrower than the width of the S iO t film 4 , so the source electrode S and the drain electrode D formed as a result of the wood processing have their ends on the ends of the S iO z film 4 . remain. Therefore, as in the conventional case, the source electrode S, the drain electrode D and the Sin. No gap is formed between the film 4 and the film 4.

The above etching step is preferably carried out using a mixed gas of CCI4 and 0.sup.C or by active ion etching. According to this etching method, the Ti film 1+n″aSi:H film 6 and a
-Si:H film 3 is etched, but siOztl*
Isn't 4 etched? . Therefore, the third resist film 5''
The Ti film 7 whose surface is exposed in the opening 13 and the lower layer n
``After the a-Si:H film 6 is removed, the SiOz film 4 exposed at the removal mark is not attacked and serves as a stopper film for etching of the channel area.Therefore, undesirable etching is prevented in the channel area. This has the advantage that etching for forming source/drain electrodes can be performed without fear of etching progressing.

After this, the third resist film 5'' is removed.

According to this example obtained in this way, the figure (e)
As shown in the figure, the ends of the source electrode S and the drain electrode D overlap the ends of the SiO film 4, and there is no gap between them. Therefore, thin film transistors with high breakdown voltage and good characteristics can be fabricated using a large area self-alignment method. Moreover, it can be manufactured without impairing suitability to fine patterns.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to manufacture thin film transistors with high breakdown voltage and good characteristics while taking advantage of the self-alignment method's suitability for large area and fine patterning, thereby improving the reliability and manufacturing yield of liquid crystal display devices. improves.

[Brief explanation of drawings]

Figure 1 (a) - (Cl is a diagram explaining the principle of the present invention, Figure 2 (
al to (e) are explanatory diagrams of the first embodiment of the present invention, Fig. 3 ta
) to (Q) are explanatory diagrams of the second embodiment of the present invention, and FIG. 4(a)
-(e) are diagrams explaining problems in the conventional manufacturing method. In the figure, 1 is an insulating substrate (glass substrate), 2 is a gate insulating film (SiN film), and 3 is an active semiconductor film (a-Si:
H film), 4 is a channel protective film (SiQ2 film), 5.5'
, 5'' are first, second, and third resist films, 6 is a contact layer (n'a-Si:H film), 7 is a conductive film (Ti film),
8 is a gap, 10 is a source/drain electrode film, 11 is an unexposed area, 12 is an exposed area, G is a gate electrode, S is a source electrode, L-+. Nopa 1 Gota 2,000 Hatsuro's Reiri-edited Jigawa Dan No. 1 (Preliminary? 1), addressed to p. 7l Principle T 冫萌m Fig. 1 (B/+2)

Claims (2)

[Claims] (1) A gate electrode (G), a gate insulating film (2), an active semiconductor film (3), and a channel protective film (4) are sequentially formed on the insulating substrate (1), and then on the channel protective film. A first resist film (5) self-aligned with the gate electrode was formed, an exposed portion of the channel protection film was removed using the first resist film as a mask, and then the first resist film was removed. After that, a second resist film (5') is formed on the channel protective film to expose the end of the channel protective film, and then a source/drain electrode film (10) is formed, and then the second resist film (5') is formed on the channel protective film. 1. A method for manufacturing a thin film transistor, comprising the steps of removing a resist film and lifting off a source/drain electrode film attached thereon. (2) A gate electrode (G), a gate insulating film (2), an active semiconductor film (3), and a channel protective film (4) are formed on the insulating substrate (1), and then the above-mentioned forming a first resist film (5) self-aligned to the gate electrode; using the first resist film as a mask, removing the exposed portion of the channel protection film; then, after removing the first resist film; , a source/drain electrode film (10) is formed on the insulating substrate including on the channel protective film, and then a third resist film (10) having an opening on a region excluding the edge of the channel protective film is formed. 5'') and removing the source/drain electrode film exposed in the opening of the third resist film using the third resist film as a mask.