JP2503001B2 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistorInfo
- Publication number
- JP2503001B2 JP2503001B2 JP62036987A JP3698787A JP2503001B2 JP 2503001 B2 JP2503001 B2 JP 2503001B2 JP 62036987 A JP62036987 A JP 62036987A JP 3698787 A JP3698787 A JP 3698787A JP 2503001 B2 JP2503001 B2 JP 2503001B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- contact
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 title claims description 8
- 239000010409 thin film Substances 0.000 title claims description 7
- 239000010408 film Substances 0.000 claims description 49
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 47
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明はスタガード型アモルファスシリコン薄膜トラ
ンジスタの製造方法において、ソース・ドレイン電極の
n+a−Siと活性層のａ−Si:Hとのコンタクトを改善する
ため、n+a−Si層などのフォトリソグラフィ工程が終了
した後、上記n+a−Si層表面に予め形成しておいた酸化
膜（SiO2膜）を除去し、しかる後活性層のａ−Si:Hを成
膜するようにしたものである。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method of manufacturing a staggered amorphous silicon thin film transistor, comprising:
In order to improve the contact between n + a-Si and a-Si: H of the active layer, after the photolithography process for the n + a-Si layer etc. is completed, it is formed in advance on the surface of the n + a-Si layer. The oxide film (SiO 2 film) that has been set aside is removed, and then a-Si: H of the active layer is formed.
本発明はスタガード型アモルファスシリコン層よりな
る活性層を有する薄膜トランジスタの製造方法に係り、
特に活性層とその上に積層するゲート絶縁膜の形成方法
に関する。The present invention relates to a method of manufacturing a thin film transistor having an active layer formed of a staggered amorphous silicon layer,
In particular, the present invention relates to a method for forming an active layer and a gate insulating film laminated thereon.
〔従来の技術〕 アクティブマトリクス型液晶パネルのスイッチング素
子として、活性層をアモルファスシリコン（ａ−Si）層
により形成し、逆スタガード型構成とした薄膜トランジ
スタ（TFT）が多く用いられていたが、液晶表示用マト
リクスの製造工程が簡単化できる点で、スタガード型構
造が見直され、その素子特性の向上及び安定化が種々検
討されている。[Prior Art] A thin film transistor (TFT) having an inverted staggered structure in which an active layer is formed of an amorphous silicon (a-Si) layer is often used as a switching element of an active matrix type liquid crystal panel. The staggered structure has been reviewed, and various improvements and stabilizations of its element characteristics have been studied in terms of simplifying the manufacturing process of the use matrix.
第２図により従来のスタガード型TFTの製造方法を、
その製造工程の順に説明する。The conventional staggered TFT manufacturing method is shown in FIG.
The manufacturing steps will be described in order.
同図（ａ）に示すように、絶縁性基板，例えばガラス
基板１の上に、ソース，ドレイン電極となる金属膜２
と、その上にn+a−Si層３を積層し、その上にソース，
ドレイン電極パターニング用のレジスト膜７を形成する
〔同図（ａ）参照〕。As shown in FIG. 3A, a metal film 2 serving as a source / drain electrode is formed on an insulating substrate such as a glass substrate 1.
And the n + a-Si layer 3 is laminated on it, and the source,
A resist film 7 for patterning the drain electrode is formed [see FIG.
次いで上記レジスト膜７をマスクとしてn+a−Si層３
と金属膜２を順次エッチングした後、上記レジスト膜７
を除去する〔同図（ｂ）参照〕。Next, using the resist film 7 as a mask, the n + a-Si layer 3 is formed.
And the metal film 2 are sequentially etched, and then the resist film 7 is formed.
Are removed [see (b) in the figure].
次いでn+a−Si層３に弗素系エッチャンチによる表示
処理を施し、表面の自然酸化膜を除去する（同図（ｃ）
参照〕。Then, the n + a-Si layer 3 is subjected to a display process using a fluorine-based etchant to remove the natural oxide film on the surface (FIG. 2C).
reference〕.
次いで活性層となるａ−Si:H層4,ゲート絶縁膜となる
SiN（窒化シリコン）層５を成膜する（同図（ｄ）参
照〕。なおゲート絶縁膜としては、二酸化シリコン（Si
O2）層等を用いてもよい。Then, the a-Si: H layer 4 which becomes the active layer and the gate insulating film becomes
A SiN (silicon nitride) layer 5 is formed (see FIG. 3D), and the gate insulating film is made of silicon dioxide (Si
An O 2 ) layer or the like may be used.
次いでゲート電極となる導電層６を形成し、その上に
ゲート電極パターニングのためのレジスト膜８を形成す
る〔同図（ｅ）参照〕。Then, a conductive layer 6 to be a gate electrode is formed, and a resist film 8 for patterning the gate electrode is formed thereon (see FIG. 8E).
次いで上記レジスト膜８をマスクとして、導電層6,Si
N層5,a−Si:H層4,n+a−Si層３を順次エッチングした
後、マスクとして用いたレジスト膜８を除去する。〔同
図（ｆ）参照〕。Then, using the resist film 8 as a mask, the conductive layer 6, Si
After the N layer 5, a-Si: H layer 4, and n + a-Si layer 3 are sequentially etched, the resist film 8 used as a mask is removed. [Refer to the same figure (f)].
なお、ここでは導電層６とａ−Si:H層４を一度のフォ
トリソグラフィ工程でパターニングする例を示したが、
勿論これらは別々の工程でエッチングしても良い。Although an example in which the conductive layer 6 and the a-Si: H layer 4 are patterned by a single photolithography process is shown here,
Of course, these may be etched in separate steps.
以上によりスタガード型TFTが完成する。 The staggered TFT is completed by the above.
上記従来のTFTの製造方法では、ソース・ドレイン電
極のエッチングによるパターニングのため、n+a−Si層
上に直接レジスト膜を形成していた。ところが、一度フ
ォトレジストを塗布したn+a−Si層表面は、通常行われ
る自然酸化膜除去のための弗酸系エッチャントによるエ
ッチングを行っても、完全に酸化膜を除去できないこと
が分析等により見出された。In the conventional TFT manufacturing method described above, the resist film is directly formed on the n + a-Si layer for patterning by etching the source / drain electrodes. However, analysis revealed that the surface of the n + a-Si layer that was once coated with photoresist could not be completely removed even by etching with a hydrofluoric acid-based etchant for removing the natural oxide film that is usually performed. Was found.
このような酸化膜が残留したn+a−Si層表面にａ−Si:
H層を形成して作成したTFTの特性は、この二つの層間の
コンタクトが不完全となることから、オン電流が低い場
合が多く、またオン電流の素子間のバラツキが大きいと
いう問題がある。On the surface of the n + a-Si layer where such an oxide film remains, a-Si:
The characteristics of the TFT formed by forming the H layer have a problem that the on-current is often low due to incomplete contact between the two layers, and there is a large variation between the on-current elements.
本発明はコンタクト層表面に酸化膜が残留することが
なく、良好なコンタクト特性が安定して得られる薄膜ト
ランジスタの製造方法を提供することを目的とする。It is an object of the present invention to provide a method of manufacturing a thin film transistor in which an oxide film does not remain on the surface of a contact layer and good contact characteristics can be stably obtained.
本発明においては、n+a−Si層３上に二酸化シリコン
（SiO2）層９を積層しておき、このSiO2膜９を含めてソ
ース・ドレイン電極のパターニングを行い、ａ−Si:H層
４を成長させる前に、上記SiO2膜９をエッチング除去
し、しかる後ａ−Si:H層４を成膜することにより、良好
なコンタクト特性を有するソース・ドレインコンタクト
を形成する。In the present invention, the silicon dioxide (SiO 2 ) layer 9 is laminated on the n + a-Si layer 3, and the source / drain electrodes including the SiO 2 film 9 are patterned to obtain a-Si: H. Before growing the layer 4, the SiO 2 film 9 is removed by etching, and then the a-Si: H layer 4 is formed to form a source / drain contact having good contact characteristics.
n+a−Si層３上に形成したSiO2膜９が、レジスト膜とn
+a−Si層３表面が直接接触することによるるn+a−Si層
３の表面状態の劣化を防止するバッファ層として働き、
弗酸系のエッチャントによるエッチングを行うことによ
り、n+a−Si層３の表面の自然酸化膜を容易に除去する
ことができ、従って、n+a−Si層３の表面を完全露出さ
せることが可能となり、この上に形成したａ−Si:H層４
との間のコンタクトは良好なものとなる。The SiO 2 film 9 formed on the n + a-Si layer 3 forms a resist film and n
+ acts as a buffer layer for preventing the deterioration of the surface state of the n + a-Si layer 3 due to the direct contact of the surface of the a-Si layer 3,
By performing etching with a hydrofluoric acid-based etchant, the natural oxide film on the surface of the n + a-Si layer 3 can be easily removed, so that the surface of the n + a-Si layer 3 can be completely exposed. And the a-Si: H layer 4 formed on this
The contact between and will be good.
以下第１図（ａ）〜（ｆ）により、本発明の一実施例
をその製造工程の順に説明する。One embodiment of the present invention will be described below in the order of its manufacturing steps with reference to FIGS.
絶縁基板，例えばガラス基板１上に、金属膜２コンタ
クト層としてn+a−Si層３、SiO2膜９を順次積層し、更
にその上に、これら積層された膜をパターニングするた
めのレジスト膜７を形成する〔第１図（ａ）参照〕。On the insulating substrate, for example, the glass substrate 1, the n + a-Si layer 3 as the contact layer of the metal film 2 and the SiO 2 film 9 are sequentially laminated, and further thereon, a resist film for patterning these laminated films. 7 is formed [see FIG. 1 (a)].
次いでこのレジスト膜７をマスクとして、上記SiO2膜
9,n+a−Si層3,金属膜２を順次エッチングし、その後レ
ジスト膜７を除去する〔同図（ｂ）参照〕。Then, using the resist film 7 as a mask, the SiO 2 film is formed.
The 9, n + a-Si layer 3 and the metal film 2 are sequentially etched, and then the resist film 7 is removed [see FIG.
次いで上記SiO2膜９を弗酸系のエッチャントによりエ
ッチング除去して、n+a−Si層３表面を露出させる〔同
図（ｃ）参照〕。Then, the SiO 2 film 9 is removed by etching with a hydrofluoric acid-based etchant to expose the surface of the n + a-Si layer 3 [see FIG.
このように本実施例ではn+a−Si層３表面にレジスト
膜７が直接接触することがないので、SiO2膜９を除去す
る際に、n+a−Si層３表面の自然酸化膜も同時に弗酸系
エッチャントによって容易に除去され、清浄なn+a−Si
層３表面が露呈される。Since the resist film 7 n + a-Si layer 3 surface in this embodiment there is no direct contact, when removing the SiO 2 film 9, the natural oxide film of the n + a-Si layer 3 surface At the same time, it is easily removed by a hydrofluoric acid-based etchant, and clean n + a-Si
The surface of layer 3 is exposed.
この後の工程は従来と全く同様に、プラズマ化学気相
成長（Ｐ−CVD）法により、ａ−Si:H層４、次いでその
上の窒化シリコン（SiN）層５を成長させる〔同図
（ｄ）参照〕ことにより、n+a−Si層３とａ−Si:H層４
との良好なコンタクトが得られる。In the subsequent steps, the a-Si: H layer 4 and then the silicon nitride (SiN) layer 5 thereon are grown by the plasma chemical vapor deposition (P-CVD) method in exactly the same manner as in the conventional method. d)], the n + a-Si layer 3 and the a-Si: H layer 4 are
Good contact with.
次いでゲート電極となる導電層６を成膜し、更にその
上にレジスト膜８を形成する〔同図（ｅ）参照〕。Then, a conductive layer 6 to be a gate electrode is formed, and a resist film 8 is further formed thereon (see FIG. 6 (e)).
次いで上記レジスト膜８をマスクとして、導電層6,Si
N層5,a−Si:H層4,n+a−Si層３を順次エッチングし、し
かる後レジスト膜８を除去して、同図（ｆ）に見られる
ようなTFTが完成する。Then, using the resist film 8 as a mask, the conductive layer 6, Si
The N layer 5, a-Si: H layer 4, and the n + a-Si layer 3 are sequentially etched, and then the resist film 8 is removed to complete a TFT as shown in FIG.
以上のようにして本実施例で得られたTFTは、n+a−Si
層３表面の自然酸化膜が完全に除去されるので、n+a−S
i層３からなるコンタクト層と、ａ−Si:H層４からなる
活性層とのコンタクトは良好で且つ十分な再現性が得ら
れ、安定して高いオン電流が得られる。この結果スタガ
ード型TFTマトリクスの製造工程が容易且つ安定する。As described above, the TFT obtained in this example has n + a−Si
Since the native oxide film on the surface of layer 3 is completely removed, n + a-S
The contact between the contact layer made of the i layer 3 and the active layer made of the a-Si: H layer 4 is good, sufficient reproducibility is obtained, and a high on-current is stably obtained. As a result, the manufacturing process of the staggered TFT matrix is easy and stable.
以上説明した如く本発明によれば、ソース・ドレイン
電極のコンタクト特性が安定し、TFT特性，特にオン電
流の値が安定化される。As described above, according to the present invention, the contact characteristics of the source / drain electrodes are stabilized, and the TFT characteristics, especially the on-current value, are stabilized.
このためアクティブマトリクス製造工程が簡単化でき
るスタガード型ａ−Si TFTを液晶パネルに使用すること
が容易となる。Therefore, it becomes easy to use the staggered a-Si TFT in the liquid crystal panel, which can simplify the active matrix manufacturing process.
第１図は本発明一実施例説明図、 第２図は従来のTFTの説明図である。 図において、１は絶縁性基板（ガラス基板）、２は金属
膜、３はコンタクト層（n+a−Si層）、４は活性層（ａ
−Si:H層）、５はゲート絶縁膜（SiN層）、６は導電
層、９はSiO2膜を示す。FIG. 1 is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a conventional TFT. In the figure, 1 is an insulating substrate (glass substrate), 2 is a metal film, 3 is a contact layer (n + a-Si layer), and 4 is an active layer (a).
-Si: H layer), 5 denotes a gate insulating film (SiN layer), 6 conductive layer, 9 denotes a SiO 2 film.
Claims (1)
上に積層されたn+a−Si層（３）からなるコンタクト層
を有するソース電極及びドレイン電極、ａ−Si:H層から
なる活性層、ゲート絶縁膜、ゲート電極を順次積層され
てなるスタガード型アモルファスシリコン薄膜トランジ
スタを製造する方法であって、前記絶縁性基板（１）上
に金属膜（２），コンタクト層（３），二酸化シリコン
層（９）を積層した後、レジスト膜（７）をマスクとし
て、上記二酸化シリコン層，コンタクト層，金属膜のパ
ターニングを行い、上記コンタクト層上に活性層（４）
を成膜する前に弗酸系エッチャントにより上記二酸化シ
リコン膜（９）を除去し、しかる後表面を露呈せるコン
タクト層上に活性層の成膜を行う工程を含むことを特徴
とする薄膜トランジスタの製造方法。1. A source electrode and a drain electrode having a contact layer composed of a metal film (2) and an n + a-Si layer (3) laminated thereon on an insulating substrate (1), a-Si: A method for manufacturing a staggered type amorphous silicon thin film transistor, which comprises an active layer composed of an H layer, a gate insulating film, and a gate electrode, which are sequentially stacked, comprising a metal film (2), a contact layer ( 3), after the silicon dioxide layer (9) is laminated, the silicon dioxide layer, the contact layer, and the metal film are patterned using the resist film (7) as a mask, and the active layer (4) is formed on the contact layer.
A method of manufacturing a thin film transistor, comprising the steps of removing the silicon dioxide film (9) with a hydrofluoric acid-based etchant before forming a film, and then forming an active layer on the contact layer exposing the surface. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62036987A JP2503001B2 (en) | 1987-02-19 | 1987-02-19 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62036987A JP2503001B2 (en) | 1987-02-19 | 1987-02-19 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63204656A JPS63204656A (en) | 1988-08-24 |
| JP2503001B2 true JP2503001B2 (en) | 1996-06-05 |
Family
ID=12485099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62036987A Expired - Lifetime JP2503001B2 (en) | 1987-02-19 | 1987-02-19 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2503001B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5372958A (en) * | 1990-11-16 | 1994-12-13 | Seiko Epson Corporation | Process for fabricating a thin film semiconductor device |
-
1987
- 1987-02-19 JP JP62036987A patent/JP2503001B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63204656A (en) | 1988-08-24 |
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