KR940005735B1 - Manufacturing method of tft - Google Patents
Manufacturing method of tft Download PDFInfo
- Publication number
- KR940005735B1 KR940005735B1 KR1019910014773A KR910014773A KR940005735B1 KR 940005735 B1 KR940005735 B1 KR 940005735B1 KR 1019910014773 A KR1019910014773 A KR 1019910014773A KR 910014773 A KR910014773 A KR 910014773A KR 940005735 B1 KR940005735 B1 KR 940005735B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- photoresist
- layer
- tft
- etching
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000011521 glass Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 29
- 230000008021 deposition Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
제 1 도는 종래 TFT의 공정단면도.1 is a process cross-sectional view of a conventional TFT.
제 2 도는 본 발명의 TFT의 공정단면도.2 is a process cross-sectional view of the TFT of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 글래스기판 2 : 게이트전극1 Glass substrate 2 Gate electrode
3 : 절연막 4 : a-Si : H막3: insulating film 4: a-Si: H film
5 : n+－aSi : H막 6 : 소오스/드레인 전극5: n + -aSi: H film 6: source / drain electrode
9, 10 : 포토레지스트9, 10: photoresist
본 발명은 TFT(박막 트랜지스터)의 제조방법에 관한 것으로 특히 n+a-Si : H건식 에칭시 오버 에칭에 의해 하부 활성층막인 비정질실리콘막까지 에칭되는 것을 방지하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a TFT (thin film transistor), and particularly, to prevent etching of an amorphous silicon film, which is a lower active layer film, by over etching during n + a-Si: H dry etching.
종래 TFT의 제조 공정은 제 1(a)도에 도시된 바와같이 글래스 기판(1)위에 게이트메틸(Cr, Al2O3등)을 증착한후 패터닝(patterning)하여 게이트 전극(2)을 형성하고 그위에 절연막(3), a－Si : H막(4), n+a－Si : H막(5), 소오스/드레인 전극(6)을 차례로 형성한다. 그리고 제1(b)도와 같이 마스크를 사용하여 소오스/드레인 전극(6)을 패터닝후 n+a－Si : H막(5)을 건식 에칭한다.In the conventional TFT manufacturing process, as shown in FIG. 1 (a), gate methyl (Cr, Al 2 O 3, etc.) is deposited on the glass substrate 1 and then patterned to form the gate electrode 2. Then, an insulating film 3, an a-Si: H film 4, an n + a-Si: H film 5, and a source / drain electrode 6 are sequentially formed thereon. And using the mask, such as the help 1 (b) source / drain electrodes (6), n + a-Si is patterned after a: to dry etch the H film 5.
다음에 제1(c)도와 같이 채널부위의 n+a－Si : H막(5)을 포토레지스트(7)로 덮은후 나머지 부분의 a－Si : H막(4)을 건식 에칭한다.Next, as shown in Fig. 1 (c), the n + a-Si: H film 5 at the channel portion is covered with the photoresist 7, and the remaining a-Si: H film 4 is dry etched.
이후 제1(d)도와 같이 a－Si : H막(4)가지 연속 중착하고 에치 스토퍼(8)를 증착한후 패터닝하며 n+a－Si : H막(5)과 소오스/드레인 전극(6)을 증착하므로 TFT를 형성한다. 그러나, 상기와 같은 종래 TFT 제조방법에 있어서는 n+a－Si : H막(5) 에칭시 하부막인 a-Si : H막(4)도 에칭되기 때문에 a－Si : H막(4)을 두껍게 증착하므로 소자의 특성이 저하될 뿐만아니라 원가가 상승된다.After claim 1 (d) a-Si As shown in Fig: H film 4 of was good and of the successive deposition of an etch stopper (8) is patterned and the n + a-Si: H film 5 and the source / drain electrodes (6 E) to form a TFT. However, in the conventional TFT manufacturing method as described above, the a-Si: H film 4 is also etched because the a-Si: H film 4, which is a lower film, is also etched during the n + a-Si: H film 5 etching. Thick deposition not only degrades device characteristics but also increases costs.
본 발명은 이와같은 종래의 결점을 해결하기 위한 것으로 n+a－Si : H막을 오버 에칭없이 정확하게 에칭할 수 있는 TFT 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional drawback, and an object thereof is to provide a TFT manufacturing method capable of accurately etching an n + a-Si: H film without over etching.
이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제 2 도에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.
먼저 제2(a)도와 같이 글래스 기판(1)위에 게이트 전극(2)을 형성하고 그위에 절연막(3)과 a－Si : H막(4)을 연속 증착한후 네가티브 포토레지스트(9)을 사용하여 채널 부분을 포함하는 에칭하고자 하는 부분의 포토레지스트만 남긴다.First, as shown in FIG. 2 (a), the gate electrode 2 is formed on the glass substrate 1, and the insulating film 3 and the a-Si: H film 4 are continuously deposited thereon, and then the negative photoresist 9 is deposited. To leave only the photoresist of the portion to be etched including the channel portion.
그리고 제2(b)도와 같이 n+a－Si : H막(5)과 소오스/드레인 전극(6)을 증착한후 상기 포토레지스트(9)를 모두 제거하면 포토레지스트(9)위에 증착된 n+a－Si : H막(5)과 소오스/드레인 전극(6)이 같이 제거된다.As shown in FIG. 2 (b), when the n + a-Si: H film 5 and the source / drain electrode 6 are deposited, all of the photoresist 9 is removed, and then n is deposited on the photoresist 9. + a-Si: The H film 5 and the source / drain electrode 6 are removed together.
여기서, 포토레지스트(9) 패터닝후 상부에 증착되는 n+a－Si : H막(5)의 증착 온도가 200℃ 정도인데 케미컬 앰프리튜드(chemical amplitude)방식의 네거티브 포토레지스트를 사용하면 200℃~250℃의 하드 베이킹(hard baking)온도를 가지므로 포토레지스트의 형태를 양호하게 할 수 있다.Here, the deposition temperature of the n + a-Si: H film 5 deposited on the upper surface after patterning the photoresist 9 is about 200 ° C., but when the negative photoresist of chemical amplitude is used, the temperature is 200 ° C. Since it has a hard baking temperature of ˜250 ° C., the shape of the photoresist may be improved.
또한, 포토레지스트(9)을 제거하면 상부에 있는 n+a－Si : H막(5)과 소오스/드레인 전극(6)이 에칭되며 이때 조금의 오버 에칭도 없이 완벽하게 n+a－Si : H막(5)을 에칭할 수 있다.In addition, when the photoresist 9 is removed, the n + a-Si: H film 5 and the source / drain electrode 6 on the upper portion are etched. At this time, the n + a-Si: The H film 5 can be etched.
다음에 제2(C)도와 같이 채널부분의 a-Si : H막(4)을 포토레지스트(10)로 가린후 a-Si : H막(4)을 RIE공정으로 식각하고 제2(D)도와 같이 포토레지스트(10)을 제거한다.Next, as shown in FIG. 2C, the a-Si: H film 4 of the channel portion is covered with the photoresist 10, and then the a-Si: H film 4 is etched by the RIE process and the second (D) is etched. As shown, the photoresist 10 is removed.
이상에서 설명한 바와같은 본 발명은 n+a－Si : H막(5)을 정확하게 에칭할 수 있어 a-Si : H막(4)의 오버 에칭을 방지할 수 있고, 이에 따라 종래와 같이 에치 스토퍼를 사용할 필요가 없어져 소자의 특성을 향상시킬수 있음과 아울러 원가를 절감할 수 있는 효과가 있다.As described above, the present invention can accurately etch the n + a-Si: H film 5, thereby preventing over-etching of the a-Si: H film 4, and thus, the etch stopper as in the prior art. Since there is no need to use, the characteristics of the device can be improved and the cost can be reduced.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910014773A KR940005735B1 (en) | 1991-08-26 | 1991-08-26 | Manufacturing method of tft |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910014773A KR940005735B1 (en) | 1991-08-26 | 1991-08-26 | Manufacturing method of tft |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930005239A KR930005239A (en) | 1993-03-23 |
| KR940005735B1 true KR940005735B1 (en) | 1994-06-23 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910014773A KR940005735B1 (en) | 1991-08-26 | 1991-08-26 | Manufacturing method of tft |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940005735B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002091454A1 (en) * | 2001-05-10 | 2002-11-14 | Koninklijke Philips Electronics N.V. | Method of manufacturing a thin film transistor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980054456A (en) * | 1996-12-27 | 1998-09-25 | 김영환 | Device Separator Formation Method of Semiconductor Device |
-
1991
- 1991-08-26 KR KR1019910014773A patent/KR940005735B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002091454A1 (en) * | 2001-05-10 | 2002-11-14 | Koninklijke Philips Electronics N.V. | Method of manufacturing a thin film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930005239A (en) | 1993-03-23 |
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