KR100272255B1 - Manufacturing mathod for thin film transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a TFT is provided to be capable of simplifying fabricating process and saving fabricating costs by forming an etch stopper pattern with an organic insulating layer. CONSTITUTION: First, a gate insulating layer(104) and a semiconductor layer(106) are formed on a glass substrate(100) having a gate electrode(102). Then, an etch stopper pattern(108a) of organic insulator material is formed on the semiconductor layer on the gate electrode. Next, an n+ semiconductor layer(110) and a metal wire layer are formed on the semiconductor layer including the etch stopper pattern. Then, a source/drain electrode(112a) is formed by partially etching the metal wire layer with a photolithography process. Finally, the n+ semiconductor layer and the semiconductor layer are etched by using the source/drain electrode as a mask.

Description

Manufacturing method of thin film transistor {Manufacturing mathod for thin film transistor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (hereinafter referred to as TFT) used as an active element such as a liquid crystal display device (hereinafter referred to as an LCD device). The present invention relates to a TFT manufacturing method in which a stopper pattern is formed of an organic insulating layer to realize a process simplification due to a reduction in the number of masks during a process.

Recently, with the development of new advanced video devices such as high definition TVs (hereinafter referred to as HDTVs), there is a demand for flat panel displays. LCD is a representative technology of flat panel display and does not have problems such as low power and high speed which ELD (electro luminescence display), VFD (vacuum fluorescence display), PDP (plasma display panel) cannot solve. The LCD is divided into two types, passive and active. The active LCD is controlled by an active element such as a thin film transistor to control each pixel one by one, which is far superior to the passive LCD in speed, field of view, and contrast. It is used as the best indicator for HDTV that requires a resolution of 1 million pixels or more. Accordingly, as the importance of TFTs is highlighted, R & D on them is intensifying.

Currently, research and development on TFTs, which are used as electrical switching elements for selective driving of pixel electrodes in LCDs, focus on reducing manufacturing costs by improving yield and improving productivity. The focus is on improvement, ohmic contact resistance of electrodes, and prevention of disconnection and short circuit. Of these, more research is being conducted on the technology of amorphous silicon TFT because of its large area, low cost, and mass productivity.

Amorphous TFTs currently used in manufacturing lines are largely divided into two types depending on the structure of the gate. One is a bottom gate type, also called an inverse stagger type, and the other is a top gate type, also called a forward stagger type.

Forming a gate electrode first on a substrate is called a bottom gate type and forms a main species. On the other hand, the top gate type first forms the source / drain electrodes of the thin film transistor, and in reality, it is not used much because of the large leakage current and lack of mass productivity.

The bottom gate type is divided into two types. 1 and 2 are cross-sectional views showing the structure of these two types of bottom gate amorphous silicon TFTs. 1 shows an etch back type TFT structure, and FIG. 2 shows an etch stopper type TFT structure.

The etch back type TFT of FIG. 1 includes a gate insulating layer (eg, SiN _X layer) 14 and a semiconductor layer (eg, amorphous silicon layer: a-Si) on the gate electrode 12 formed on the glass substrate 10. Layer) 16, n ⁺ semiconductor layer (e.g., n ⁺ amorphous silicon layer: n + a-Si layer) 18, and source / drain electrodes 20 in a stacked structure, the etch stopper of FIG. TFTs of the type include a gate insulating layer 14, a semiconductor layer (e.g., an a-Si layer) 16, an etch stopper pattern 17 of SiNx material, an n ⁺ semiconductor layer 18, and a source on the gate electrode 12. The drain electrode 20 has a structure in which it is continuously stacked.

The etch stopper type TFT is able to protect the semiconductor layer 16 from the etching process due to the etch stopper pattern 17 formed to prevent damage to the semiconductor layer, thereby minimizing the thickness of the semiconductor layer. Not only can the on / off current value of the TFT be improved, but also the parasitic capacitance of the portion where the gate electrode 12 and the source / drain electrode 20 cross. It is possible to reduce the value of, and to minimize the influence of the semiconductor layer by light, and to reduce the photocurrent, and to improve the operation characteristics of the transistor compared to the etchback type TFT of FIG. Although it has an advantage, it is more limited than the etchback type TFT due to the increase in the number of manufacturing processes and various problems in the manufacturing process. There is a situation.

This will be described in detail with reference to the process block diagram shown in FIG. 3. 3 is a process block diagram schematically showing a method of manufacturing an etch stopper type TFT shown in FIG.

In the first step 30, a gate metal (for example, Al metal or Mo metal) is deposited on the glass substrate 10, and then the gate metal is exposed so that the substrate surface is partially exposed by a photolithography process using a mask. The etching process is performed to form the gate electrode 12. In this case, the gate electrode 12 may be formed to have a two-layer stacked structure such as "Al-Nd / Mo" according to the purpose of use.

As a second step 32, a gate insulating layer (eg, SiNx layer) 14, a semiconductor layer (a-Si layer) 16 as an active layer on the entire surface of the substrate 10 including the gate electrode 12. , The etch stopper layer (SiNx layer) 17 is continuously deposited, and then a curing process is performed. In this case, the etch stopper layer 17 is deposited by chemical vapor deposition (hereinafter referred to as PECVD) using plasma, and serves to prevent damage to the semiconductor layer 16 from overetching in a subsequent process. do.

In a third step 34, a photoresist film (not shown) is deposited on the etch stopper layer, and the photoresist film is etched by a front surface exposure method using a mask to have a line width slightly larger than that of the gate electrode 12. Next, the photoresist pattern is patterned to have the same line width as the gate electrode 12 by a backside exposure method using the gate electrode 12 as a mask. Subsequently, the photoresist pattern is cured at a high temperature of about 200 ° C. to enhance adhesion to the underlying layer, and then the lower portion of the semiconductor layer 16 is exposed by using the cured photoresist pattern as a mask. The etch stopper layer is etched to form an etch stopper pattern 17 on the channel portion of the TFT, and the surface of the photoresist pattern hardened by the curing process is first etched to a predetermined thickness using an etching process, and then the photoresist film is etched. Remove the remainder of the pattern. In this case, the etch stopper layer is etched by a wet etching process or a dry etching process using an HF solution, and the photoresist pattern may be immediately etched without an ashing process. However, when the etching process is not performed, the photoresist residue is completely removed after the etching process. It requires a great deal of attention to the process because it causes the residue to be removed and remains as a residue.

As a fourth step 36, the entire surface of the substrate 10 is cleaned with an HF solution, and an n + semiconductor layer (eg, n + a-Si) is used for ohmic contact on the semiconductor layer 16 including the etch stopper pattern 17. Layer 18).

In a fifth step 38, a metal wiring layer (eg, an AL layer) 20 is deposited on the n + semiconductor layer 18, and a photoresist pattern is formed on the metal wiring layer by a photolithography process using a mask. By using the photoresist pattern as a mask, the metal wiring layer is etched to form a source / drain electrode 20, and the photoresist pattern is removed.

In a sixth step 40, the n + semiconductor layer 18 and the semiconductor layer 16 under the semiconductor layer 16 are disposed so that the gate insulating layer 14 is partially exposed using the source / drain electrode 20 as a mask. Etching is performed by reactive ion etching (RIE) to expose a portion of the surface of the etch stopper pattern 17 of the TFT channel portion, thereby completing the manufacture of one TFT.

However, when manufacturing the thin film transistor using the above process, the following four disadvantages occur.

First, since an etching process using a mask is required three times (for example, when forming a gate electrode, when forming an etch stopper pattern, and when forming a source / drain electrode) during the process, not only three masks are required but also an etch stopper pattern is formed. In the process of forming the photoresist pattern in order to prevent mis alignment, two exposure processes (front exposure and back exposure) and curing processes are required, thereby increasing manufacturing costs.

Second, since the etching time required to form the etch stopper pattern is long, when the etching process is performed by the wet etching process using HF as an etching solution, the photoresist pattern is changed by the HF solution during the process and the photoresist residue is removed even after the photoresist pattern removal process. Residual organic components remain, which causes particles to be opened during the subsequent process, which leads to line open, whereas when the etching process is performed using a dry etching process, the semiconductor layer is a lower layer. It is difficult to selectively etch the structure, and thus it is necessary to consider the structure in consideration of the loss of the semiconductor layer, and to perform the ashing process using a plasma to remove the photoresist pattern after the dry etching, and in this process, the semiconductor layer is exposed to the plasma. The characteristics of the amorphous silicon constituting the semiconductor layer Poor phenomena such as change are caused.

Third, in the cleaning process using HF solution, SiN _X constituting the etch stopper layer is partially dissolved in the HF solution, and thus, residues of SiN _X dissolved in the pattern valleys of the semiconductor layer formed underneath flow into the silica. It is formed, which causes the process failure during the subsequent process.

Fourth, since the etching time required to form the etch stopper pattern is long, the time required for the amorphous silicon layer, which is a semiconductor layer, to be exposed in the air during the etching process is long, so that a thin natural oxide film (eg, a silicon oxide film) is formed on a portion of the surface thereof. When the n ⁺ semiconductor layer is deposited thereon, the surface of the n ⁺ semiconductor layer is impaired due to a poor adhesion to the natural oxide layer, so that water droplet defects appear as if water droplets are formed. The inconvenience of having to perform a separate cleaning process, such as HF cleaning or H ₂ O ₂ cleaning to remove the.

Accordingly, the present invention was devised to improve the above-mentioned disadvantages, and by forming the etch stopper pattern as an organic insulating film (photosensitive organic insulating film, non-photosensitive organic insulating film), TFT manufacturing can be realized to simplify the process and reduce manufacturing cost. The purpose is to provide a method.

1 is a cross-sectional view showing a structure of a conventional etchback type thin film transistor;

2 is a cross-sectional view showing a conventional etch stopper type thin film transistor structure;

3 is a process block diagram schematically showing a method of manufacturing an etch stopper type thin film transistor shown in FIG.

4A to 4E are process flowcharts showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention;

5A to 5F are process flowcharts showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention.

In order to achieve the above object, the present invention provides a process of forming a gate insulating layer and a semiconductor layer on a substrate having a gate electrode, and forming an etch stopper pattern of an organic insulating material on the semiconductor layer above the gate electrode. And forming an n + semiconductor layer and a metal wiring layer on the semiconductor layer including the etch stopper pattern, forming a source / drain electrode by etching a predetermined portion of the metal wiring layer by a photolithography process, and the source / Provided is a TFT manufacturing method comprising etching the n + semiconductor layer and a semiconductor layer below the drain electrode as a mask. In this case, when the etch stopper pattern is manufactured by using the photosensitive organic insulating layer, the pattern is formed by etching the etch stopper layer directly by using a backside exposure process, whereas when the etch stopper pattern is manufactured by using the non-photosensitive organic insulating layer. After forming a photoresist pattern on the etch stopper layer by a back exposure process, a pattern is formed by patterning the etch stopper layer using the mask as a mask. Examples of the photosensitive organic insulating film to be applied in the present invention include photosensitive polyimide, photosensitive acrylic, photosensitive BCB (benzocyclobutine), and the like. .

When the process proceeds as described above, the two exposure processes (front exposure and back exposure processes) required for forming the etch stopper pattern can be reduced to one exposure process (back exposure process), thereby reducing the number of process steps. do. In addition, this can reduce the number of masks required in the process of forming the etch stopper pattern in the TFT manufacturing process by one, thereby realizing the process simplification and cost reduction.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The present invention focuses on forming an etch stopper pattern with an organic insulating film (photosensitive organic insulating film or non-photosensitive organic insulating film) material, thereby eliminating the complexity of the process proceeding caused by manufacturing the etch stopper type TFT and realizing cost reduction. As a technique, this will be described in detail with reference to the process steps shown in FIGS. 4A to 4E and 5A to 5F.

4A to 4E show a TFT manufacturing method in the case of forming an etch stopper pattern with a photosensitive organic insulating film as a first embodiment of the present invention, and FIGS. 5A to 5F show a second embodiment of the present invention. The TFT manufacturing method at the time of forming an etch stopper pattern with a non-photosensitive organic insulating film is shown.

First, the TFT manufacturing method according to the first embodiment will be described. The TFT manufacturing method is largely divided into five process steps, which will be described by dividing step by step. Each process corresponds to FIGS. 4A-4E.

As a first step, as shown in Figure 4a, by depositing a gate metal layer of 2000 ~ 2500Å thickness on the substrate (for example, glass substrate) 100 by the sputtering method, and then by a photolithography process using a mask The metal layer is etched to form the gate electrode 102. At this time, the metal constituting the gate electrode 102 may be Al, Ta, W, Cr, etc., depending on the purpose of use, the gate electrode 102 has a stack structure of "Al-Nd / Mo". It may be formed so that.

Subsequently, a gate insulating layer (eg, SiN _X ) 104 having a thickness of 3000 ± 100 μs and a semiconductor layer having a thickness of 10˜5000 μm are formed on the entire surface of the substrate S on which the gate electrode 102 is formed by PECVD. (Amorphous Silicon Layer) 106 is sequentially deposited, and the entire substrate is cleaned using HF solution. Then, the etch stopper layer 108 made of the photosensitive organic insulating material is formed to a thickness of 1 to 20,000 [mu] s using a spin coating method. Coating. In this case, as the photosensitive organic insulating layer, a material such as photosensitive polyimide, photosensitive acrylic, photosensitive BCB (Benzocyclobutine) is used, and the thickness of the etch stopper layer 108 may be 500 kPa.

As a second step, as shown in FIG. 4B, a backside exposure using the gate electrode 102 as a mask is performed to leave a photosensitive organic insulating layer forming an etch stopper layer only on the gate electrode 102. As a result, an etch stopper pattern 108a of the illustrated form is formed. Subsequently, a hardening process is performed to harden the etch stopper pattern 108a at a temperature of about 200 ° C. (eg, 180 to 350 ° C.) to enhance adhesion between the etch stopper pattern 108a and the semiconductor layer 106.

As a third step, as shown in FIG. 4C, the substrate 100 using H ₂ plasma which does not damage the etch stopper pattern 108a made of the photosensitive organic insulating material to remove contaminants of the semiconductor layer 106. ) Over the semiconductor layer 106 on the semiconductor layer 106 including the etch stopper pattern 108a using PECVD for ohmic contact with the source / drain electrodes to be subsequently formed. 110). Subsequently, a metal wiring layer 112 made of Cr is deposited on the n + semiconductor layer 110 to a thickness of 10 to 5000 Å. In this case, the n + semiconductor layer 110 is formed of n + amorphous silicon or fine crystalline silicon (n + μC-Si) doped with PH ₃ , the metal wiring layer 112, in addition to Cr, Mo alloy (eg, Mo-W ), Al, Mo, Al alloy (eg Al-NCl) and the like may be used.

As a fourth step, a photoresist film is deposited on the metallization layer 112 as shown in FIG. 4D, and the photoresist layer is partially etched by a photolithography process using a mask to form a photoresist pattern 114.

As a fifth step, as shown in FIG. 4E, the metal wiring layer 112 is wet-etched using the photoresist pattern 114 as a mask to form a source / drain electrode 112a, and the photoresist pattern 114 is removed. Next, by simultaneously etching the n + semiconductor layer 110 and the semiconductor layer 106 below using the source / drain electrode 112a as a mask, one TFT manufacturing is completed. At this time, since only the n + semiconductor layer 110 is selectively etched by the etch stopper pattern 108a of the TFT, the surface of the etch stopper pattern 108a of this portion is exposed to a predetermined portion.

In this case, since the mask is used only when the gate electrode 102 is formed on the substrate 100 and when the source / drain electrodes 112a are formed, the number of masks is 1 compared with the conventional case. This can reduce costs and increase productivity.

In addition, the entire surface exposure process, photoresist pattern curing process, etch stopper layer etching process using the photoresist pattern as a mask, an ashing process for removing the photoresist pattern, which are required when forming the etch stopper pattern 108a by a photolithography process using a mask, are performed. And since the etching process can be skipped, it is possible to solve the difficulty of TFT manufacturing due to the complexity of the process proceeding procedure, which is a problem in the conventional etch stopper type TFT manufacturing process.

Next, a TFT manufacturing method according to the second embodiment will be described. The TFT manufacturing method is largely divided into six process steps, and each process step corresponds to FIGS. 5A to 4F. In the case of the above embodiment, since the etch stopper pattern is formed of the non-photosensitive organic insulating film, and is basically the same as the first embodiment except for a small difference in the process proceeding procedure, the other parts except for forming the etch stopper pattern are used. Only briefly mentioned.

As a first step, as shown in FIG. 5A, the gate insulating layer 104 made of SiN _X material and the semiconductor layer made of amorphous silicon are formed on the entire surface of the substrate (eg, glass substrate) 100 having the gate electrode 102. (106), the entire surface of the substrate 100 is cleaned using an HF solution, and the etch stopper layer 108 of the non-photosensitive organic insulating material is formed on the semiconductor layer 106 to a thickness of 1 to 20000 kPa. After coating, a photosensitive film 109 is deposited thereon. In this case, a material such as polyimide, acrylic, benzocyclobutine (BCB), perflorecyclobutine (PFCB) is used as the non-photosensitive organic insulating layer, and the etch stopper layer 108 may have a thickness of 500 kPa.

As a second step, as shown in FIG. 5B, a backside exposure using the gate electrode 102 as a mask is performed so that the photoresist film remains only on the gate electrode 102. As a result, the photosensitive film pattern 109a of the illustrated form is formed. Subsequently, a curing process of hardening the photoresist pattern is performed at a high temperature of about 120 ° C. in order to enhance adhesion with the lower layer.

As a third step, the etch stopper layer 108 is etched by dry etching using the photoresist pattern 109a cured as shown in FIG. 5C as a mask to form an etch stopper pattern 108a. After removing the photoresist pattern 109a, the etch stopper pattern 108a is formed at a temperature of about 200 ° C. (eg, 180 to 350 ° C.) to enhance adhesion between the etch stopper pattern 108a and the semiconductor layer 106. Hardening process to harden) is performed. In this case, the photoresist pattern 109a may be removed by first etching the surface of the photoresist pattern hardened by the curing process using an ashing process, and then removing the remaining photoresist pattern 109a.

As a fourth step, as shown in FIG. 5D, the substrate (using H ₂ plasma that does not damage the etch stopper pattern 108a made of a non-photosensitive organic insulating material for removing contaminants of the semiconductor layer 106). 100, the n + semiconductor layer 110 and the metal wiring layer 112 made of Cr are deposited on the semiconductor layer 106 including the etch stopper pattern 108a. In this case, the n + semiconductor layer 110 is formed of n + amorphous silicon or fine crystalline silicon (n + μC-Si) doped with PH ₃ , the metal wiring layer 112, in addition to Cr, Mo alloy (eg, Mo-W ), Al, Mo, Al alloy (eg Al-NCl) and the like may be used.

As a fifth step, as illustrated in FIG. 5E, the photoresist pattern 114 is formed on the metal wiring layer 112 by a photolithography process using a mask.

As a sixth step, as shown in FIG. 5F, the metal wiring layer 112 is partially wet-etched using the photoresist pattern 114 as a mask to form a source / drain electrode 112a, and the photoresist pattern ( Remove 114). Subsequently, the n + semiconductor layer 110 and the semiconductor layer 106 below are etched using the source / drain electrode 112a as a mask so that the surface of the etch stopper pattern 108a of the TFT channel portion is partially exposed. One TFT manufacturing is completed.

In the case of the above embodiment, when forming the etch stopper pattern 108a of the TFT, a photoresist pattern forming process using backside exposure, a photoresist pattern curing process, an etch stopper layer 108 etching process using the photoresist pattern 109a as a mask, and a photoresist pattern Since the ashing process and the etching process for removing 109a are not skipped, the number of processes required for forming an etch stopper pattern is somewhat higher than that of the first embodiment, but the front exposure process using a mask is skipped. Compared with the conventional case, since the number of masks can be reduced by one, the process can be simplified, thereby reducing costs and improving productivity.

As described above, according to the present invention, first, since a photolithography process using a mask is required twice (at the time of forming a gate electrode and a source / drain electrode) when manufacturing a thin film transistor, the number of masks is reduced by one compared with the conventional case. It is possible to simplify the process, reduce the manufacturing cost, and improve productivity. Second, since the etch stopper pattern is formed by the backside exposure process, it prevents the line disconnection phenomenon caused when the etch stopper pattern is formed by the wet etching process. Third, when the etch stopper pattern is formed of the photosensitive organic insulating layer, a separate dry etching process for etching the etch stopper layer is not necessary during the process, thereby preventing the loss of the semiconductor layer when forming the etch stopper pattern. In addition to skipping the ashing and etching processes to remove the photoresist pattern Since the process can be simplified, and the characteristics of the semiconductor layer can be prevented, and the etch stopper pattern is formed by the backside exposure process, the pattern is formed by the photolithography process using a mask. Since the etching time required to form the etch stopper pattern can be reduced, the growth of the native oxide film on the semiconductor layer can be suppressed as much as possible, and a separate cleaning process is not required.

Claims (31)

Forming a gate insulating layer and a semiconductor layer on the substrate provided with the gate electrode; Forming an etch stopper pattern of a photosensitive organic insulating film on the semiconductor layer above the gate electrode; Forming an n + semiconductor layer and a metal wiring layer on the semiconductor layer including the etch stopper pattern; Forming a source / drain electrode by etching a predetermined portion of the metal wiring layer by a photolithography process; Etching the n + semiconductor layer and the semiconductor layer using the source and drain electrodes as masks; The forming of the etch stopper pattern of the photosensitive organic insulating material may include depositing an etch stopper layer of the photosensitive organic insulating material on the semiconductor layer; And etching the etch stopper layer by performing a series of backside exposure using the gate electrode as a mask. The method of claim 1, wherein the etch stopper pattern of the photosensitive organic insulating material is formed to a thickness of 1 ~ 20000Å. The method of claim 1, further comprising a hardening process after forming the etch stopper pattern of the photosensitive organic insulating material. The method of claim 3, further comprising a substrate cleaning process using H ₂ plasma after the curing process. The method of claim 3, wherein the curing process is performed in a temperature range of 180 to 350 ° C. 5. The method of claim 1, further comprising a cleaning process using an HF solution after the semiconductor layer is formed. The method of claim 1, wherein the etch stopper layer of the photosensitive organic insulating material is formed by spin coating. The method of claim 1, wherein the etch stopper pattern of the photosensitive organic insulating material is formed of any one selected from photosensitive polyimide, photosensitive acrylic, and photosensitive Benzocyclobutine (BCB). The method of claim 1, wherein the n + semiconductor layer is formed of n + amorphous silicon or fine crystalline silicon (n + μC—Si) doped with PH ₃ . The method of claim 1, wherein the metal wiring layer is formed of any one selected from Cr, Mo alloy, Al, Mo, Al alloy. The method of claim 1, wherein the metal wiring layer is formed to a thickness of 10 ~ 5000 ~. The method of claim 1, wherein the n + semiconductor layer is formed by PECVD. The method of claim 1, wherein the metal wiring layer is formed by a sputtering method. The method of claim 1, wherein the metallization layer is wet etched. The method of claim 1, wherein the semiconductor layer is formed to a thickness of 10 ~ 5000Å. Forming a gate insulating layer and a semiconductor layer on the substrate provided with the gate electrode; Forming an etch stopper pattern of a non-photosensitive organic insulating material on the semiconductor layer above the gate electrode; Forming an n + semiconductor layer and a metal wiring layer on the semiconductor layer including the etch stopper pattern; Forming a source / drain electrode by partially etching the metal wiring layer by a photolithography process; Etching the n + semiconductor layer and the semiconductor layer using the source and drain electrodes as masks; The step of forming an etch stopper pattern of the non-photosensitive organic insulating material includes depositing an etch stopper layer of the non-photosensitive organic insulating material on the semiconductor layer; Depositing a photoresist film on the etch stopper layer; Forming a photoresist pattern by etching a predetermined portion of the photoresist by a series of backside exposure processes using a gate electrode as a mask; Etching the etch stopper layer of the non-photosensitive organic insulating material using the photosensitive film pattern as a mask; The thin film transistor manufacturing method comprising the step of removing the photosensitive film pattern. 17. The method of claim 16, wherein the etch stopper layer of the non-photosensitive organic insulating material is dry etched. 17. The method of claim 16, further comprising a curing process after deposition of the etch stopper layer of the non-photosensitive organic insulating material. The method of claim 18, wherein the curing process is performed in a temperature range of 180 to 350 ° C. 19. The method of claim 16, further comprising: cleaning the substrate using H ₂ plasma after removing the photoresist pattern. The method of claim 16, wherein the etch stopper pattern of the non-photosensitive organic insulating material is formed to a thickness of 1 to 20000 Å. The method of claim 16, further comprising a cleaning process using an HF solution after forming the semiconductor layer. The method of claim 16, wherein the etch stopper layer of the non-photosensitive organic insulating material is formed by spin coating. The method of claim 16, wherein the etch stopper pattern of the non-photosensitive organic insulating material is formed of one selected from polyimide, acrylic, benzocyclobutine (BCB), and perflorecyclobutine (PFCB). The method of claim 16, wherein the n + semiconductor layer is formed of n + amorphous silicon or microcrystalline silicon (n + μC-Si) doped with PH ₃ . The method of claim 16, wherein the metal wiring layer is formed of any one selected from Cr, Mo alloy, Al, Mo, Al alloy. 17. The method of claim 16, wherein the metal wiring layer is formed to a thickness of 10 ~ 5000Å. 18. The method of claim 16, wherein the n + semiconductor layer is formed by PECVD. The method of claim 16, wherein the metal wiring layer is formed by a sputtering method. 17. The method of claim 16, wherein the metallization layer is wet etched. The method of claim 16, wherein the semiconductor layer is formed to a thickness of 10 ~ 5000Å.

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