JPH0832082A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To contrive reduction in leakage current in a thin film transistor as well as to suppress the generation of the film defects in a transistor in a process of manufacturing the transistor by a method wherein the bottom gate thin film transistor with an offset provided in a self alignment is manufactured. CONSTITUTION:A first process: a gate electrode 12 is formed on a transparent substrate 11 and a light-shielding insulating film 13 is formed on the surface of the electrode 12. A second process: a semiconductor layer pattern 17, which crosses the upper part of the electrode 12, is formed on the electrode 12 via a gate insulating film 16. A third process: after an upper insulating film 18 and an N-type resist film 19 are laminated on the whole surface of the pattern 17, the film 19 is exposed and developed from the side of the substrate 11 using the film 13 as a mask to form a resist pattern 20 which is used as an etching mask. A fourth process: an insulating film pattern 21, which is used as an ion doping mask, is formed of the film 18 by etching. A fifth process: source-drain regions 22 and 23 are formed in the pattern 17 by ion doping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor which is a bottom gate type and has source / drain regions formed in an offset structure.

[0002]

2. Description of the Related Art As a thin film transistor having a self-aligned offset structure, a top gate type thin film transistor has been proposed. A method of manufacturing the top gate type thin film transistor having the self-aligned offset structure will be described with reference to the schematic sectional view of FIG.

As shown in the figure, a silicon nitride layer 82 is formed on a quartz substrate 81. Further, a silicon layer pattern 83 and a gate insulating film 84 are formed. Then, the gate electrode 85 is formed, and a silicon oxide film (not shown) is formed on the entire surface. Then, the silicon oxide film is etched back to form sidewalls 86 on the sidewalls of the gate electrode 85. Then, by using the gate electrode 85 and the side wall 86 as a mask, conductive type impurities are introduced (for example, ion implantation) into the silicon layer pattern 83, so that the source / drain regions 89 having the offsets 87 and 88 formed in the silicon layer pattern 83, Form 90.

[0004]

However, no method for manufacturing a bottom gate type thin film transistor having an offset structure has been proposed. If a bottom gate type thin film transistor with an offset structure is to be manufactured, an ion implantation mask that secures an offset length with respect to a gate electrode must be formed during ion implantation for forming source / drain regions. . However, it is not possible to sufficiently form the above ion implantation mask due to the mask alignment accuracy. Therefore, it is difficult to form the offset length accurately. Therefore, it is necessary to form the offset by self-alignment. Also,
Annealing at a high temperature is required to remove defects generated by ions or plasma irradiated during ion implantation or etching. Therefore, when a substrate having low heat resistance such as a glass substrate is used, a process involving ion implantation or etching which requires annealing at a high temperature cannot be applied.

An object of the present invention is to provide a method of manufacturing a thin film transistor which is excellent in forming an offset structure in a self-aligned manner.

[0006]

The present invention is a method of manufacturing a thin film transistor, which has been made to achieve the above object. That is, in the first aspect of the present invention, in the first step, after the gate electrode is formed on the surface of the transparent substrate at least the surface side of which is insulative, the surface of the gate electrode is shielded from light of at least a predetermined wavelength Form a film. Next, in a second step, after forming a gate insulating film on the gate electrode, a semiconductor layer pattern that crosses the gate electrode is formed thereon. Then, in a third step, after forming an upper layer insulating film and a negative resist film on the entire surface of the transparent substrate in order, the negative resist is exposed from the transparent substrate side using the light shielding insulating film as a mask, and subsequently, Development is performed to form a resist pattern. Then, in a fourth step, an insulating film pattern is formed by the upper insulating film by etching using the resist pattern as a mask. Then, in a fifth step, the source / drain regions are formed by introducing impurity ions into the exposed semiconductor thin film layer by ion doping using the insulating film pattern as a mask.

In the second invention, after the steps similar to the first to fourth steps of the first invention are sequentially performed, the resist pattern is removed in the fifth step, and then the semiconductor layer is formed. A doped layer containing conductive impurities is formed on both sides of the insulating film pattern to be connected to the pattern, and the conductive impurities in the doped layer are diffused into the semiconductor layer pattern of the portion to be connected to it, and then the doped layer is patterned. Then, the source / drain regions are formed.

In the third invention, after performing the same steps as the first and second steps of the first invention, in the third step, a negative resist film is formed on the entire surface of the transparent substrate. After that, the negative resist is exposed from the transparent substrate side using the light-shielding insulating film as a mask, and then developed to form a resist pattern. Subsequently, in a fourth step, after forming a doped layer containing conductive impurities on the entire surface on the resist pattern side, the resist pattern and the doped layer on the upper surface thereof are removed by a lift-off method. Thereafter, in a fifth step, the conductive impurities in the doped layer left by the lift-off method are diffused into the semiconductor layer pattern of the portion connected to this doped layer to form source / drain regions.

[0009]

The first aspect of the method for manufacturing the above thin film transistor
In the invention, since the light shielding insulating film is formed on the surface of the gate electrode, the length of the light shielding insulating film is longer than the gate length. After that, the negative resist film is exposed from the transparent substrate side using the light-shielding insulating film as a mask and further developed, so that the length of the resist pattern formed is almost the same as the length of the light-shielding insulating film transferred. Be longer than long.
Further, since the insulating film pattern is formed by etching using the resist pattern as a mask, the length of the insulating film pattern becomes almost the length of the resist pattern transferred, which is also longer than the gate length. Then, by ion doping using an insulating film pattern longer than the gate length as a mask, impurity ions are introduced into the exposed semiconductor layer pattern to form a source / drain region, so that the source / drain region is more than the gate electrode. It will be formed at a position separated in the gate length direction. Therefore, an offset is formed between the source / drain region and the channel region formed in the semiconductor layer pattern on the gate electrode. Moreover, in this manufacturing method, since the source / drain regions are formed by diffusion, ion implantation is not required. Therefore, no defects are generated by the ion implantation.

In the second invention, the length of the insulating film pattern is formed longer than the gate length, as in the first invention. Then, a doped layer is formed in a state of covering the semiconductor layer pattern with an insulating film pattern, and then impurities are diffused from each doped layer into the semiconductor layer pattern, so that each doped layer and a semiconductor layer pattern of a portion connected to the doped layer are formed. Since the source / drain regions are formed,
The drain region is not formed in the semiconductor layer pattern covered with the insulating film pattern. Therefore, there is an offset between the source / drain region and the channel region formed in the semiconductor layer pattern above the gate electrode. Moreover, in this manufacturing method, since the source / drain regions are formed by diffusion, ion implantation is not required. Therefore, no defects are generated by the ion implantation. Furthermore, since the insulating film pattern serves as an etching stopper when the doped layer is etched, etching damage is not applied to the underlying semiconductor layer pattern.

In the third invention, as in the first invention, the resist pattern is formed by development after exposure using the light-shielding insulating film formed on the surface of the gate electrode as a mask. It is formed longer than the length. Then, a doped layer is formed on the entire surface on the resist pattern side, and subsequently, the resist pattern and the doped layer on the upper surface thereof are removed by a lift-off method.
The length of the doped layer removed by the lift-off method is longer than the gate length. Then, the impurities in the doped layer left by etching are diffused into the semiconductor layer pattern connected thereto to form the source / drain regions, so that the source / drain regions and the channel region formed in the semiconductor layer pattern above the gate electrode are formed. There is an offset between them.
Moreover, in this manufacturing method, since the source / drain regions are formed by diffusion, ion implantation is not required. Therefore, no defects are generated by the ion implantation. Furthermore, since the doped layer is patterned by the lift-off method, the semiconductor layer pattern is not damaged by etching.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to the manufacturing process diagram of FIG. In the figure, a bottom gate type thin film transistor is shown.

As shown in FIG. 1A, in the first step, a gate electrode forming layer (not shown) is formed on a transparent substrate 11 having an insulating property at least on the surface side. As the transparent substrate 11, for example, a glass substrate is used. Next, the gate electrode 12 is formed in the gate electrode forming layer by lithography and etching. This gate electrode 12
Is made of, for example, aluminum, aluminum alloy, tantalum, molybdenum, titanium, chromium or copper.

Thereafter, a light-shielding insulating film 13 that shields light of at least a predetermined wavelength (for example, in the range of 360 nm to 470 nm) is formed on the surface of the gate electrode 12 by an oxidation method such as an anodic oxidation method or a plasma oxidation method. For example, when the light-shielding insulating film 13 is formed by the anodic oxidation method, the thickness of the light-shielding insulating film 13 is controlled by selecting the formation current, voltage and oxidation time during the anodic oxidation. Desirably, the thickness of the light shielding insulating film 13 is 0.1 μm or more.
Set to a certain value within the range of 2 μm.

At the time of the anodic oxidation, light is shielded by an electrolytic color development method (a mixed solution of sulfosalicylic acid (10%) and sulfuric acid (1%) is used as an electrolytic solution and 35 V AC 100 A / dm ³ is applied). The insulating film 13 is colored. Alternatively, an aqueous solution of hydrobromic acid (3% to 4%) may be used as the electrolytic solution, and the applied voltage may be set to 25 V to perform anodic oxidation to develop the color. The light-shielding insulating film 13 formed by the above-described color development method is exposed to light of photolithography (wavelength: 360 nm to 470 nm).
Range).

Next, the second step shown in FIG. 1B is performed. In this step, a silicon nitride film 14 for preventing contamination from the transparent substrate 11 is formed on the entire surface on the gate electrode 12 side by, for example, the CVD method. Further, for example, C
The silicon oxide film 15 is formed by the VD method. The light shielding insulating film 13, the silicon nitride film 14, and the silicon oxide film 15 form a gate insulating film 16.

After that, an amorphous silicon layer (not shown) is formed on the gate insulating film 16 by, for example, the CVD method, and then this amorphous silicon layer is modified into a polycrystalline silicon layer by the laser crystallization method. . In this way, a semiconductor layer (not shown) made of a polycrystalline silicon layer is formed. Subsequently, the semiconductor layer is patterned by lithography and etching to form a semiconductor layer pattern 17 that crosses the gate electrode 12.

Although not shown, an amorphous silicon layer is formed and then patterned by lithography and etching to form an amorphous silicon layer pattern. Then, the amorphous silicon layer pattern is formed by a laser crystallization method. The semiconductor layer pattern 17 made of polycrystalline silicon may be formed by crystallization.

Next, the third step shown in FIG. 1C is performed. In this step, the upper insulating film 18 made of, for example, silicon oxide is formed on the entire surface of the transparent substrate 11 by the CVD method, for example. Further, a negative resist film 19 is formed on the upper insulating film 18 by a coating technique. Next, using the light-shielding insulating film 13 as a mask, the transparent substrate 1
The negative resist film 19 is exposed from the 1 side. Then, the exposed negative resist film 19 is developed to remove the negative resist film 19 in the portion indicated by the chain double-dashed line, and a resist pattern 20 is formed with the remaining negative resist film (19).

Then, a fourth step shown in FIG. 1 (4) is performed. In this step, the insulating film pattern 21 is formed of the upper insulating film (18) by etching using the resist pattern 20 as a mask. At this time, the upper insulating film 18 shown by the chain double-dashed line is removed.

After that, the resist pattern (20) is removed. Then, the fifth step shown in (5) of FIG. 1 is performed. In this step, the exposed semiconductor layer pattern 1 is formed by ion doping using the insulating film pattern 21 as a mask.
Into the source / drain regions 22, 2 by introducing impurity ions [eg arsenic ions (As ⁺ ) as n-type ions]
3 is formed.

Thereafter, as shown in FIG. 2, a passivation film 31 made of silicon nitride is formed by the CVD method. Then, by lithography and etching, a contact hole 32 is formed in the passivation film 31,
33 is opened. Then, wiring (not shown) together with the source / drain electrodes 34 and 35 is formed by a wiring forming technique
To form. Then, activation annealing treatment is performed, and further hydrogenation treatment is performed to obtain the thin film transistor 1. In the hydrogenation process in this case, hydrogen can be introduced into the entire surface of the semiconductor layer pattern 17 through the insulating film pattern 21.

Alternatively, although not shown, after forming the wiring forming film, the source / drain electrodes are formed on the source / drain regions 22 and 23 by lithography and etching. Then, the passivation film 31 may be formed. In this case, the insulating film pattern 21 is
It also serves as an etching stopper when forming the source / drain electrodes.

In the embodiment of the first invention described above, as shown in FIG. 3, the light shielding insulating film 1 is formed on the surface of the gate electrode 12.
3 is formed, the length Lsi of the light shielding insulating film 13 becomes longer than the gate length Lg. Then, using the light-shielding insulating film 13 as a mask, the negative resist (1
Since 9) is exposed and further developed, the length Lr of the resist pattern 20 becomes a length almost transferred from the length Lsi of the light-shielding insulating film 13. Furthermore, the resist pattern 2
Insulating film pattern 2 by etching with 0 as a mask
1 is formed, the length Li of the insulating film pattern 21 is
Is the length to which the resist pattern 20 is almost transferred. Therefore, the length of the insulating film pattern 21 is longer than the gate length Lg.

Then, the source / drain regions 22 are formed by ion doping using the insulating film pattern 21 as a mask.
23 is formed, the source / drain regions 22,
23 and an offset 25 between the channel region 24 formed in the semiconductor layer pattern (17) on the gate electrode 12;
26 is formed. Thus, the offsets 25, 26
Therefore, the thin film transistor 1 has a reduced leak current.

Further, according to the manufacturing method described with reference to FIGS. 1 and 2, hydrogen contained in the passivation film 31 can be introduced into the channel region 24. Then, the subsequent annealing treatment makes it possible to reduce defects due to hydrogenation in a short time. Therefore, the throughput is high.

Next, a method of forming the light-shielding insulating film 13 will be described with reference to FIGS. 4, 5 and 6. Each drawing shows a method of coloring the oxide film formed on the surface of the gate electrode for manufacturing the self-aligned offset structure. The colored oxide film must have the effect of a light-shielding mask against exposure from the back surface of the glass substrate. For example, when the wavelength of the irradiation light is 436 nm (G line), the oxide film may be colored in red, green or yellow. As the colored layer, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), copper oxide (II) (CuO), or the like can be used.

For example, the gate electrode is made of aluminum (A
When formed in 1), a so-called alumite coating which is an aluminum oxide coating is formed on the surface of the gate electrode by the anodic oxidation method.

As shown in FIG. 4A, the transparent substrate 11
After forming a gate electrode forming film (not shown) on the gate electrode, the gate electrode forming film is patterned by lithography and etching to form the gate electrode 12. afterwards,
For example, by oxidizing the gate electrode 12 as an anode in a 1% to 3% aqueous solution of hydrobromic acid (25 ° C.), (2) in FIG.
As shown in FIG. 5, a porous aluminum oxide (α-Al ₂ O ₃ ) film 51 is formed on the surface of the aluminum gate electrode 12.
(Corresponding to the light shielding insulating film 13 in FIG. 1) is formed. At that time, opaque colloidal Al ₂ O ₃ .3H ₂ O is first generated on the surface of the anode aluminum, and oxygen (O) is generated by the discharge of OH ⁻ ions in the solution. Then, the generated oxygen reaches the aluminum surface and is converted into dense amorphous aluminum oxide (Al ₂ O ₃ ). At this time, the amorphous aluminum oxide is dissolved by the electrolytic solution and grows while leaving a barrier layer 52 at the aluminum oxide (Al ₂ O ₃ ) / aluminum (Al) interface and forming a plurality of micropores 53 thereon. Go. The size of the micropores 53 is several nm to several tens of nm depending on the conditions of the electrolytic solution, and the depth of the micropores 53 is approximately twice that of the barrier layer 52.

To dye an aluminum oxide layer formed by anodization, an alloy aluminum is used instead of pure aluminum as a material for the gate electrode 12,
The metal can be dispersed in the aluminum oxide film to spontaneously develop color. Even when pure aluminum is used, when an organic acid electrolyte containing a dye is used as the electrolyte, the dye disperses in the alumina coating and is colored.

Next, another coloring method will be described. (1) of FIG.
As shown in, a porous aluminum oxide film 51 is formed on the surface of the gate electrode 12 by the anodic oxidation method. Then, as shown in (2) of FIG. 5, a secondary electrolytic solution treatment is performed to deposit and color the metal layer 54 on the bottoms of the micropores 53 formed in the porous aluminum oxide film 51. In this way, the porous aluminum oxide film 51 is colored.

Further, as shown in FIG. 6A, the gate electrode 12 is formed by patterning a metal film such as tantalum (Ta) by lithography and etching.
In this case, even if anodization is performed, the anodized film formed on the gate electrode 12 does not necessarily become a porous layer.
Therefore, as shown in (2) of FIG. 6, the dye is dispersed in the anodized film 61 formed on the surface of the gate electrode 12 by performing anodization using an organic acid electrolyte containing a dye. . Therefore, the anodic oxide film 61 is colored.

Next, an embodiment of the second invention will be described with reference to the manufacturing process chart of FIG. In the figure, the same components as those described with reference to FIG. 1 are designated by the same reference numerals.

The first described in (1) to (4) of FIG.
The steps from the fourth step are performed in substantially the same manner. That is, as shown in FIG. 7A, the gate electrode 12 is formed on the transparent substrate 11, and the light-shielding insulating film 13 is formed on the surface of the gate electrode 12 by the anodic oxidation method. Next, a silicon nitride film 14 and a silicon oxide film 15 are formed on the entire surface on the gate electrode 12 side. The light shielding insulating film 13, the silicon nitride film 14 and the silicon oxide film 15 serve as the gate insulating film 16. Then, a semiconductor layer pattern 17 is formed on the gate insulating film 16 so as to cross the gate electrode 12. Then, an upper insulating film (18) (including a portion indicated by a chain double-dashed line) in a state of covering the semiconductor layer pattern 17 is formed on the entire surface of the transparent substrate 11. After that, a resist pattern 20 made of a negative resist film (not shown) is formed on the upper insulating film 18 in a state where the light shielding insulating film 13 is almost transferred upward. Next, the insulating film pattern 21 is formed by the upper insulating film (18) by etching using the resist pattern 20 as a mask.

Then, as shown in FIG. 7B, the fifth step is performed. In this step, after removing the resist pattern (20), a conductive type impurity (for example, n ⁺ ) is connected to the semiconductor layer pattern 17 to cover the insulating film pattern 21.
A doped layer 27 containing a type impurity) is formed.

Then, by laser irradiation, the conductive impurities in the doped layer 27 are diffused into the semiconductor layer pattern 17 in the portion connected thereto. This treatment is performed on the doped layer 2
After patterning 7, an activation annealing process may be performed. Next, an electrode forming film (not shown) is formed by, for example, the stopper method.

Then, as shown in (3) of FIG. 7, the doped layer (2
7) is patterned to form the source / drain regions 22,
23 and source / drain electrodes 36, 3 connected to them
Form 7. Next, the passivation film 38 made of silicon nitride is formed by, for example, the CVD method. Then, activation annealing treatment is performed, and further hydrogenation treatment is performed to obtain the thin film transistor 2.

Alternatively, although not shown, after the conductive impurities in the doped layer 27 are diffused into the semiconductor layer pattern 17,
The doped layer 27 is patterned by lithography and etching to form the source / drain regions 22 and 23. Next, a passivation film is formed, and hydrogenation treatment and annealing treatment are performed. After that, after forming a contact hole communicating with the source / drain regions 22 and 23 in the passivation film, an electrode forming film may be formed and a source / drain electrode may be formed by lithography and etching.

In the embodiment of the second invention described above, as shown in FIG. 8, the length Li of the upper insulating film pattern 21 is formed longer than the gate length Lg as in the case of the first invention. . Then, a doped layer 27 is formed so as to cover the insulating film pattern 21, and conductive impurities are diffused from the doped layer 27 into the semiconductor layer pattern 17 to form the source / drain regions 22,
23 to form each source / drain region 2
2, 23 are not formed in the semiconductor layer pattern 17 covered with the insulating film pattern 21. Therefore, the source
Offsets 25 and 26 are formed between the drain regions 22 and 23 and the channel region 24 formed in the semiconductor layer pattern 17 above the gate electrode 12.

Further, in the above manufacturing method, since the source / drain regions 22 and 23 are formed by diffusion, ion implantation is not necessary. Therefore, no defects are generated by the ion implantation. Further, since the insulating film pattern 21 serves as an etching stopper when the doped layer 27 is etched, etching damage is not applied to the underlying semiconductor layer pattern 17.

Further, hydrogen contained in the passivation film 38 can be introduced into the channel region 24 through the insulating film pattern 21. Then, the subsequent annealing treatment makes it possible to reduce defects due to hydrogenation in a short time. Therefore, the throughput is high.

Next, an embodiment of the third invention will be described with reference to the manufacturing process chart of FIG. In the figure, the same components as those described with reference to FIG. 1 are designated by the same reference numerals.

The first described in (1) and (2) of FIG.
The process and the second process are performed in substantially the same manner. That is, as shown in FIG. 9A, the gate electrode 12 is formed on the transparent substrate 11.
And the light-shielding insulating film 1 is formed on the surface by the anodic oxidation method.
3 is formed. Next, a silicon nitride film 14 and a silicon oxide film 15 are formed on the entire surface on the side of the gate electrode 12 to form a gate insulating film 16. Then, a semiconductor layer pattern 17 is formed on the gate insulating film 16 so as to traverse the gate electrode 12. Here, the semiconductor layer pattern 17 is formed of amorphous silicon.

Next, the third step shown in FIG. 9B is performed. In this step, a negative resist film 19 is formed on the entire surface of the transparent substrate 11 with the semiconductor layer pattern 17 covered by a normal coating technique. Then, the negative resist film 19 is exposed from the transparent substrate 11 side using the light shielding insulating film 13 as a mask, and then developed to form a resist pattern 20 made of the negative resist film (19).

Subsequently, the fourth step shown in FIG. 9C is performed. In this step, the doped layer 2 containing conductive impurities (for example, n-type impurities) is formed on the entire surface on the resist pattern 20 side.
8 is formed. Then, the resist pattern 20 and the doped layer 28 on the upper surface thereof are removed by a lift-off method.

Thereafter, a fifth step shown in FIG. 9 (4) is performed. In this step, the semiconductor layer pattern 17 and the doped layer 28 left by the lift-off method are crystallized by the excimer laser annealing process, and the semiconductor in the portion where the conductive impurities in the doped layer 28 are connected to the doped layer 28. Source / drain regions 22 and 23 are formed by diffusing into the layer pattern 17.

Thereafter, as shown in FIG. 11, source / drain electrodes 39, 40 connected to the source / drain regions 22, 23 are formed by a wiring forming technique. Next, the passivation film 41 made of silicon nitride is formed by, for example, the CVD method. After that, activation annealing treatment is performed, and further hydrogenation treatment is performed to obtain the thin film transistor 3.

In the embodiment of the third invention described above, as shown in FIG. 11, as in the case of the first invention, exposure and development using the light shielding insulating film 13 formed on the surface of the gate electrode 12 as a mask. Since the resist pattern 20 is formed by the above, the length Lr of the resist pattern 20 is formed longer than the gate length Lg. And the doped layer 28
After the formation of the resist pattern, the resist pattern 20 and the doped layer 28 on the upper surface thereof are removed by the lift-off method.
The length Lo of the portion where the doped layer 28 is removed is the gate length Lg.
Will be longer than. Therefore, the distance between the source / drain regions 22 and 23 formed by the doped layer 28 left by the lift-off method and the semiconductor layer pattern 17 connected thereto becomes longer than the gate length Lg. Therefore, offsets 25 and 26 are formed between the source / drain regions 22 and 23 and the channel region 24 formed in the semiconductor layer pattern 17 above the gate electrode 12.

Further, in this manufacturing method, since the source / drain regions 22 and 23 are formed by diffusing the conductive impurities of the doped layer 28 into the semiconductor layer pattern 17, ion implantation is not necessary. Therefore, no defects are generated by the ion implantation. Further, since the doped layer 28 is patterned by the lift-off method, the semiconductor layer pattern 17 is not damaged by etching.

According to the above process, as shown in FIG. 10, hydrogen contained in the passivation film 41 can be introduced into the semiconductor layer pattern 17 in which the channel region is formed. Then, the subsequent annealing treatment makes it possible to reduce defects due to hydrogenation in a short time. Therefore, the throughput is high.

[0051]

As described above, according to the first aspect of the invention, since the light shielding insulating film is formed on the surface of the gate electrode, the length of the light shielding insulating film is longer than the gate length. Since a resist pattern composed of a negative type resist film is obtained by exposure using the light-shielding insulating film as a mask, the insulating film pattern formed by using the resist pattern is used as a mask to perform ion doping to form the source / drain regions. The source / drain regions can be formed at positions apart from the gate electrode in the gate length direction. Therefore, a self-aligned offset can be formed between the source / drain region and the channel region formed in the semiconductor layer pattern on the gate electrode. Since such a self-aligned offset structure can be easily formed, it becomes possible to easily manufacture a thin film transistor having a small leak current.

According to the second aspect of the invention, similarly to the first aspect of the invention, the length of the insulating film pattern can be formed longer than the gate length, and the semiconductor layer pattern not covered with the insulating film pattern can be formed into a source / source layer. Since the drain region can be formed, an offset can be formed by self-alignment between the source / drain region and the channel region formed in the semiconductor layer pattern above the gate electrode. Since such a self-aligned offset structure can be easily formed, a thin film transistor with a small leak current can be easily manufactured.

According to the third aspect of the invention, as in the first aspect of the invention, the length of the light-shielding insulating film can be formed longer than the length of the gate electrode. The resist pattern of the negative resist can be formed longer than the gate length. Since the doped layer is left on the semiconductor layer pattern by the lift-off method using this resist pattern and the source / drain regions are formed by impurity diffusion from the doped layer, the source / drain region and the semiconductor layer pattern above the gate electrode are formed. An offset can be formed in self alignment with the channel region. Since such a self-aligned offset structure can be easily formed, it becomes possible to easily manufacture a thin film transistor having a small leak electrode.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram illustrating an embodiment of the first invention.

FIG. 2 is a cross-sectional view of an electrode forming method.

FIG. 3 is an explanatory diagram of offset.

FIG. 4 is an explanatory diagram of a dyeing method by natural coloring.

FIG. 5 is an explanatory diagram of a dyeing method by a secondary electrolytic solution treatment.

FIG. 6 is an explanatory diagram of a method for dyeing an anodized film of tantalum.

FIG. 7 is a manufacturing process diagram illustrating an embodiment of the second invention.

FIG. 8 is an explanatory diagram of offset.

FIG. 9 is a manufacturing process diagram illustrating an embodiment of the third invention.

FIG. 10 is a cross-sectional view of an electrode forming method.

FIG. 11 is an explanatory diagram of offset.

FIG. 12 is a schematic sectional view of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 thin film transistor 2 thin film transistor 3 thin film transistor 11 transparent substrate 12 gate electrode 13 light-shielding insulating film 15 gate insulating film 16 semiconductor layer pattern 17 upper insulating film 18 negative resist film 19 resist pattern 20 insulating film pattern 21 source / drain region 22 source / drain region 27 Doped layer 28 Doped layer

Claims (3)

[Claims] 1. A first step of forming a gate electrode on the surface of a transparent substrate having an insulating property at least on the surface side, and then forming a light-shielding insulating film that shields light of at least a predetermined wavelength on the surface of the gate electrode. A second step of forming a gate insulating film on the gate electrode, and then forming a semiconductor layer pattern across the gate electrode on the gate insulating film, and an upper insulating film and a negative type film on the entire surface of the transparent substrate. Forming a resist film in order, exposing the negative resist from the transparent substrate side using the light-shielding insulating film as a mask, and then developing the resist film to form a resist pattern; and the resist pattern. And a fourth step of forming an insulating film pattern on the upper insulating film by etching using the mask as a mask, and ion doping using the insulating film pattern as a mask. A method of manufacturing the thin film transistor characterized by comprising a fifth step of forming a source and drain region by introducing impurity ions into the semiconductor layer pattern are. 2. A first step of forming a gate electrode on the surface of a transparent substrate having an insulating property at least on the surface side, and then forming a light-shielding insulating film that shields light of at least a predetermined wavelength on the surface of the gate electrode. A second step of forming a gate insulating film on the gate electrode, and then forming a semiconductor layer pattern across the gate electrode on the gate insulating film, and an upper insulating film and a negative type film on the entire surface of the transparent substrate. Forming a resist film in order, exposing the negative resist from the transparent substrate side using the light-shielding insulating film as a mask, and then developing the resist film to form a resist pattern; and the resist pattern. A fourth step of forming an insulating film pattern on the upper insulating film by etching using the mask as a mask; and, after removing the resist pattern, connecting to the semiconductor layer pattern. Therefore, a doped layer containing conductive impurities is formed on both sides of the insulating film pattern, and the conductive impurities in the doped layer are diffused into the semiconductor layer pattern at a portion connecting to the doped layer, and then the doped layer is formed. And a fifth step of forming source / drain regions by patterning. 3. A first step of forming a gate electrode on the surface of a transparent substrate having an insulating property at least on the surface side, and then forming a light-shielding insulating film that shields light of at least a predetermined wavelength on the surface of the gate electrode. A second step of forming a gate insulating film on the gate electrode and then forming a semiconductor layer pattern across the gate electrode on the gate insulating film, and forming a negative resist film on the entire surface of the transparent substrate. After forming the film, the negative type resist is exposed from the transparent substrate side using the light shielding insulating film as a mask, and then developed to form a resist pattern, and a conductive type is formed on the entire surface of the resist pattern side. A fourth step of removing the resist pattern and the doped layer on the resist pattern by a lift-off method after forming a doped layer containing impurities; The conductivity type impurity of said doped layer leaving the diffused into the semiconductor layer pattern portion connected to the doped layer 5 to form the source and drain regions
A method of manufacturing a thin film transistor, comprising the steps of: