JPH0350838A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the integration of a semiconductor device thereby enabling reduction of the number of processes by forming a plurality of electrodes without a gap to the face direction in the element formation area of a semiconductor layer, and forming an oxide insulating film, using an electrode as a mask. CONSTITUTION:A plurality of electrodes 3 are formed without a gap to the face direction in the element formation area 2 of a semiconductor layer 1. After formation of the electrodes 3, oxygen ions are implanted, using the electrode 3 as a mask, into at least an element isolating region 4 provided around the element formation area 2, so as to form an oxide insulating layer 5. It follows that the region of the semiconductor substrate, to which ions are implanted, is oxided and there an insulating layer 5 is formed in a self alignment manner. Accordingly, the necessity to form a protective mask when forming the insulating layer 5 at the element isolating region 5 disappears, and there is no necessity to specially provide an error region required for alignment of the protective mask.

Description

[Detailed Description of the Invention] (If!t Required) Regarding a method for manufacturing a semiconductor device having a step of separating elements in a semiconductor integrated circuit, the present invention provides a method for manufacturing a semiconductor device having a step of separating elements in a semiconductor integrated circuit, which performs element isolation with high accuracy and reduces the number of steps for forming an insulating layer for element isolation. For the purpose of and forming an oxide insulating layer by implanting oxygen ions into the element isolation region.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a step of forming an insulating layer for isolation between elements in a semiconductor integrated circuit.

In recent years, with the increase in the scale of semiconductor integrated circuits, there has been an increasing need for miniaturization of semiconductor elements. This requires not only miniaturization of each electrode but also miniaturization of the active region of the element, and it is necessary to form the element with high precision within a fine active region.

Furthermore, in the element forming process, there is a demand for simplification and shortening of the process in order to improve the yield of elements, reduce costs, and the like.

[Prior Art] In a semiconductor device formed on a semiconductor substrate, an insulating layer is formed to isolate elements from each other. As shown in the figure, a protective mask 32 made of gold, resist, etc. is formed on the element formation region 31 of the semiconductor substrate 30, and oxygen ions (oz'') are implanted from above to form the semiconductor substrate around the protective mask 32. 30 is oxidized to form an insulating layer 3.
There are some that are 3.

When forming an element in the element formation region 31,
After removing the protective mask 32, the ohmic electrode 34. A gate electrode 35 and the like are to be formed.

[Problem to be solved by the invention]

By the way, the insulating layer 3 for element isolation is formed by implanting oxygen ions.
3, it is necessary to form the protective mask 32 larger in area than the actual element forming region 31 in consideration of the alignment accuracy of the protective mask 32, which hinders high integration of semiconductor devices. There is a problem of becoming.

Moreover, when forming this type of protective mask 32,
Multiple processes that are not directly related to element formation, such as forming a film that will become the protective mask 32, applying resist, exposing, developing, and removing the protective mask. This has the disadvantage that the manufacturing process of the semiconductor device becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can perform element isolation with high precision and reduce the number of steps required to form an insulating layer for element isolation.

[Means for Solving the Problems] The above-mentioned problems can be solved by the semiconductor I? After the process of forming a plurality of electrodes 3 without gaps in the plane direction in the element formation region 2 of 51 and the formation of the three electrodes 3, using the Ti electrode 3 as a mask, at least the element formation region 2 is formed. The present invention is solved by a method for manufacturing a semiconductor device characterized by comprising a step of injecting oxygen ions into an element isolation region 4 provided around a semiconductor device to form an oxide insulating layer 5.

[For production]

According to the present invention, when a plurality of electrodes 3 are provided on the semiconductor layer 1, the electrodes 3 are formed so that there are no gaps in the planar direction between the electrodes 3. After this, oxygen ions are implanted from above using the electrode 3 as a mask, and the oxygen ions are implanted into the element isolation region 4 around the element formation region 2 covered by the plurality of electrodes t)3.

Therefore, the region of the semiconductor substrate 1 into which ions are implanted is
The insulating layer 5 is formed in a self-aligned manner through oxidation.

Therefore, when forming the insulating layer 5 in the element isolation region 4, there is no need to form a protective mask, and there is no need to particularly provide an error region necessary for alignment of the protective mask.
Semiconductor devices can be further integrated, and the time and effort of forming and removing protective masks is no longer required, making it possible to improve the I/O quality of semiconductor devices. I! Man-hours can be reduced.

[Example] FIG. 2 is a process diagram showing an example of the present invention in cross section, and the reference numeral 11 in the figure indicates HE M T (high eIe
cLron mobility transistor also or
) to form a semi-insulating group (11) made of GaAs; on top of this group (11) there is a buffer layer 12 made of non-doped gallium arsenide (i-GaAs); an electron transit layer 13 made of n-type aluminum gallium arsenide (n-AIGaAs) doped with impurities;
and a cap layer 15 made of n-type gallium arsenide (n-GaAs) are laminated in this order. These layers 12-15
is formed by epitaxial growth.

In this state, first, as shown in FIG.
12 (SiO□ film) 16 is formed to a thickness of about 6,000 layers, a resist 17 is spread on it, and the resist 17 is further exposed and developed to form a central portion of the gate electrode forming area. A window 18 is formed in the area.

After this, the 5iO7 film 16 exposed from the window 1B is etched to form a gate opening 19 (FIG. 2(b)).
. Etching in this case is performed by a reactive ion etching method, using an etching gas containing, for example, CF4.

Next, titanium (Ti), platinum (Pt), and gold (ΔU) were sequentially formed to a thickness of 1000, 1000, and 3000, respectively, on top of this three-layer Ti-PL/^U film 20. By applying a resist 21, exposing it to light, and developing it, the resist 21 remains in the gate electrode formation area A, and using this as a mask, the Ti/Pt/Au film 20 is R
When etching IE film type 0, Ti/Pt/Au film 2
0 is formed to have a T-film shape in cross section. The Ti/Pt/^U film 20 patterned in this way is
(Figure 2 (C)).

After this, the 5in2 film 16 is completely covered using the gate ring (22) which has a T-shaped cross section as a mask! When etching is performed from 'Jl, the camp layer 15 is exposed and the gate ring (
A total of 16 SiO□ films 16 are formed on both sides of the legs 23 at t22. In this case, the patterned Si0□ film 16
The gate electrode 22 is etched until the width between both ends becomes narrower than the head 24 of the gate electrode 22, so that the head 24 protrudes like an eave (FIG. 2(d)).

The resist 21 is then peeled off.

Next, a new resist 25 is applied, exposed and developed to leave the resist 25 in areas other than the element forming KW area B (FIG. 2(e)).

In this state, as shown in FIG. 2(f), resist 25. Gate 7J, pole 22
AuGe/Au film 26 is formed on the cap layer 15 on both sides of the gate electrode 22.
The 8uGe/heU film 26, which is deposited on the camp layer 15, becomes an ohmink electrode 27, 28.

In this case, since the gate electrode 22 protrudes to the sides of the SiO□ film 1G like an eaves, the gate ring (YuGe/Au′v! 26 formed on both sides of the gate ring 22) The AuGe/Au film 26 on 22 is in contact with the 26 sag,
It is no longer connected to the gate electrode 22.

Here, the AuGe/Au film 26 on the resist 25 is removed by the riff-on method, while the AuGe/Au film 26 on the gate 7J and the pole 22 is left as is.

In such a state, the Ohminck electrode i27.28 is formed in a self-aligned manner and there is no gap in the plane direction between it and the gate electrode 22, so at this stage I OO~200K
When oxygen ions (0□゛) are absorbed by 't% in a Dawes star with an energy of eV and 1×IQ12/Cm2 (Fig. 2 (
g)) The ohmink electrodes 27 and 28 and the gate electrode 22 act as a protective 3W mask, and oxygen ions are not implanted into the element formation region B, but only into the head region C corresponding to the amount of elements around it. Then, the insulating layer 29 is formed by oxidizing each layer from the substrate 11 to the cap layer X5 in that region. Here, the width of the ion implantation is approximately 300 nm.
(Figure 2 (h)).

Note that in the above-mentioned embodiment, hydronic acid was used when etching the entire SiO□ film 16, but nitrogen trifluoride (NF3
) and plasma etching is also possible.

Furthermore, in the above embodiment, the SiO□ film 16 was formed on both sides of the gate electrode having a T-shaped cross section, but a silicon nitride film could also be used, and the gate electrode and the Ohminck electrode [ The material is not limited to the above embodiments either.

Furthermore, the above-mentioned embodiments are for element isolation when creating HE to IT! I! ! , explained the formation of the marginal layer, but
M E S F E T (MeLal Semtco
nductor F1a1edEffect Tran
sistor), etc., 1M electrodes are formed without any gaps in the plane direction, and then oxygen ion 4
It is also possible to form an insulating layer for one element by injecting it into a semiconductor layer.

[Effects of the Invention] As described above, according to the present invention, when a plurality of electrodes are provided over the entire element formation region of a semiconductor layer, gaps in the planar direction are prevented from occurring between the electrodes, and in this state, ,
Oxygen ions are implanted using the electrode as a mask, and the oxygen ions are made to be the main ion in the element isolation region around the electrode, so an insulating layer is formed in a self-aligned manner in the semiconductor layer where one ion is the main ion. It turns out.

Therefore, there is no need for a protective mask when forming an insulating layer for element isolation, and there is no need to specifically provide an error area for positioning the protective mask (which allows semiconductor devices to be more highly integrated and , formation of a protective film,
Since the effort of removal etc. is no longer necessary, the number of steps for manufacturing the semiconductor device can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is a process diagram showing an embodiment of the present invention in cross section; FIG. 3 is a process diagram showing a conventional method in cross section. (Explanation of symbols) l... semiconductor layer, 2...Element formation region, 3... Electrode, 4...Element formation region, 5... Insulating layer, 1... board, 2... buffer layer, 3...electron transport layer, 4...electron supply layer, 5...kiya, pu layer, 6...SiO□ film, 9...Gate opening, 0・-4i/Pt/Au film, 2...gate electrode, 6-AuGe/Au film, 7.28...Ohmic electrode, 9...Insulating layer.

Claims (1)

[Claims] A step of forming a plurality of electrodes without gaps in the plane direction in an element formation region of a semiconductor layer, and using the electrodes as a mask to form an element provided at least around the element formation region. 1. A method of manufacturing a semiconductor device, comprising the step of implanting oxygen ions into a separation region to form an oxide insulating layer.