JPH02310932A - Manufacture of inverted stagger-type thin-film transistor - Google Patents

Abstract

PURPOSE:To omit a photolithographic process and an etching process and to reduce the number of processed by a method wherein a doped layer is formed in such a way that impurities are contained directly in a semiconductor by using a plasma doping method by making use of a protective layer on a semiconductor layer as a mask. CONSTITUTION:A second nitride Si insulating film 109 situated in an uppermost layer is processed by using a photolithographic technique and a dry etching technique; it is patterned as a protective film 110 at the upper part of a gate electrode 102. An a-Si:H semiconductor film 104 is exposed to a high-frequency plasma in an atmosphere of phosphine gas 111 using hydrogen as a base under conditions at a pressure of 200 Pa, at a substrate temperature of 200 deg.C and an RF output of 0.05W/cm<2>; phosphorus is plasma-doped; a doped layer 105 is formed. Under the doping conditions, a phosphorus concentration in a-Si:H in the doped layer 105 amounts to 10<20> to 10<21> (atm/cm<2>) and displays a sufficient n<+> characteristic as an ohmic contact layer. During this plasma doping process, the sufficiently thick protective film 110 disturbs that phosphorus is plasma-doped to the a-Si:H film at its lower part; as a result, it is not required to use a photoresist or the like especially.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing an inverted staggered thin film transistor. More specifically, the present invention relates to a method of manufacturing an inverted staggered thin film transistor of a thin film transistor array used in a liquid crystal display, etc.

BACKGROUND ART Display devices using liquid crystals are attracting the most attention as flat-panel displays that can replace television picture tubes because they have low power consumption, are small and lightweight, and can relatively easily handle full-color display. Among them, the active matrix type, in which each pixel that makes up the screen is provided with an active element such as a transistor to drive it, is currently in high demand as it provides a high contrast ratio and is also advantageous for high definition and large screens. This method is currently being researched.

Active element systems used in this active matrix system include a three-terminal thin film transistor (hereinafter referred to as TPT) system and a two-terminal element nonlinear diode (hereinafter referred to as M
Currently, the TFT method is the mainstream due to its ease of drive control and advantageous contrast ratio.

However, in the case of this TFT method, the number of steps is large due to the complexity of the element structure, and the resulting high cost and reduction in yield are major problems.

Conventional methods for manufacturing thin film transistors of this type are roughly divided into two types: channel digging type and terminal digging type. Second
Figures (a) to (f) illustrate the channel digging type process. In this step, first, a gate electrode 202 is formed on a glass substrate 201 (FIG. 2(a)). On top of that, Si nitride
(SiN) insulation film 203, hydrogenated amorphous silicon (hereinafter referred to as a-Si:H) semiconductor film 204, and a low resistance doping film 205 for ensuring ohmic contact with the electrodes are formed by a method such as plasma CVD. (Figure 2)). Thereafter, the semiconductor film and the doped film are processed into an island layer 206 by etching (FIG. 2(C)). Furthermore, after forming source 207 and drain 208 electrodes thereon (FIG. 2(d))
Then, the doped film 205 is etched to form a channel (FIG. 2(e)), and a Si nitride protective layer 210 is formed to complete the TPT (FIG. 2(f)).

Further, FIGS. 3(a) to 3(g) illustrate the terminal digging type process. In this step, a gate electrode 302 is formed on a substrate 301 (FIG. 3(a)), and a first Si nitride insulating film 303, an a-3i:H semiconductor film 304, and a second nitride S1 are formed thereon. An insulating film 309 is formed by a method such as plasma CVD (see FIG. 3). Next, the second nitride S1 insulating film 309 is etched to form a protective film 310 (FIG. 3C), and the a-3i:H semiconductor film 304 is further etched to form an island layer 306 (FIG. 3C).
Figure (d)).

Then, a low resistance Si:H doped film 305 to ensure ohmic contact with the electrode is formed by plasma CVD.
After forming the island layer 306 by a method such as D (FIG. 3(e)), it is separated into a source portion and a drain portion by etching (FIG. 3(f)), and then a source is formed on each of them. A TPT is formed by forming an electrode 307 and a drain electrode 308 (third
Figure ((a)).

Problems to be Solved by the Invention Among the conventional TPT manufacturing methods described above, in the channel trench type, a margin for the thickness of the semiconductor film must be made large due to the problem of controllability of the trench depth by etching. Therefore, there is a problem that the electrical characteristics of TPT cannot be fully exhibited. For example, the doping film thickness is 5
If the doped film in a plane of 100 mm x 100 mm is completely removed by etching, the underlying semiconductor film will also be over-etched by about 500 to 1,000 people. When calculating this thickness, the thickness of the semiconductor film must be at least 2000. For this reason, other TPs formed with about 200 semiconductor layers
Compared to a T element, the ON current is reduced to less than half, and the photocarrier generation rate is significantly increased, resulting in a disadvantage that the OFF resistance during light irradiation is lowered.

Furthermore, in the terminal digging type process, the doping film is formed after the island layer is formed. Therefore, the interface between the doped film and the semiconductor film comes into contact with the atmosphere, water, photoresist, and the like. Therefore, the electrical characteristics of TPT deteriorate. Furthermore, there is a drawback that the number of man-hours inevitably increases due to doping film formation, photophosphorography, and etching.

The above-mentioned doping film is indispensable for ensuring ohmic contact between the source electrode and the drain electrode and the semiconductor film in both the channel digging type and terminal digging type methods.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an inverted staggered thin film transistor that solves the problems of the prior art described above, requires less man-hours, and provides a high-performance TPT.

Means for Solving the Problems According to the present invention, a gate electrode formed on a substrate, a semiconductor island layer formed on the gate electrode via an insulating layer, and a semiconductor island layer each doped with an impurity. A method for manufacturing an inverted staggered thin film transistor comprising a source electrode and a drain electrode coupled via a semiconductor film, in which a first insulating film, a semiconductor film and a second the second insulating film is formed as a protective layer, and using the protective layer as a mask, a portion of the semiconductor film not covered with the protective layer is subjected to plasma doping. There is provided a method for manufacturing an inverted staggered thin film transistor, characterized in that a portion of the semiconductor film covered with the protective layer is formed into a semiconductor island layer by doping with impurities.

Function: In contrast to the conventional manufacturing method of an inverted stagger type thin film transistor, the method of the present invention does not form a doping layer on the semiconductor film, and exposes the first insulating film, the semiconductor film, and the second insulating film to the atmosphere. Films are formed by laminating them continuously. After that, a part of the semiconductor film is made into a doped layer by a plasma doping method. Therefore, a thin film transistor can be formed without contaminating the film interface, and since doping is performed after masking the channel portion with a protective layer, there is no need to dig a channel. Therefore, the semiconductor layer can be made thinner, the number of photolithography and etching steps can be reduced, and an inverted staggered thin film transistor with good electrical characteristics can be manufactured with fewer steps than before.

EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention in any way.

Example 1 FIGS. 1(a) to 1(f) show an example of a process according to the method of the present invention using longitudinal cross-sectional views of a device.

First, as shown in FIG. 1(a), a gate electrode 102 is formed on a glass substrate 101. In this embodiment, a glass substrate 101 with a thickness of 1 mm whose surface has been polished with a low alkali is used. A metal chromium film was formed on this surface to a thickness of 1400 mm by sputtering, and then a gate electrode 102 with a desired pattern was formed using dry etching technology.

Next, as shown in Fig. 10)), the first
A-3i with a nitride S1 insulating film 103 and a film thickness of 150:
H semiconductor film 104 and second nitrided film 5 with a film thickness of 3500 A
The ilA edge film 109 and the ilA edge film 109 were sequentially formed by plasma CVD in a film forming chamber without being exposed to the atmosphere.

The plasma CVD apparatus used was a parallel plate electrode type device in which the above-described film formation could be performed in an independent film formation tank for each film.

Thereafter, as shown in FIG. 1C, the second nitride S1 insulating film 109 in the uppermost layer is processed using photolithography and dry etching techniques, and patterned as a protective film 110 above the gate electrode 102. did.

This dry etching is performed in plasma discharge at a pressure of approximately 10 Pa using an etching gas containing carbon tetrafluoride and oxygen as main components, thereby ensuring a sufficient etching selectivity with respect to the a-5i:H semiconductor film 104. It can be made large.

Next, as shown in FIG. 1(d), the a-3i:H semiconductor film 104 was patterned into an island layer 106 by dry etching. This dry etching is performed in a plasma discharge at a pressure of 10 Pa using an etching gas containing carbon tetrachloride, oxygen, and helium as main components, so that the etching selectivity with respect to the first Si nitride insulating film 103 in the lower layer is sufficiently high. It is possible to take a large amount.

Next, as shown in FIG. 1(e), using the protective film 110 as a mask, a hydrogen-based phosphine gas 111 with a pressure of 200 Pa and a substrate temperature of 200
The a-3i:H semiconductor film 104 was exposed to high frequency (13.56 MHz) plasma under the conditions of 0.degree. Under this doping condition,
a-3i of doping layer 105: Phosphorus concentration in H is 1
020 to 10" (atm/cnf), exhibiting sufficient n' characteristics as an ohmic contact layer. In this plasma doping process, a sufficiently thick protective film 110 is deposited onto the underlying a-3i:H semiconductor film. There is no particular need to use a photoresist or the like since it prevents plasma doping of phosphorus.

Then, as shown in FIG. 1(f), a metal chromium film with a thickness of 2000 mm was formed by sputtering, and this was etched using dry etching to form the source electrode 10.
7 and a drain electrode 108 are formed.

By performing the above etching under reduced pressure of about 10 Pa using a mixed gas of carbon tetrachloride and oxygen as an etchant, a sufficiently large selectivity with respect to the underlying Si nitride film 110 can be ensured.

Through the above steps, the formation of an inverted staggered thin film transistor according to the method of the present invention is completed.

Example 2 FIGS. 4(a) to 4(f) show schematic longitudinal cross-sectional views of steps in a second example of the method of the present invention. Figure 4 (a) to (C)
The steps are completely (equal) to the steps in FIGS. 1(a) to (C) of Example 1.

1++u surface polished with low alkali as in Example 1
After forming a metal chromium film to a thickness of 1,400 mm on a glass substrate 401 with a thickness of n by sputtering, a gate electrode 402 is formed using a dry etching technique (see FIG. 4).
a)). Next, using a plasma CVD apparatus similar to that in Example 1, a first Si nitride insulating film 403 with a thickness of 3000 was formed.
, an a-5i:H semiconductor film 404 with a thickness of 150 mm and a second nitride S1 insulating film 409 with a thickness of 3500 mm were successively deposited in a deposition chamber without exposure to the atmosphere (see Fig. 4). b)). Thereafter, the second Si nitride film 409 was processed using photolithography and dry etching techniques to form a pattern as a protective film 410 above the gate electrode 402 (FIG. 4(C)).

Next, as shown in FIG. 4(d), using the protective film 410 as a mask, 5000 ppm of hydrogen-based phosphine gas 41
1 atmosphere, pressure 200 Pa, substrate temperature 200°C,
High frequency (13,56
In MI(z) plasma, a-3i:H semiconductor film 40
4 is subjected to phosphorus plasma doping to form a doped layer 4.
05 was formed.

Furthermore, as shown in FIG. 4(e), a doping layer 405
was etched by photolithography and dry etching to form an island layer 406.

The above etching was performed except for the portions of the doped layer 405 that would form ohmic contacts with the source and drain electrodes. For the etchant, a mixed gas containing carbon tetrachloride, oxygen, and helium as main components is used, and a pressure of 1
By etching at 0 Pa and RF output of 0.25 W/ctl, a sufficiently large selectivity with respect to the underlying nitride S1 film 403 could be obtained.

Finally, as shown in FIG. 4(f), a 2000 layer metal chromium film was formed by sputtering, and then a source electrode 407 and a drain electrode 408 were formed using photolithography and dry etching. . By using a mixture of carbon tetrachloride and oxygen as the etchant and performing etching at a pressure of 8 Pa and an RF output of 0.20 W/ci, sufficient selectivity with respect to the underlying Si nitride films 403 and 410 can be ensured. Ta.

In the method of this example, during the plasma doping shown in FIG. 4(d), since the a-3i:H film is on the entire surface,
It is possible to prevent excess impurities from diffusing into the Si nitride film 03 which is the gate insulating film.

FIG. 5(a) shows the man-hour ratio between the conventional channel digging type manufacturing method and the plasma doping type manufacturing method of the present invention, assuming that the number of steps in the conventional terminal digging type manufacturing method is 100%. In addition, the drain voltage 10 of the thin film transistors manufactured using the respective manufacturing methods is shown in FIG.
The relationship between source current and gate voltage when V is applied is shown.

The method of the present invention requires fewer man-hours than any of the conventional methods, and since there is no need to dig a channel, the thickness of the semiconductor film can be designed to be extremely thin. Therefore, the ON current is improved due to the increase in carrier mobility, and the O due to the decrease in photocarriers.
This has effects such as improving (increasing) FF resistance.

As described in detail, the manufacturing method of the inverted staggered thin film transistor of the present invention includes forming a doping layer to ensure ohmic contact between the semiconductor film and the electrode metal, and forming a protective layer on the semiconductor film. This is done by directly incorporating impurities into the semiconductor using a plasma doping method using a mask as a mask.

However, since the photophosphorographic and etching steps for the doped layer can be omitted, the number of steps can be reduced.

In addition, all films except the metal film for electrodes are formed in the same vacuum process, and the film interface is kept clean without being exposed to the atmosphere or photoresistors, which has the effect of improving the stability of film characteristics. .

Furthermore, in the method for manufacturing an inverted staggered thin film transistor of the present invention, a conventional plasma CVD apparatus for forming a doping film can be used almost as is as equipment for plasma doping, so new dedicated equipment is introduced. There is no need to do this, and it can be implemented at low cost in terms of manufacturing equipment.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are diagrams schematically showing longitudinal cross-sectional views of an embodiment of the method for manufacturing an inverted staggered thin film transistor of the present invention, and FIGS. 2(a) to (f) ) is a schematic vertical cross-sectional view showing a conventional method for manufacturing a channel-engraved inverted staggered thin film transistor;
4(g) is a schematic vertical cross-sectional view showing a conventional method for manufacturing a terminal recessed type of an inverted staggered thin film transistor, and FIGS. FIG. 5(a) is a diagram showing another embodiment of the manufacturing method of a submerged film transistor in a schematic vertical cross-sectional view, and FIG. Graphs (Figures 5 and 5) show thin films produced by the production method of the present invention. 1 is a graph showing electrical characteristics of a transistor and a 1ttL thin film transistor manufactured by a conventional manufacturing method. [Main reference numbers] 101, 201.301.401...Glass substrate 10
2, 202.302.402...gate electrode 103,
203.303.403---First insulating film (SiN,
film) 104, 204.304.404...semiconductor film (
a-Si:H film) 105, 205.305.405... Doping layer 1
06, 206.306.406...Island layer 10
7, 207.307.407...source electrode 108,
208.308.408...Drain electrode 109, 2
09.309.409 ---Second insulating film (SiN,
film) 110, 210.310.410...protective layer 11
1, 411...Plasma-excited doping layer strip

Claims (1)

[Claims] A gate electrode formed on a substrate, a semiconductor island layer formed on the gate electrode via an insulating layer, and each of the semiconductor island layers doped with an impurity.
In a method for manufacturing an inverted staggered thin film transistor comprising a source electrode and a drain electrode coupled through a semiconductor film, a first insulating film, a semiconductor film and a second insulating film are disposed on a substrate surface including the gate electrode. Insulating films are successively laminated, the second insulating film is formed as a protective layer, and using the protective layer as a mask, a portion of the semiconductor film not covered with the protective layer is doped with impurities by plasma doping. A method for manufacturing an inverted staggered thin film transistor, characterized in that a portion of the semiconductor film covered with the protective layer is used as a semiconductor island layer.