KR20010043439A - Field emission device, its manufacturing method and display device using the same - Google Patents

Abstract

Amorphous substrates; Impurity diffusion prevention layer; A FET formed on the formation surface of the semiconductor layer made of amorphous silicon or polycrystalline silicon; One or more emitters made by etching the semiconductor layer in the FET drain region; And a field emission device (FED) including an extraction electrode. The semiconductor layer is made by a CDV process. The emitter array is formed in a ring or polygonal FET drain region and is surrounded by a ring or polygonal gate electrode and a source electrode. The entire FET area is covered with an insulating layer and a metal layer. This configuration provides uniform current emission characteristics for each emitter chip and achieves uniform electron emission in all directions. The application of this FET to flat display devices achieves high image quality, low power consumption and low manufacturing cost.

Description

Field emission device, its manufacturing method and display device using same Field of the invention {Field emission device, its manufacturing method and display device using the same}

The most well-known basic construction of a conventional field emission device (FED) is 1976. Applied Physics Journal vol. 47, p. 5238. It has a conical spine structure as disclosed in Spint et al. However, such a spin configuration FED has a problem in stable emission current. In particular, when used in flat panel displays as proposed in Japanese Patent Application Laid-Open No. 6-14263 due to unstable emission currents, unstable currents are a major problem because they directly affect display quality.

Japanese Patent Laid-Open No. 7-118259 discloses a FED having stable emission by using a negative feedback effect by connecting a high resistance resistor in series to an emitter emitting electrons. However, using a high resistance resistor in the range of 10 to 100 M ohms connected in series to the emitter reduces the response of the FED and consumes significant power. In addition to inserting high resistance resistors, to solve this problem, for example, by integrating more than 1000 emitters to form an emitter array for one FED, the emitter instability is averaged by solving the emitter instability . However, increasing the number of emitters increases complexity and increases the cost of manufacturing FEDs.

In order to solve these problems, Japanese Patent Laid-Open No. 9-259744 discloses a method of directly connecting an active element such as a transistor to an emitter of a FED to control a current flowing in the emitter. This can stabilize the current with low power consumption. Moreover, it eliminates the need to form a large number of emitters. However, this conventional technique uses single crystal silicon as the substrate, and therefore, it is impossible to manufacture a large flat panel display element, and the cost also increases.

Recently, Japanese Patent Laid-Open No. 9-129123; H. Kamo et al., Applied Physics Letters, vol. 73, p. 1301, 1998; Why. H. Song et al. SID 98 DIGEST, p. 189, 1998 discloses the use of glass substrates instead of single crystals to enable large size and reduce cost for application in flat panel display devices. In this structure, the emitter, the field effect transistor (FET), and its thin film transistor (TFT) are formed on the glass substrate using amorphous silicon and polycrystalline silicon.

10A and 10B show the configuration of a conventional FED including an emitter array 7 and a TFT 23. 10A is a perspective view illustrating an entire FED corresponding to one pixel. 10 (b) is an enlarged cross-sectional view of one emitter and TFT in the emitter array 7.

As shown in Fig. 10A, more than 1000 emitters 10 are formed in the emitter array 7 of the FED for each pixel controlled by one TFT 23. The current coming from the emitter array 7 is controlled by the TFT 23 connected to the edge of the emitter array 7 via the cathode electrode.

As shown in Fig. 10 (b), the FED includes the above-described TFT 23 and an emitter portion connected through the drain electrode 19. Figs. The TFT 23 includes a chromium source electrode 9, an n + amorphous silicon contact layer and a channel i amorphous silicon layer 20, a silicon dioxide gate insulating layer 3, and a chromium gate electrode 4 on a glass substrate. . The emitter portion includes the TFT 23, the chromium drain metal 19, the amorphous silicon emitter 10, the silicon dioxide insulating layer 24, and the niobium extraction electrode 11 described above.

11 illustrates a conventional FED manufacturing method. As shown in Fig. 11A, each material is sequentially formed in layers. Subsequently, the portion to be the TFT 7 is covered with the photoresist 21. Areas other than the TFTs are removed by etching to expose the lower drain electrode 19 (Fig. 11 (b)). Next, the amorphous silicon layer 20 for forming the emitter is formed again (Fig. 11 (c)). An emitter shape is made (Fig. 11 (d)), an insulating layer 24 and an extraction electrode 11 are formed thereon, and an emitter hole is made to expose the emitter tip (Fig. 11 (e)). .

In the description, a portion such as a cone that emits cold electrons is referred to as an emitter below, and an element made by connecting such an emitter to a transistor is referred to as an FED as a whole.

The conventional FED has the following problems.

When a thin amorphous or polycrystalline silicon layer with a thickness of 200 nm or less is formed on a glass substrate, it is not possible to obtain a silicon layer having high electron mobility and good crystallinity. If the channel layer of the TFT or TFT is formed on this silicon layer, no TFT or FET having uniform and good characteristics is obtained.

Excimer lasers are also used to anneal amorphous silicon on glass substrates for crystallization. This complicates the process. Laser annealing is also disadvantageous for mass production and increases manufacturing costs.

In addition, the prior art requires the formation of thin amorphous silicon layers, insulating layers, and metal layers for manufacturing TFTs or FETs. These layers are etched on the emitter and the process is complicated because the thick amorphous silicon layer for forming the emitter is formed again. Before forming the amorphous silicon layer again to make the emitter, its formation surface is exposed to air. This may contaminate the growth surface and reduce the crystallinity of the amorphous silicon layer.

Also, as shown in Fig. 10A, many emitter arrays are controlled by one FET connected to one end of the array area. This results in a different distance between the FET drain and each emitter chip, causing a difference in resistance between the FET and the emitter. As a result, the emission characteristics of each emitter are different.

Moreover, the gate and source of the FET are symmetrically disposed with respect to the emitter array. This causes asymmetry in the space potential distribution between the emitter array and the phosphor substrate anode substrate when the FED is used in a flat panel display device. As a result, the electron moving direction becomes anisotropic.

In addition, since the gate metal of the FET is covered only by the insulating layer, any small amount of external noise may adversely affect the gate metal and may cause the FET to operate incorrectly, thereby greatly changing the emitter emission current.

As mentioned above, the prior art FED has many problems, and the use of such a FET in a flat panel display device makes it impossible to make high quality which depends on uniformity and high brightness. In addition, power consumption and costs are increased.

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to the field of field emission devices (FEDs) employed in devices employing electron beams and methods of manufacturing the same, including devices including flat display devices, sensors, high frequency oscillators, ultrafast devices, electron microscopes, and electron beam exposure devices. . In particular, the present invention provides an FED having an emitter that integrates field effect transistors (FETs) to stabilize emission current: FED having high current density and satisfactory power efficiency; And it relates to a production method thereof.

1 is a cross-sectional view of an FED according to a first embodiment of the present invention.

2 is a cross-sectional view of a conical FED according to a first embodiment of the present invention.

3 is a cross-sectional view showing a manufacturing process of the FED according to the first embodiment of the present invention.

4 is a cross-sectional view of an FED according to a second embodiment of the present invention.

5 is a cross-sectional view of an FED according to a third embodiment of the present invention.

6 is a cross-sectional view of an FED according to a fourth embodiment of the present invention.

7 (a) is a plan view of an FED according to a fifth embodiment of the present invention.

7B is a cross-sectional view of the FED according to the fifth embodiment of the present invention.

8 is a cross-sectional view of an FED having a converging electrode according to a fifth embodiment of the present invention.

9 is a cross-sectional view of an FED according to a sixth embodiment of the present invention.

10 (a) is a perspective view of a conventional FED.

Fig. 10 (b) is an enlarged cross-sectional view of the part related to the elements of the conventional FED.

11 is a cross-sectional view showing a conventional method for manufacturing a FED.

FED of the present invention,

Amorphous substrates;

Impurity diffusion barrier layer;

A field effect transistor (FET) formed on a surface of a semiconductor layer made of polycrystalline silicon formed on amorphous silicon or an impurity diffusion barrier layer;

One or more emitters having sharp tips made by etching a semiconductor layer on the drain region of the FET; And

And an extraction electrode for extracting electrons by applying a high field to the emitter.

The semiconductor layer is formed using a chemical vapor deposition method (CVD method) that utilizes a catalytic effect caused by contact of a semiconductor material gas with a high melting point metal heated to a high temperature.

Emitters or arrays comprising one or more emitters are formed in a circular or polygonal FET drain region. The emitter array is surrounded by a ring or polygonal gate electrode and a source electrode. The entire FET is then covered with an insulating layer and a metal layer.

This configuration provides the following effects.

Polycrystalline layers thicker than 500 nm can be directly formed at a high rate of 0.2 nm / s or more, which is relatively high speed. This eliminates the need for a polycrystallization process using laser annealing after the formation of the polycrystalline silicon layer. Moreover, the thick layer improves crystallinity near the surface, achieves high mobility and makes it possible to manufacture FETs with uniform and good properties.

By growing the semiconductor layer in a single step, the formation of FETs and emitters simplifies the process. Since there is no second step to obtain a thick semiconductor layer, exposure to the growth surface in the air can be avoided, thus preventing the possibility of surface contamination.

The formation of emitter arrays in the circular or polygonal FET drain region equalizes the distance between the FET drain and each emitter, so that the resistance can be averaged at each emitter and thus the emission characteristics of each emitter chip can be made uniform. can do. Furthermore, the spatial potential distribution between the emitter array and the anode electrode is symmetrical in the substrate, allowing electrons to be emitted uniformly in all directions. Since the ratio (gate width / gate length) of the FET also becomes large, it is possible to manufacture a high current level FET even if the mobility of the FET is low.

To shield the noise, a metal layer is installed on the FET. This is adversely affected by weak external noise, which significantly changes the emitter's emission current, preventing the FET's behavior from changing.

The above characteristics of the FED applied to the flat display device make it possible to provide high picture quality, including uniformity and high brightness, low power consumption, and low cost.

First embodiment

A first embodiment of the present invention is described below with reference to Figs.

As shown in FIG. 1, the FED of the present invention includes a substrate 1, a semiconductor layer 2, an FED gate insulating layer 3, a FET gate metal 4, a FET source region 5, and a FET drain region ( 6), and emitter array 7.

In the first embodiment, the emitter array 7 is formed by etching the semiconductor layer 2 over the FET drain region after forming the FET. That is, the first embodiment makes it possible to form both the FET and the emitter by the single growth of the semiconductor layer 2. Exposing the surface to air becomes a problem for the growth of the semiconductor layer 2 in two steps. By preventing this, the process can be simplified and the decrease in crystallinity is prevented.

FIG. 2 shows a cross-sectional view of the FED after the conical emitter 10 and extraction electrode 11 have been added to the emitter portion shown in FIG. 1. In addition to FIG. 1, an impurity diffusion barrier layer 8, an FET source electrode 9, and an emitter array 7 are insulated from one conical emitter 10, an extraction electrode 11, and an extraction electrode 12. Layer, and the FET passivation layer 13 is shown.

Because the conical emitter lies in the center of the cylindrical hole, the electric field is uniformly concentrated at the tip of the emitter, which dissipates cold electrons at a uniform and relatively low voltage. Therefore, satisfactory cold electron emission characteristics can be achieved by using a conical emitter and an extraction electrode in the FET configuration shown in FIG.

The substrate 1 is a single crystal or polycrystalline substrate made of a semiconductor such as silicon. In particular, because amorphous glass substrates are used, the size can be increased, the cost can be reduced when applied to the display element, and the screen size can be increased.

In general, satisfactory crystallinity cannot be achieved with a thin layer thinner than 200 nm in the initial layer formation step because the lattice constant of the crystal is different when the polycrystalline semiconductor layer 2 is formed on the glass substrate 1. Crystallinity gradually improves after the layer thickness exceeds 500 nm. Therefore, since the FET is formed on the crystal surface of the layer of 500 nm or more, the semiconductor layer 2 having an electron mobility exceeding 10 cm ² / V · s is easily formed. One method of forming the semiconductor layer 2 is a CVD method utilizing the catalytic effect caused by contacting a semiconductor material gas with a high melting point metal heated to a high temperature. If micro grain silicon or polycrystalline silicon is grown using this CVD method, a semiconductor layer 2 having an electron mobility of 10 cm ² / V · s or more is obtained, which is suitable for controlling the emission current from the emitter.

The impurity diffusion preventing layer 8 is provided to prevent any adverse influence caused by elements in the substrate that thermally diffuse into the semiconductor layer as impurities when the substrate and the semiconductor layer on top have different compositions. In particular, the closely packed silicon dioxide and silicon nitride layers used in the general process can effectively suppress any diffusion of impurities and can also be made easily.

As the semiconductor 2, group 4 semiconductors such as silicon and group 3-4 semiconductors such as gallium and arsenic can be used. In particular, semiconductors having a wide bandgap, such as diamond, boron nitride, and gallium nitride, have low electron affinity. These types emit electrons into the vacuum at low voltages and are therefore suitable for use as emitters. There has been extensive research on the use of silicon in integrated circuits, and silicon also has a stable oxide layer. Thus, the use of silicon has the advantage of controlling the emitter using integrated circuits. Since the semiconductors described above can also be used as emitters, emitters combined with FETs are easily manufactured.

In manufacturing an n-channel FET capable of responding quickly and allowing a large current to flow, a p-type semiconductor can be used as the material for the semiconductor layer 2. The p-type semiconductor can be made by doping boron or aluminum to a Group 4 semiconductor or by doping magnesium and zinc to a Group 3-4 semiconductor. On the other hand, in manufacturing an n-channel FET, an n-type semiconductor can be used. An n-type semiconductor can be made by doping phosphorus or arsenic into a Group 4 semiconductor or by doping silicon or sulfur into a Group 3-4 semiconductor. MOS circuits are suitable for integrating electronic circuits to control the operation of the emitter. In this case, n and p channels are required.

The semiconductor layer 2 may have an amorphous, polycrystalline or single crystal structure. When using a single crystal for the semiconductor layer 2, the material for the substrate 1 can be limited. In a large glass substrate, it may be necessary to use an amorphous or polycrystalline semiconductor layer 2. In this case, hydrotreating is effective in order to improve crystallinity by forming a terminal with a dangling bond in the semiconductor.

The FET gate insulating layer 3 may be made of silicon dioxide, silicon nitride, or a composite thereof having high electrical insulating capability and very dense configuration. In order to reduce the distortion of the insulating layer 3, single layers of these materials may be combined to form a plurality of layers. If the CVD method is used in manufacturing the insulating layer 3, the layers from the semiconductor layer to the silicon nitride layer can be formed continuously without causing any damage to the semiconductor layer. The insulating layer 3 can also be used as an etching mask for processing the emitter or as a mask for doping ions in the drain region of the FET.

In order to process the shape of the emitter, the above-described insulating layer 3 may be used as a mask. The insulating layer 3 can also be used as a mask for doping ions in the FET drain region.

In the metal wiring including the FET gate metal 4, the FET source electrode 9, and the extraction electrode 11, aluminum which can be used to form an inexpensive, low electrical resistance and high quality anodization layer can be used. . Alternatively, inexpensive and low electrical resistance copper; Titanium, which improves adhesion to glass substrates, or tantalum, which can form a high quality anodization layer, may be used. Other elements, such as neodymium, may be added to aluminum, for example, to suppress hillock and to produce alloys containing greater than 95 percent by weight of the main component.

When forming a metal layer on a glass substrate, a thin titanium layer of 100 nm or less is first formed, and then an aluminum layer is formed to improve adhesion and electrical conductivity. Thus, these metal elements may be used as a single layer or may be combined to form a plurality of layers to utilize the best properties of each metal.

3 (a) to 3 (f) show cross-sectional views of an example of the manufacturing process of the FED in the first embodiment.

As shown in Fig. 3A, the impurity diffusion barrier layer 8, the semiconductor layer 2, and the FET gate insulating layer 3 are successively formed using a plasma-enabled CVD method, followed by a FET gate by vacuum deposition. The metal 4 is deposited. Next, as shown in Fig. 3B, the gate metal 4 and the gate insulating layer 3 are patterned by etching such as reactive ion etching to determine the positions of the FETs and the emitters.

Subsequently, as shown in Fig. 3C, a conical emitter is formed using the gate insulating layer 3 as a mask for etching such as reactive ion etching.

Next, as shown in Fig. 3D, the FET source region 5 and the FET drain region 6 are formed using a doping technique such as ion implantation. At the same time the emitter is doped.

As shown in Fig. 3 (e), the insulating layer 12 under the extraction electrode 11 is formed by using a plasma-enabled CVD method, followed by contact holes being etched in the source region 5 and FET source. The electrode 9 is usually formed using sputtering.

As shown in Fig. 3 (f), the FET passivation insulating layer 13 and the extraction electrode 11 are continuously formed using a plasma-using CVD method.

Finally, as shown in Fig. 3 (g), the insulating layer under the extraction electrode 11 and the extraction electrode 12 is etched to expose the conical emitter.

The insulating layer 13 is allowed to etch slower than the insulating layer 12. For example, silicon dioxide may be used for the insulating layer 12 and silicon nitride may be used for the insulating layer 13, or the insulating layer 13 is made thicker than the insulating layer 12. This is because if the insulating layer 12 and the insulating layer 13 are made of the same material and the same thickness, the FET itself is applied to the etching agent while the extraction electrode 11 and the insulating layer 12 are etched to expose the emitter. This is because it can be eliminated by dissolving.

The semiconductor layer 2 or the gate insulating layer 3 shown in Fig. 3A is a material gas for CVD utilizing the catalytic effect of a high melting point metal such as tungsten, tantalum, and molybdenum (so-called hot wire method). Preferably, at least one of monosilane, disilane, hydrogen, nitrogen, ammonia, methane, ethane, propane, butane, trimethyl gallium, triethyl gallium, trimethyl aluminum, acine, phosphine, and diborane Is formed using. Compared with conventional plasma using CVD using RF discharge, it has a polyelectron mobility of 10 cm ² / V · s or more and a thickness of 500 nm or more at a relatively high speed of about 0.2 to 0.5 nm / s even at a relatively low temperature of 500 ° C. or less. It is possible to form a silicon layer. As a result, no post annealing process for polycrystallization is necessary, such as using excimer laser annealing.

Furthermore, as shown in Fig. 3C, the process is simplified by using a part of the gate insulating layer 3 as an etching mask for etching the conical emitter.

As shown in Fig. 3D, the FET source region 5, the FET drain region 6, the conical emitter 10, the FET drain, and the inter-emitter electrical resistance are adjustable using ion implantation and thus The process is simplified. If ions are implanted between the FET drain and the emitter, except for a portion of the FET gate insulating layer 3, this residual portion will be undoped or less doped, thus reducing the electrical resistance of the entire channel between the FET drain and emitter. It can be finely adjusted.

The ion doping amount is also adjustable in accordance with the thickness of the FET gate insulating layer and thus the resistance is also adjustable. Since the resistance between each emitter and drain can be adjusted, the electron emission from each emitter can be made uniform. Also, if a high electrical resistance is provided between the emitter and the drain, the change of electron emission from the emitter over time can be stabilized by the negative feedback of the resistance.

In the process shown in Fig. 3G, the crystallinity of the semiconductor layer 2 can be improved by heat treatment, so that the characteristics and planar uniformity of the FET can be improved. In particular, in the case of amorphous silicon and polycrystalline silicon, the heat treatment may be implemented with a single nitrogen or an inert gas if a silicon nitride passivation layer containing a large amount of hydrogen is formed. In general, however, the FET characteristics are effectively improved by heat treatment in an atmosphere containing hydrogen or water vapor.

Second embodiment

A second embodiment of the present invention will be described with reference to FIG. The surface of the emitter 10 is covered with a carbon protective layer 14 such as diamond or carbon such as diamond or diamond which is chemically inert and does not impair electron emission characteristics, thereby making the surface of the emitter chemically inert. As a result, it can be maintained even at a relatively low vacuum without being damaged by the impact or adsorption of the gas remaining in the vacuum system. The protective layer 14 is typically formed after the step shown in FIG. 3 (f) in a region other than the electrode pad, using microwave excited plasma-assisted CVD.

Third embodiment

A third embodiment of the present invention will be described with reference to FIG.

As shown in Fig. 5, the FED of this embodiment includes a high resistance region 15 between the gate and the source and between the gate and the drain of the FET. The high resistance region 15 can be made by reducing the doping amount between the gate and the source and between the gate and the drain. With the structure of the third embodiment, it is possible to prevent drift of the emission current due to the impact ion effect generated by the high electric field around the drain electrode, thereby reducing the off current and impact ion effect.

Fourth embodiment

A fourth embodiment of the present invention is described with reference to FIG.

When the glass substrate 1 or the impurity diffusion barrier 8 is amorphous, or when they have a lattice constant different from that of the semiconductor layer 2, the semiconductor formed on the glass substrate 1 or the impurity diffusion barrier 8 Crystallization of the layer is difficult. Even if the semiconductor layer is crystallized, distortion or defect density may increase. In order to reduce such distortion or defect density, the FED of the fifth embodiment inserts an amorphous layer 16 of 100 nm or less between the substrate and the semiconductor layer or between the impurity diffusion preventing layer and the semiconductor layer.

For example, if polycrystalline silicon is formed on a glass substrate, a 100 nm thick strained super lattice silicon and germanium or amorphous silicon layer is deposited using a plasma-based CVD method to prevent propagation of defective crystal growth at the interface. It can also be inserted. Distortion caused by the difference in lattice constant or the difference in thermal expansion coefficient can be further reduced to promote crystallization of the semiconductor layer 2. After the amorphous silicon layer is formed, the polycrystalline silicon layer may be formed using the same process at a lower temperature than in the case of polycrystalline silicon. This type of amorphous silicon layer is particularly effective for the uniform crystallization of the polycrystalline silicon layer in the entire substrate in later processes.

Fifth Embodiment

A fifth embodiment of the present invention is described below with reference to FIGS. 7 and 8.

In this example embodiment, the manufacturing process of the FED is the same as that illustrated in FIG. 3. The difference is that the ring gate structure is adopted for the FET as shown in Fig. 7, and the emitter is formed in the circular drain region at the center of the FET.

The emitter 10 is arranged concentrically or rotationally symmetrically in the circular drain region 6 so that the distance between the FET gate and each emitter is constant. The resistance is the same for each emitter, so that the emission current from each emitter is the same, and leakage current from the FET can be prevented.

Moreover, the electric fields generated by the extraction electrode 11, the gate metal 4, and the source electrode 3 have the same effect on the electrons emitted from the emitter, so that the electrons are uniformly emitted in all directions. Moreover, the large gate width / gate length (W / L) ratio can be ensured in the FET due to the ring gate structure, so that a high current can be produced even if the electron mobility of the semiconductor layer 2 is low. .

If a FET having the same current level as in the prior art shown in Fig. 10 is made, the gate area (W x L) can be made larger than before, so that the variation in the W / L ratio in the substrate caused by the variation in the manufacturing size of the FET can be achieved. Can be reduced.

However, for n-channel FETs, the gate voltage is generally controlled by a positive electric field. This leads to electrons emitted from the emitter, which slightly diffuse the electrons into the substrate. Accordingly, in order to adjust the diffusion angle of the emission electrons, as shown in FIG. 8, the convergent electrode 17 in the negative electric field is formed on the ring FET. The extraction electrode 11 shown in FIG. 3F may be patterned to act as the converging electrode 17.

Sixth embodiment

A sixth embodiment of the present invention will be described with reference to FIG.

In the sixth embodiment, the entire FET is covered with a metal layer 18 to make noise shielding for the FET. This eliminates large fluctuations in the emission current from the emitter formed in the FET drain due to small external noise generated by inductive noise in the gate metal. The extraction electrode 11 shown in FIG. 3F can be patterned to act as this metal layer 18. The metal layer 18 may be kept at ground potential to achieve sufficient noise shielding effect.

As described above, the FED of the present invention is an emitter array with FETs having uniform and satisfactory properties using a simple process of forming a semiconductor layer on a large glass substrate in a single step, without the need for a post annealing process. To be prepared.

In addition, the use of metal layer shielded FETs with ring gates provides strong resistance to external noise, enables uniform control of relatively large current emission characteristics, and emitter characteristics with uniform electron emission in all directions are obtained. . Therefore, factors important for high image quality, including uniformity and high brightness, low power consumption, and low cost, can be realized when applying the FET of the present invention to a flat display device.

Claims (40)

In the field emission device, A semiconductor layer formed on the substrate; A field effect transistor comprising an insulating layer and an electrode; And at least one emitter formed in one of a drain region of the field effect transistor and a portion of the semiconductor layer in contact with the drain region. The field emission device of claim 1, wherein the emitter has a conical tip. 2. The field emission device of claim 1, wherein an extraction electrode for emitting electrons is formed, and the extraction electrode is formed so as not to contact the emitter and the drain region. The field emission device of claim 1, wherein the substrate is an amorphous substrate. The field emission device according to claim 1, further comprising an impurity diffusion preventing layer between the substrate and the semiconductor layer. 6. The field emission device according to claim 5, wherein the impurity diffusion preventing layer is made of one of a single layer of silicon dioxide and silicon nitride, a plurality of layers in combination thereof, and a composite layer thereof. The field emission device as claimed in claim 1, wherein the semiconductor layer is made of one of a composite semiconductor mainly composed of group IV elements and group IV elements in a periodic table. The field emission device of claim 1, wherein the semiconductor layer is made of a composite semiconductor in which group III elements and group V elements are combined in a periodic table. The field emission device of claim 1, wherein the semiconductor layer is one of a doped p-type semiconductor and an n-type semiconductor. The semiconductor device of claim 1, wherein the semiconductor layer comprises: a p-type semiconductor doped with one of boron, aluminum, magnesium, and zinc; And an n-type semiconductor doped with one of phosphorus, arsenic, antimony, and sulfur. The field emission device of claim 1, wherein the semiconductor layer has one of amorphous, hydrotreated amorphous, polycrystalline, and hydrotreated polycrystalline. The field emission device according to claim 1, wherein the insulation layer of the field effect transistor is made of one of a single layer of silicon dioxide and silicon nitride, a plurality of layers in combination thereof, and a composite layer thereof. The method of claim 1, wherein the metal layer and all metal wirings of the field effect transistor are made of one of aluminum, copper, titanium, and tantalum containing at least 95% by weight, and a combination of a plurality of layers thereof. A field emission device characterized by the above-mentioned. 4. The field emission device according to claim 3, wherein an insulating layer having an etching rate lower than that of the insulating layer under the extraction electrode is used as a passivation insulating layer of the field effect transistor. 15. The field emission device according to claim 14, wherein silicon dioxide is used for the insulating layer under the extraction electrode and silicon nitride is used for the passivation layer of the field effect transistor. 4. The field emission device of claim 3, wherein the gate insulating layer of the field effect transistor is thicker than the insulating layer under the extraction electrode. 2. The field emission device as claimed in claim 1, wherein the surface of the emitter is coated with a chemically inert protective layer that does not degrade electron emission characteristics. 18. The field emission device as claimed in claim 17, wherein the protective layer is made of carbon. 2. The field emission device as claimed in claim 1, wherein a layer having a higher electrical resistance than the source and the drain is inserted between i) the source and the drain and ii) the drain and the gate of the field effect transistor. The field emission device of claim 1, wherein the semiconductor layer is one of a polycrystalline layer and a single crystal layer including one of a strain super lattice layer and an amorphous layer not thicker than 100 nm. In the field emission device, An emitter array formed in one of circular and polygonal drain regions of the field effect transistor; One of a ring and polygonal ring gate electrode around the drain region; And And a source electrode around the gate electrode. 22. The field emission device as claimed in claim 21, wherein the emitter is disposed in the drain region at one of the concentric and rotationally symmetric positions. 22. The field emission device as claimed in claim 21, wherein the emitter array has one of a ring and a polygonal ring converging electrode, wherein the converging electrode surrounds the emitter array in rotational symmetry. 24. The field emission device as claimed in claim 23, wherein the converging electrode also functions as an extraction electrode for electron emission. In the field emission device, Emitters; And A field effect transistor, And the upper portion of the field effect transistor is covered with an insulating layer and a metal layer. 27. The field emission device as claimed in claim 25, wherein the metal layer also functions as an extraction electrode for electron emission. 27. The field emission device as claimed in claim 25, wherein the metal layer is held at ground potential. In the field emission device manufacturing method, Forming a semiconductor layer on the substrate; Forming a field effect transistor by forming an insulating layer and an electrode on the semiconductor layer; Forming at least one emitter on the semiconductor layer in one of the drain region of the field effect transistor and the semiconductor layer in contact with the drain region. 29. The method of claim 28, wherein the emitter and the semiconductor layer of the field effect transistor are made of the same material and formed simultaneously. 29. The method of claim 28, further comprising forming an impurity diffusion barrier layer between the substrate and the semiconductor layer. 29. The electric field of claim 28, wherein one of the semiconductor layer and the insulating layer is formed using a chemical vapor deposition method utilizing a catalytic effect caused by the contact of a substance gas with a metal of high melting point heated to a high temperature. Method of manufacturing the emitting device. 32. The method of claim 31, wherein the mass gas is monosilane, disilane, hydrogen, nitrogen, ammonia, methane, ethane, propane, butane, trimethyl gallium, triethyl gallium, trimethyl aluminum, acine, phosphine, and dibo The field emission device manufacturing method characterized in that at least one of the columns. 32. The method of claim 31, wherein the high melting point metal is at least one of tungsten, tantalum, and molybdenum. 29. The method of claim 28, wherein the insulating layer is used as an etching mask to process the emitter shape. 29. The method of claim 28, wherein the electrical resistance of the drain region in which the emitter is formed is adjusted by ion implantation. 36. The method of claim 35, wherein ions are implanted into the drain region while the insulating layer remains. 29. The method of claim 28, wherein the semiconductor layer is heat-treated at a temperature not higher than 500 ° C. in one of an atmosphere containing nitrogen and an inert gas atmosphere and one containing hydrogen and water vapor. In the field emission device manufacturing method, Forming three layers of a semiconductor layer, a gate insulating layer, and a gate metal of the FET on one of the substrate and the impurity diffusion barrier layer formed on the substrate; Forming a FET gate and a gate electrode by patterning the gate metal and gate insulating layer; Forming an emitter by etching a portion of the drain region of the FET; Doping a surface of one of said FET source and drain and an emitter; Forming a source electrode on the FET through an insulating layer; Forming a passivation layer on the FET; Forming an extraction electrode on the emitter through one of an insulating layer and a space; And And heat-treating one of the FET and the emitter region. In the field emission display device having an electron-emitting device, A semiconductor layer formed on the substrate; A field effect transistor comprising an insulating layer and an electrode; And at least one emitter formed on one of the portion of the semiconductor layer in contact with the field effect transistor and the drain region. In the field emission display device having an electron-emitting device, An emitter array formed in one of circular and polygonal drain regions of the field effect transistor; One of a ring and a polygonal ring gate electrode around the drain electrode; And And a source electrode around the gate electrode.