JPH11167857A - Cold electron emitting element and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field emission type electron emitting element capable of suppressing the electric current fluctuation to the minimum and at the same time suppressing local large current flow without increasing the operational voltage and formable on a glass substrate easy to lower the cost and to enlarge the surface area of the element. SOLUTION: This field emission type cold electron emitting element is produced by sequentially laminating a first conductive layer 2 on an insulating substrate 1, an insulating layer 5, and a gate electrode 7, forming an aperture part B in the insulating layer 5 and the gate electrode 7, and forming an emitter 8 in the aperture part B while keeping the emitter separated from the gate electrode 7. In this case, the emitter 8 is made of a non-single crystal silicon and a second conductive layer 3 is formed on the insulating substrate 1 while being kept from a contact with the first conductive layer 2. Further, a semiconductor thin layer 4 of a non-single crystal silicon is formed on the insulating substrate 1 at least between the first conductive layer 2 and the second conductive layer 3 and a third conductive layer 6 is formed on or under the semiconductive thin layer 4 through a gate insulating layer 5' while being kept from a contact with the first conductive layer 2 and the second conductive layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a field emission type cold electron emitting device that emits cold electrons by a strong electric field and a method of manufacturing the same. More specifically, as an electron source or electron gun such as an optical printer, an electron microscope, an electron beam exposure device, or as a micro illumination source of an illumination lamp,
Array-like FEA (Field E
The present invention relates to a cold electron emission element useful as an electron source of a mitter array and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube has been widely used as an electronic display device. However, the cathode ray tube consumes a large amount of energy to emit thermoelectrons from a cathode of an electron gun, and is structurally large. There were problems such as requiring a volume.

[0003] For this reason, there has been a demand for a flat display in which cold electrons can be used instead of thermoelectrons, thereby reducing the energy consumption as a whole and further reducing the size of the device itself. There is also a strong demand for such a flat display to realize high-speed response and high resolution.

As a structure of such a flat display utilizing cold electrons, a structure in which minute electron-emitting devices are arranged in an array in a high-vacuum flat plate cell is considered promising. And as an electron-emitting device used for that,
A field emission type cold electron-emitting device utilizing the field emission phenomenon has attracted attention. This field emission type cold electron emission element
When the intensity of the electric field applied to a substance is increased, the width of the energy barrier on the surface of the substance is gradually reduced in accordance with the intensity. When the electric field strength becomes a strong electric field of 10 ⁷ V / cm or more, electrons in the substance are caused by a tunnel effect. They can break through the energy barrier and take advantage of the phenomenon that electrons are emitted from matter. In this case, a member that emits electrons (emitter) because the electric field follows Poisson's equation
When a portion where an electric field is concentrated is formed, cold electrons can be efficiently emitted with a relatively low extraction voltage.

As a general example of such a field emission type cold electron emitting device, a conical cold electron emitting device having a sharp tip as shown in FIG. 7 can be exemplified. In this element, a conductive layer 72, an insulating layer 73, and a gate electrode 74 are sequentially stacked on an insulating substrate 71, and an opening B reaching the conductive layer 72 is formed in the insulating layer 73 and the gate electrode 74. Have been. And the opening B
A conical emitter 75 having a point-like projection is formed on the conductive layer 72 inside so as not to contact the gate electrode 74.

Among such conical emitters, Spindt-type emitters are widely known.

An example of manufacturing a cold electron-emitting device having a Spindt-type emitter will be described with reference to FIGS.

First, as shown in FIG. 8A, an insulating layer 83 and a gate electrode 84 are sequentially formed on an insulating substrate 81 on which a conductive layer 82 is formed in advance by a sputtering method or a vacuum evaporation method. . Subsequently, the insulating layer 8 is formed using photolithography and reactive ion etching (RIE).
3 and a part of the gate electrode 84 are etched such that a circular hole (gate hole) is opened until the conductive layer 82 is exposed.

Next, as shown in FIG. 8B, a lift-off material 85 is formed only on the upper and side surfaces of the gate electrode 84 by oblique evaporation. The material of the lift-off material 85 is A
1, MgO and the like are often used.

Subsequently, as shown in FIG. 8C, a metal material for the emitter 86 is deposited on the conductive layer 82 by a normal anisotropic deposition from a vertical direction. At this time,
As the evaporation proceeds, the conical emitter 86 is formed on the conductive layer 82 in a self-aligned manner at the same time as the opening diameter of the gate hole is reduced. The vapor deposition is performed until the gate hole is finally closed. As the material of the emitter, Mo, Ni, or the like can be used.

Finally, as shown in FIG. 8D, the lift-off material 85 is peeled off by etching, and the gate electrode 84 is patterned as necessary. Thus, a cold electron-emitting device having the Spindt-type emitter 86 is obtained.

The cold electron-emitting device having such a Spindt-type emitter has the advantage that a conical emitter can be easily formed in a self-aligned manner by anisotropic vapor deposition, and that the emitter material can be selected over a wide range. doing.

When a cold electron-emitting device utilizing fine processing technology, such as a Spindt-type emitter, is applied to a flat display or the like in particular, the small fluctuation of the emission current from the emitter leads to high quality image quality. Indispensable to get.

The fluctuation of the emission current can be reduced to some extent by integrating the emitter.
This is because the effect of variations in emission characteristics of individual emitters is reduced by integration. However, in this method, the emission current from each emitter is merely averaged, so that it is impossible to suppress an abnormally large emission current that appears locally.

As means for reducing such a variation in emission current, US Pat. No. 3,789,471 discloses a technique in which a spint type emitter is provided with a resistive layer between a conductive layer and the emitter.

An example of the configuration of a cold electron emission device having such a resistance layer will be described with reference to FIG.

A conductive layer 92 and a resistance layer 9 are formed on an insulating substrate 91.
3, an insulating layer 94 and a gate electrode 95 are sequentially laminated, and the insulating layer 94 and the gate electrode 95
3 is formed. A conical emitter 96 is formed on the resistance layer 93 in the opening B so as not to contact the gate electrode 95.

In this case, the resistance layer 93 is electrically inserted between the conductive layer 92 and the emitter 96 in series. The resistance layer 93 has an effect of equalizing the current between the elements, and furthermore, a large current that leads to element destruction can be reduced, and the fluctuation of the emission current can be reduced in proportion to the resistance value of the resistance layer 93. It becomes possible. The specific resistance of the resistance layer 93 is appropriately set to 10 ² to 10 ⁶ Ω · cm.

On the other hand, a silicon emitter to which a semiconductor integrated circuit manufacturing technology is applied is also widely known (Tech. Dig. IV).
MC., P26 (1991)).

An example of manufacturing a cold electron-emitting device having a silicon emitter will be described with reference to FIGS.

First, as shown in FIG. 10A, a single crystal silicon substrate 101 is thermally oxidized to form a silicon oxide layer on the surface, and the silicon oxide layer is patterned into a circular shape by using a photolithography method. Thus, a circular silicon oxide layer 102 for an etching mask is formed. This silicon oxide layer 102 also functions as a lift-off material as described later. Note that the silicon oxide layer 102
Is approximately equivalent to the gate diameter.

Next, as shown in FIG. 10B, the silicon substrate 101 is etched by a reactive ion etching (RIE) under a condition of a high side etch rate.
An emitter 103 is formed.

Subsequently, as shown in FIG. 10C, a silicon oxide layer 104 for sharpening the tip of the emitter is formed on the surfaces of the silicon substrate 101 and the emitter 103 by thermal oxidation. Due to the stress generated when the silicon oxide layer 104 is formed, the emitter 103 inside the silicon oxide layer 104 is formed.
Is easily sharpened.

Then, as shown in FIG. 10D, an insulating layer 105 and a gate electrode 106 are laminated by an anisotropic vapor deposition method.

Finally, as shown in FIG. 10E, the silicon oxide layer 102 for an etching mask, which also functions as a lift-off material, is lifted off by etching.
The silicon oxide layer 104 on the surface of the emitter 103 is removed by etching. Then, the gate electrode 106 is patterned as necessary. Thereby, a cold electron emission device having a silicon emitter is obtained.

More recently, in silicon emitters,
It has been shown that advanced current control is possible using the properties of silicon as a semiconductor (Jpn.J. Appl.Phys.v.
ol. 35 p6637 (1996)). A silicon emitter equipped with such a current control function is called a MOSFET structure emitter. The configuration of the cold electron-emitting device having the MOSFET structure emitter will be described with reference to FIG.

On the same plane of the p-type silicon substrate 111,
An emitter wiring layer 114 is provided via a conical emitter 112 made of n-type silicon and an n-type silicon layer 113, and a gate electrode 116 is provided between the emitter 112 and the emitter wiring layer 114 via an insulating layer 115. I have.
That is, the MOSFET (metal-oxide-sem
The emitter field layer 114 of the cold electron emission element has a structure in which an emitter field-effect-transistor) structure is built in the cold electron emission element.
2 is a drain, gate electrode 116 is a gate, insulating layer 11
5 each function as a gate insulating layer.

A manufacturing example of a cold electron emission device having a MOSFET structure emitter will be described with reference to FIGS.

First, as shown in FIG. 12A, a single crystal p-type silicon substrate 121 is thermally oxidized to form a silicon oxide layer on the surface, and the silicon oxide layer is formed into a circular shape by using photolithography. To form a silicon oxide layer 122 for a circular etching mask. This silicon oxide layer 122 also functions as a lift-off material as described later. Note that the diameter of the silicon oxide layer 122 substantially corresponds to the gate diameter.

Next, as shown in FIG. 12B, the p-type silicon substrate 121 is etched by reactive ion etching (RIE) under a condition of a high side etch rate to form an emitter 123.

Subsequently, as shown in FIG. 12C, a silicon oxide layer 124 for sharpening the tip of the emitter and for the insulating layer is formed on the surfaces of the p-type silicon substrate 121 and the emitter 123 by thermal oxidation. Due to the stress generated when the silicon oxide layer 124 is formed, the tip of the emitter 123 inside the silicon oxide layer 124 is easily sharpened.

Then, as shown in FIG. 12D, a material for the gate electrode 125 is formed, and the material of the gate electrode 125 is formed into a circular hole pattern for the emitter wiring by using photolithography.

Next, as shown in FIG. 12E, the silicon oxide layer 122 for an etching mask, which also functions as a lift-off material, is lifted off by etching, and the silicon oxide layer 124 on the surface of the emitter 123 is removed by etching. At the same time, an emitter wiring hole C is formed.

Subsequently, as shown in FIG. 12F, diffusion annealing is performed after ion implantation of phosphorus, and
3 is made n-type, and n is formed at the bottom of the emitter wiring hole C.
A mold silicon layer 126 is generated.

Finally, as shown in FIG. 12 (g), after forming a metal thin film 127 of aluminum or the like as an electrode material for the emitter wiring and the gate wiring, the gate electrode 125 is patterned as necessary. This allows MOSF
A cold electron emission device having an ET structure emitter is obtained.

In a cold electron emission device comprising a silicon emitter having such a MOSFET structure, although a MOS transistor can be easily manufactured in substantially the same manufacturing process as a conventional silicon emitter, a MOS transistor is built in the device. An extremely stable emission current controlled by a transistor can be obtained, and the generation of a local large current can be eliminated.

[0037]

However, in a cold electron emitting device provided with a resistance layer for stabilizing a current, a larger current reducing characteristic is required to obtain a sufficient current reduction characteristic with respect to a local large current. In addition to the necessity of providing a resistance, there has been a problem that the current fluctuation can be reduced only relative to the characteristics of the individual elements, and further, an increase in the operating voltage cannot be avoided in principle.

On the other hand, a MOSFE equipped with a current control function
With a silicon emitter having a T structure, a stable current can be obtained at a very high level by transistor control. However, since a single crystal silicon substrate is required, it is difficult to reduce the cost and increase the area. was there.

In the cold electron emitting device according to the prior art, since the driving voltage of the device is a drawing voltage (operating voltage) of cold electrons applied to the gate electrode, a high voltage of usually several tens of volts or more is required. Since a costly IC circuit cannot be used, there is a problem that the driving circuit becomes expensive.

The present invention is intended to solve the above-mentioned problems of the prior art. By mounting a current control function on a device itself using a semiconductor thin film, a local large scale operation can be performed without increasing the operating voltage. The current can be suppressed and the current fluctuation can be reduced to the minimum, and the cost and the area can be easily reduced by using a glass substrate, and the driving voltage can be reduced by providing the switching electrode separately from the gate electrode. It is an object of the present invention to provide a field emission type cold electron-emitting device and a method for manufacturing the same, which can reduce the circuit cost.

[0041]

Means for Solving the Problems The present inventor has provided a first conductive layer (drain) and a second conductive layer (source) on an insulating substrate, and provided at least an insulating substrate at a gap between the conductive layers. A thin film transistor (TFT) structure is realized by laminating a third conductive layer and a semiconductor thin film made of non-single-crystal silicon via a gate insulating layer on the third conductive layer, and further on the first conductive layer (drain). By forming an emitter made of non-single-crystal silicon, a thin film transistor can be easily formed in the vicinity of the emitter in the cold electron-emitting device without using a single-crystal silicon substrate. As a result, they have found that the current can be stabilized and that the driving voltage can be reduced by using the gate electrode of the thin film transistor as the switching electrode of the element, and have completed the present invention.

That is, according to the present invention, a first conductive layer, an insulating layer and a gate electrode are sequentially laminated on an insulating substrate, an opening is provided in the gate electrode and the insulating layer, and an emitter is provided in the opening. Are formed so as not to contact the gate electrode, the emitter is made of non-single-crystal silicon, and the second conductive layer is not in direct contact with the first conductive layer. A semiconductor thin film layer made of non-single-crystal silicon is provided on the insulating substrate between at least the first conductive layer and the second conductive layer; 3 conductive layer,
A cold electron emission element is provided above or below a semiconductor thin film layer via a gate insulating layer so as not to contact with the first conductive layer and the second conductive layer.

According to the present invention, there is provided a method of manufacturing a cold electron emitting device as described above, wherein the third conductive layer is provided on the semiconductor thin film via the gate insulating layer: (a) On the insulating substrate Forming a first conductive layer and a second conductive layer simultaneously without direct contact with each other by patterning the metal thin film layer by a photolithography method; Material layer,
A step of sequentially forming a gate insulating material layer and a third conductive material layer; (b) patterning by photolithography to form a third conductive layer, and then sequentially patterning by photolithography to perform gate insulation Forming a layer and a semiconductor thin film layer and leaving a resist layer; (c) a step of sequentially forming an emitter material and an etching mask material layer on at least the second conductive layer; and (d) photolithography of the etching mask material layer. Forming an etching mask layer by patterning holes having a shape corresponding to the opening diameter of the gate by a method, and forming an emitter by etching the emitter material by reactive ion etching until the first conductive layer is exposed; And (e) an insulating material is formed on the semiconductor thin film layer by anisotropic vapor deposition in a direction perpendicular to the insulating substrate. And forming a gate electrode material in a self-aligned manner, peeling off the etching mask layer, and simultaneously peeling off the insulating material layer and the gate electrode material on the emitter to form an insulating layer and a gate electrode. Is patterned by photolithography to form a gate insulating layer, and at the same time, stripping the resist layer together with the insulating material and the gate electrode material on the resist layer.

According to another aspect of the present invention, there is provided another method for manufacturing the above-mentioned cold electron-emitting device, wherein the third conductive layer is provided on the semiconductor thin film via the gate insulating layer. After forming a metal thin film layer on a substrate, the metal thin film layer is patterned by photolithography to form a first conductive layer and a second conductive layer simultaneously without direct contact with each other, A step of sequentially forming a semiconductor thin film layer, an emitter material, and an etching mask material layer; (b ') forming an etching mask layer by patterning the etching mask material layer into holes having a shape corresponding to the opening diameter of the gate by photolithography; Forming an emitter by etching the emitter material by reactive ion etching until the semiconductor thin film layer is exposed; (c ') an insulating substrate A step of forming an insulating material and a gate electrode material in a self-aligned manner on the semiconductor thin film layer by anisotropic vapor deposition in the vertical direction; (d ') removing the etching mask layer and simultaneously forming the insulating material on the emitter; Peel off the layer and gate electrode material,
Forming an insulating layer and a gate electrode; and (e ') patterning the insulating layer and the gate electrode by photolithography to form a gate insulating layer, and subsequently forming a third conductive layer by a lift-off method. There is provided a manufacturing method characterized by including a step.

According to the present invention, there is also provided a method for manufacturing a cold electron emitting device as described above, wherein the third conductive layer is provided on the semiconductor thin film via the gate insulating layer: (a ″) Insulating substrate After forming a metal thin film layer thereon, the metal thin film layer is patterned by photolithography to form a first conductive layer and a second conductive layer simultaneously so as not to directly contact each other. Forming a gate insulating material, a third conductive material sequentially, patterning by photolithography to form a third conductive layer, and further patterning by photolithography to form a gate insulating layer; (B ″) An emitter material and an etching mask material layer are sequentially formed, and the etching mask material layer is formed into a hole having a shape corresponding to the opening diameter of the gate by photolithography. To form an etching mask layer, and the reactive ion etching is used to convert the emitter material to an insulating layer or a first layer.
(C ″) an insulating layer material and a gate electrode material are formed on the semiconductor thin film layer by anisotropic vapor deposition in a direction perpendicular to the insulating substrate; (D ″) a step of forming an insulating layer and a gate electrode by peeling off the etching mask layer and simultaneously removing an insulating material and a gate electrode material on the emitter; and (e ″). A manufacturing method characterized by including a step of patterning an insulating layer and a gate electrode by a photolithography method to expose a third conductive layer and a gate insulating layer.

According to another aspect of the present invention, there is provided a method for manufacturing a cold electron-emitting device as described above, wherein the third conductive layer is provided below the semiconductor thin film via the gate insulating layer. After forming a metal thin film layer thereon, the metal thin film layer is patterned by photolithography to form a third conductive layer, and then a gate insulating layer, a semiconductor thin film material layer, and a metal thin film layer are sequentially formed. (G) patterning the metal thin film layer by photolithography to form a first conductive layer and a second conductive layer at the same time so as not to directly contact each other, and then to form at least a first conductive layer by photolithography. Forming a resist layer on the gap between the layer and the second conductive layer; (h) forming an emitter material and an etching mask material layer sequentially, and photolithography the etching mask material layer An etching mask layer is formed by patterning holes having a shape corresponding to the opening diameter of the gate by a method, and the emitter material is etched by reactive ion etching until the insulating layer or the first conductive layer is exposed to form an emitter. (I) forming an insulating layer material and a gate electrode material in a self-aligned manner on at least the second conductive layer by anisotropic vapor deposition in a direction perpendicular to the insulating substrate; and (j) At the same time as removing the etching mask layer, the insulating material and the gate electrode material on the emitter are peeled off to form the insulating layer and the gate electrode, and then the insulating layer material and the gate electrode material are patterned by photolithography to be insulated. Forming a layer and a gate electrode, stripping the resist layer, and simultaneously forming an insulating material and a gate electrode on the resist layer There is provided a manufacturing method, comprising a step of stripping a material.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings.

FIGS. 1 (a), 1 (a '), 1 (b) and 1 (b') show a third embodiment of the present invention in which a third conductive layer is provided on a semiconductor thin film layer via a gate insulating film. FIG. 3 is a cross-sectional view of the electron-emitting device.

That is, in the cold electron-emitting device shown in FIG. 1A, a first conductive layer 2 and a second conductive layer 3 are provided on the same plane of an insulating substrate 1, and the first conductive layer A semiconductor thin film layer 4 made of non-single-crystal silicon is continuously arranged from above the second conductive layer 3 to the gap A between the first conductive layer 2 and the second conductive layer 3. Then, on the semiconductor thin film layer 4 in the gap A between the first conductive layer 2 and the second conductive layer 3, a third conductive layer 6 is formed via a gate insulating layer 5 '. An insulating layer 5 and a gate electrode 7 are sequentially stacked on the first conductive layer 2, and an emitter hole B reaching the semiconductor thin film layer 4 is provided in the gate electrode 7 and the insulating layer 5. . A conical or frustoconical emitter 8 made of non-single-crystal silicon is formed on the first conductive layer 2 in the emitter hole B so as not to contact the gate electrode 7.

The cold electron-emitting device shown in FIGS. 2C and 2C has a structure in which the third conductive layer is provided below the semiconductor thin film layer via the gate insulating layer. It is sectional drawing of an element.

That is, in the cold electron-emitting device shown in FIG. 2C, a first conductive layer 2 and a second conductive layer 3 are provided on an insulating substrate 1, and the first conductive layer 2 and the second The semiconductor thin film layer 4 made of non-single-crystal silicon is continuously arranged from below the conductive layer 3 to the gap A between the first conductive layer 2 and the second conductive layer 3. A third conductive layer 6 is formed below the semiconductor thin film layer 4 in a gap A between the first conductive layer 2 and the second conductive layer 3 with a gate insulating layer 5 'interposed therebetween. Also,
An insulating layer 5 and a gate electrode 7 are sequentially stacked on the first conductive layer 2, and the gate electrode 7 and the insulating layer 5 are provided with an emitter hole B reaching the semiconductor thin film layer 4. Then, on the first conductive layer 2 in the emitter hole B,
A conical or frustoconical emitter 8 made of non-single-crystal silicon is formed so as not to contact the gate electrode 7.

Here, the first conductive layer 2, the second conductive layer 3, the semiconductor thin film layer 4, the gate insulating layer 5 ′, and the third conductive layer 6 work together in a thin film transistor operating in an n-channel enhancement mode. It constitutes a structure (TFT). That is, the first conductive layer 2 is a drain, the second conductive layer 3
Denotes a source, the semiconductor thin film layer 4 functions as a channel, the gate insulating layer 5 'functions as a gate insulating layer literally, and the third conductive layer 6 functions as a gate. In the present invention, in order to more easily control the thickness of the gate insulating film of the TFT, a structure in which the insulating layer is formed into two layers can be used.

Further, a lower extraction voltage (operating voltage)
From the viewpoint of obtaining the first, as shown in FIG.
The semiconductor thin film layer 4 is not interposed between the conductive layer 2 and the emitter 8. Further, from the viewpoint of obtaining better current control characteristics, FIGS.
1 (b) and FIG. 2 (c), respectively.
(A '), as shown in FIGS. 1 (b') and 2 (c '), respectively, between the first conductive layer 2 and the semiconductor thin film layer 4 and between the second conductive layer 3 and the semiconductor thin film layer 4 It is preferable that an ohmic layer 9 is interposed between them.

In the present invention, the insulating substrate 1 is used as a support substrate for a cold electron emission element, and an insulating substrate that can be easily formed in a large area can be preferably used.
As such an insulating substrate, a glass substrate, a ceramic substrate, a quartz substrate, or the like can be used, and among them, a glass substrate can be preferably used. A substrate in which an insulating layer is formed over the surface of single crystal silicon can also be used.

In the present invention, the first conductive layer 2 is made of TF
Functions as a drain of T. As a material of such a first conductive layer 2, a material having a low wiring resistance and a high adhesion to the underlying insulating substrate 1 is suitable. Such a material is particularly preferably a Cr or Al, Cr laminated film.

The thickness of the first conductive layer 2 is not particularly limited as long as sufficient wiring resistance and adhesion can be obtained.
It is 1 to 1.0 μm, preferably 0.05 to 0.5 μm.

The second conductive layer 3 functions as an emitter wiring layer and also functions as a source of the TFT. As a material of such a second conductive layer 3, a material having low wiring resistance and high adhesion to the underlying insulating substrate 1 is suitable. As such a material, Cr or Al, C is particularly preferable.
r laminated film.

The thickness of the second conductive layer 3 is not particularly limited as long as sufficient wiring resistance and adhesion can be obtained.
It is 1 to 1.0 μm, preferably 0.05 to 0.5 μm.

The semiconductor thin film layer 4 includes a thin film transistor (T
FT). Such a semiconductor thin film layer 4 can be formed from a known material similar to a TFT widely used as a switching element of a liquid crystal display, and preferably, non-single-crystal silicon can be used. Examples of such non-single-crystal silicon include amorphous silicon (especially non-doped hydrogenated amorphous silicon) and polysilicon.

When a glass substrate is used as the insulating substrate 1, amorphous silicon hydride or polysilicon obtained by laser annealing can be preferably used as the semiconductor thin film layer 4.

The thickness of the semiconductor thin film layer 4 is usually 0.01 to 2.0 as a thickness capable of operating as a TFT channel.
μm, preferably 0.03 to 0.7 μm.

The insulating layer 5 is a layer for electrically insulating the emitter 8 and the first conductive layer 2 from the gate electrode 7. Further, they are used simultaneously to electrically insulate the semiconductor thin film layer 4 and the third conductive layer 6. That is, T
It also functions as the gate insulating layer 5 'of the FT.

The insulating layer 5 is desirably anisotropically deposited to form in a self-aligned manner, and is a silicon oxide formed by a reactive chimney resistance heating deposition method using a mixed gas of ozone and oxygen as a reactive gas. Is particularly preferred since good insulation can be obtained. However, a gate insulating layer of the TFT is separately formed depending on a manufacturing method. In such a case, the insulating layer 5 can be formed from a known material similar to a conventional TFT. For example, PECV
Silicon nitride or silicon oxide by the D method can be used.

The thickness of the insulating layer 5 may be such that sufficient insulation between the emitter 8, the first conductive layer 2 or the semiconductor thin film layer 4 and the gate electrode 7 is maintained around the emitter. , 0.2 to 2.0 μm, preferably 0.3
１．０1.0 μm. Further, in order to function as the gate insulating layer 5 'of the TFT portion, usually, 0.01 to 1.0.
0 μm, preferably 0.03 to 0.5 μm.

The third conductive layer 6 functions as a gate of the TFT. Examples of the material of the third conductive layer 6 include:
A material having low wiring resistance and high adhesion to the lower insulating layer 5 is suitable. Such a material is particularly preferably C
r or an Al or Cr laminated film.

The thickness of the third conductive layer 6 is not particularly limited as long as sufficient wiring resistance and adhesion can be obtained.
It is 5 to 2.0 μm, preferably 0.05 to 0.5 μm.

The gate electrode 7 is an electrode for concentrating a strong electric field on the emitter 8. As a material for the gate electrode 7, a material having a high melting point from the viewpoint of current resistance and having resistance to an etching solution used for forming an emitter can be used. Preferably, Cr, W, Ta or Nb is used. Can be mentioned.

The thickness of the gate electrode 7 can be appropriately determined as needed, but is preferably 0.1 to 0.5 μm.
m.

The emitter 8 is a member that directly emits electrons from its surface, and uses a non-single-crystal silicon thin film. Here, when the emitter 8 is formed of a non-single-crystal silicon thin film, for example, a polysilicon thin film or an amorphous silicon thin film, more stable emission characteristics can be obtained because the emitter itself has a certain degree of resistance.

The thickness (height) of the entire emitter 8 can be appropriately determined as necessary, but is preferably 0.3
２．０2.0 μm.

The shape of the emitter 8 is preferably a cone or a cylinder, or a truncated cone or a truncated polygon.

The ohmic layer 9 is provided for obtaining an ohmic contact between the first conductive layer 2 and the second conductive layer 3 and the semiconductor thin film layer 4 or for obtaining a better ohmic contact. Such a material of the ohmic layer 9 can be formed from a known material similar to a conventional TFT. For example, n-type hydrogenated amorphous silicon by PE (plasma enhanced) CVD using a mixed gas of at least silane and phosphine as a reaction gas can be used.

The thickness of the ohmic layer 9 is not particularly limited as long as sufficient ohmic characteristics can be obtained.
To 1.0 μm, preferably 0.03 to 0.07 μm.

Next, a method of manufacturing the cold electron-emitting device of the embodiment shown in FIG. 1A will be described in detail with reference to FIG.

Step (a) First, after a metal thin film is formed on the insulating substrate 1 by a sputtering method or the like, the first conductive layer 2 and the second conductive layer 3 are formed by photolithography on the channel length of the TFT. Patterning is performed by providing a corresponding gap and a width corresponding to the channel width.

Next, a semiconductor thin film material layer 4 'of non-single-crystal silicon or the like is formed by a CVD method or the like. Here, as the semiconductor thin film material layer 4 ', hydrogenated amorphous silicon formed by PECVD or thermal CVD or PCVD
A polysilicon film formed by annealing an amorphous silicon film formed by the ECVD method by, for example, laser annealing or the like can be preferably used.

Subsequently, an insulating film is formed as the gate insulating material layer 5a. Here, as the gate insulating material layer 5a, a silicon oxide film or a silicon nitride film formed by a PECVD method, an evaporation method, or a sputtering method can be used. Particularly preferably, a silicon nitride film formed by a PECVD method using a mixed gas of silane and ammonia as a reaction gas can be used.

Further, on the gate insulating material layer 5a, a third
A metal thin film is formed as the conductive material layer 6 'by using a normal film forming method such as an evaporation method or a sputtering method (FIG. 3A).

Step (b) Next, the third conductive material layer 6 ′ is patterned by photolithography so as to be disposed immediately above the TFT channel to form a third conductive layer 6. The gate insulating material layer 5a and the semiconductor thin film material layer 4 'are sequentially patterned so that the second conductive layer 3 is exposed, thereby forming the gate insulating layer 5' and the semiconductor thin film layer 4. At this time, the resist used for patterning is left as the protective layer 11 and TF is used in the subsequent steps.
It is used for protecting T (FIG. 3B).

Step (c) Subsequently, the emitter material 8 'such as non-single-crystal silicon is
The film is formed by a VD method or the like. Here, as a film forming method of the emitter material 8 ', a PECVD method using a mixed gas of silane or disilane and phosphine as a reaction gas is preferable. In this case, an n-type hydrogenated amorphous silicon film can be formed. Alternatively, a sputtering method can also be preferably used, and in this case, an amorphous silicon film can be formed.

Subsequently, a silicon oxide film is formed as an etching mask material layer 10 'using a normal film forming method such as a vapor deposition method or a sputtering method (FIG. 3C).

Step (d) Next, an etching mask layer 10 is formed by patterning holes (circular or polygonal) having a shape corresponding to the opening diameter of the gate in the etching mask material layer 10 'by photolithography. The emitter 8 is formed by etching the emitter material 8 'by ionic ion etching until the second conductive layer 3 is exposed.

Then, an insulating material 5 ″ and a gate electrode material 7 ′ are deposited on the semiconductor thin film layer 4 by normal anisotropic vapor deposition from the vertical direction. At this time, the insulating material 5 ″
In order to form the film in a self-aligned manner, anisotropic vapor deposition is desirable, and a silicon oxide film formed by a reactive chimney resistance heating vapor deposition method using a mixed gas of ozone and oxygen as a reaction gas is used (FIG. 3D )).

Step (e) Next, the etching mask layer 10 is peeled off by etching to form the insulating layer 5 and the gate electrode 7. The gate electrode 7 is patterned as required. At this time, when the resist used at the end of the patterning is stripped, the protective layer 11 can also be stripped at the same time (FIG. 3E). Thus, the cold electron-emitting device shown in FIG. 1A is obtained.

In the case where the ohmic layer 9 is provided,
In the step (a), after forming a metal thin film on the insulating substrate 1, an ohmic layer is formed subsequently. As the ohmic layer, for example, n-type hydrogenated amorphous silicon can be used. The pattern nig may be performed simultaneously with the metal thin film.

Next, a method of manufacturing another cold electron-emitting device according to the embodiment of FIG. 1A will be described in detail with reference to FIG. Step (a ') First, after a metal thin film is formed on the insulating substrate 1 by a sputtering method or the like, the first conductive layer 2 and the second conductive layer 3 corresponding to the channel length of the TFT are formed by a photolithography method. Patterning is performed by providing a width corresponding to the gap and the channel width.

Next, a semiconductor thin film layer 4 of non-single-crystal silicon or the like and an emitter material 8 'are formed by a CVD method or the like.
Here, as the semiconductor thin film layer 4, a hydrogenated amorphous silicon film formed by a PECVD method, or a polysilicon film formed by annealing an amorphous silicon film formed by a thermal CVD or PECVD method, for example, by laser annealing or the like Can be preferably used.

As a film forming method of the emitter material 8 ', a PECVD method using a mixed gas of silane or disilane and phosphine as a reaction gas is preferable. In this case, an n-type hydrogenated amorphous silicon film can be formed. Alternatively, a sputtering method can also be preferably used, and in this case, an amorphous silicon film can be formed.

Subsequently, a silicon oxide film is formed as an etching mask material layer 10 'using a normal film forming method such as an evaporation method or a sputtering method (FIG. 4A').

Step (b ') Next, the etching mask material layer 10' is patterned into holes (circular or polygonal) having a shape corresponding to the opening diameter of the gate by photolithography to form the etching mask layer 10. The emitter 8 is formed by etching the emitter material 8 'by reactive ion etching until the semiconductor thin film layer 4 is exposed (FIG. 4 (b')).

Step (c ') Subsequently, an insulating material 5 "and a gate electrode material 7' are deposited on the semiconductor thin film layer 4 by normal anisotropic vapor deposition from the vertical direction (FIG. 4 (c ')). At this time, the insulating material 5 ″ is desirably anisotropic vapor deposition in order to form in a self-aligned manner, and is oxidized by a reactive chimney type resistance heating vapor deposition method using a mixed gas of ozone and oxygen as a reactive gas. Use a silicon film.

Step (d ') Next, the etching mask layer 10 is peeled off by etching to form the insulating layer 5 and the gate electrode 7. The gate electrode 7 is patterned if necessary (FIG. 4D ').

Step (e ′) Finally, the insulating layer 5 and the gate electrode 7 are patterned by photolithography to form a gate insulating layer 5 ′ of a predetermined thickness of the TFT, and a third gate insulating layer 5 ′ is formed immediately above the TFT channel.
Is formed by photolithography, for example, by a lift-off method (FIG. 4E '). Thus, another cold electron-emitting device shown in FIG. 1A is obtained.

When the ohmic layer 9 is provided,
In the step (a '), after forming a metal thin film on the insulating substrate 1, an ohmic layer is formed subsequently. As the ohmic layer, for example, n-type hydrogenated amorphous silicon can be used. The patterning may be performed simultaneously with the metal thin film.

Next, a method for manufacturing the cold electron-emitting device of the embodiment shown in FIG. 1B will be described in detail with reference to FIG.

Step (a ″) First, a thin metal film is formed on an insulating substrate 1 by a sputtering method or the like, and then a first conductive layer 2 and a second conductive layer 3 are formed by photolithography on the TFT. Patterning is performed by providing a gap corresponding to the channel length and a width corresponding to the channel width.

Next, a semiconductor thin film layer 4 of non-single-crystal silicon or the like and a gate insulating layer 5 'are formed by a CVD method or the like. Here, as the semiconductor thin film layer 4, hydrogenated amorphous silicon formed by PECVD or thermal CV
A polysilicon film formed by annealing an amorphous silicon film formed by D or PECVD, for example, by laser annealing or the like can be preferably used.

As a method for forming the gate insulating layer 5 ', a PECVD method for forming a silicon nitride film using a mixed gas of silane and ammonia as a reaction gas is preferable.

Subsequently, a metal thin film is formed by a normal film forming method such as an evaporation method or a sputtering method, and then patterned by photolithography to form a third gate as a TFT gate.
Is formed.

Further, the semiconductor thin film layer 4 and the gate insulating layer 5 'are patterned by photolithography into a shape excluding a portion to be a base of the emitter (FIG. 5).
(A ″)).

Step (b ″) Next, non-single-crystal silicon is formed as an emitter material.The emitter material is formed by using an n-type mixed gas of silane or disilane and phosphine as a reaction gas. PE to form hydrogenated amorphous silicon
A CVD method or a sputtering method for forming amorphous silicon is preferable.

Next, an etching mask layer 10 is formed by patterning the etching mask material into holes having a shape corresponding to the opening diameter of the gate by photolithography.
An emitter 8 is formed by etching the emitter material by reactive ion etching until the semiconductor thin film layer 4 is exposed (FIG. 5 (b ″)).

Step (c ″) Subsequently, the insulating material layer 5 ″ and the gate electrode material 7 ′ are deposited on the gate insulating layer 5 ′ by ordinary anisotropic vapor deposition from the vertical direction (FIG. 5 ( c ″)) At this time, anisotropic vapor deposition is desirable as the insulating material layer 5 ″ in order to form in a self-aligned manner, and reactive chimney type resistance heating vapor deposition using a mixed gas of ozone and oxygen as a reactive gas. A silicon oxide film formed by a method is used.

Step (d ″) Next, the etching mask layer 10 is removed by etching to form an insulating layer 5 and a gate electrode 7. The gate electrode 7 is patterned as necessary (FIG. 5 (d ″)). .

Step (e ″) Finally, the third conductive layer 6 and the gate insulating layer 5 ′ are exposed while patterning the insulating layer 5 and the gate electrode 7 by photolithography (FIG. 5 (e ″)). ). Thus, the cold electron emitting device of FIG. 1B is obtained.

When the ohmic layer 9 is provided,
In the step (a ″), an ohmic layer is subsequently formed after forming a metal thin film on the insulating substrate 1. As the ohmic layer, for example, n-type hydrogenated amorphous silicon can be used. It may be performed simultaneously with the metal thin film.

As described above, in the cold electron-emitting device of the present invention, the T
By having an FT structure and forming an emitter of non-single-crystal silicon on a drain electrode, an emission current highly controlled by a transistor can be obtained even on an insulating substrate, and a gate electrode (lead electrode) of the emitter. Instead, low-voltage driving can be achieved by driving using the gate of the TFT as a switching electrode.

Next, a method of manufacturing the cold electron-emitting device of the embodiment shown in FIG. 2C will be described in detail with reference to FIG.

Step (f) First, after a metal thin film layer is formed on the insulating substrate 1 by sputtering or the like, the third conductive layer 6 is provided by patterning by photolithography.

Next, a gate insulating layer 5 'of silicon oxide, silicon nitride or the like is formed by a CVD method or the like. Here, as the gate insulating layer 5 ', silicon oxide or silicon nitride formed by a PECVD method can be preferably used. In particular, as a method for forming the gate insulating layer 5 ', a PECVD method in which a silicon nitride film is formed using a mixed gas of silane and ammonia as a reaction gas is preferable.

Next, a semiconductor thin film layer 4 of non-single-crystal silicon or the like is formed by a CVD method or the like. Here, as the semiconductor thin film layer 4, a hydrogenated amorphous silicon film formed by a PECVD method, or a polysilicon film formed by annealing an amorphous silicon film formed by a thermal CVD or PECVD method, for example, by laser annealing or the like Can be preferably used.

Subsequently, a metal thin film 3 'is formed by a normal film forming method such as a vapor deposition method or a sputtering method (FIG. 6 (f)).

Step (g) Next, the metal thin film 3 ′ is formed on the first conductive layer 2 and the second conductive layer 3 by photolithography to form a gap corresponding to the channel length of the TFT and a width corresponding to the channel width. And patterning.

Further, the semiconductor thin film layer 4 and the gate insulating layer 5 'are patterned by photolithography into a shape excluding a portion to be a base of the emitter. Then, the resist pattern used in the photolithography method is left as the protective layer 11 in the subsequent steps (FIG. 6).
(G)).

Step (h) Next, non-single-crystal silicon is formed as the emitter material 8 '. As a method for forming a film of the emitter material, a sputtering method for forming amorphous silicon is preferable.

Subsequently, a silicon oxide film is formed as an etching mask material layer 10 'by using a normal film forming method such as an evaporation method or a sputtering method (FIG. 6 (h)).

Step (i) Next, an etching mask layer 10 is formed by patterning the etching mask material into holes having a shape corresponding to the opening diameter of the gate by photolithography, and the emitter material is changed to a semiconductor thin film by reactive ion etching. The emitter 8 is formed by etching until the layer 4 is exposed.

Subsequently, the insulating material layer 5 ″ and the gate electrode material 7 ′ are deposited on the gate insulating layer 5 ′ from the vertical direction by ordinary anisotropic vapor deposition (FIG. 6 (i)). At this time, as the insulating material layer 5 ″, anisotropic vapor deposition is desirable in order to form in a self-aligned manner, and a silicon oxide film formed by a reactive chimney resistance heating vapor deposition method using a mixed gas of ozone and oxygen as a reaction gas is used. use.

Step (j) Next, the etching mask layer 10 is peeled off by etching to form the insulating layer 5 and the gate electrode 7. The gate electrode 7 is patterned as needed (FIG. 6 (j)). Thereby, the cold electron emitting device of FIG. 2C is obtained.

When the ohmic layer 9 is provided,
In the step (f), after the semiconductor thin film layer 4 is formed, an n-type hydrogenated amorphous silicon layer is subsequently formed. The patterning may be performed simultaneously with the metal thin film 3 '.

As described above, in the cold electron-emitting device of the present invention, the T
By having an FT structure and forming an emitter of non-single-crystal silicon on a drain electrode, an emission current highly controlled by a transistor can be obtained even on an insulating substrate, and a gate electrode (lead electrode) of the emitter. Instead, low-voltage driving can be achieved by driving using the gate of the TFT as a switching electrode.

[0122]

EXAMPLES The production examples of the cold electron-emitting device of the present invention will be specifically described in the following examples.

Example 1 (Example of manufacturing a cold electron-emitting device according to the embodiment of FIG. 1A (see FIG. 3)) Step (a) First, Cr was deposited as a metal thin film on an insulating substrate 1 by a sputtering method. After forming a film having a thickness of 1 μm, the first conductive layer 2 and the second conductive layer 3 were patterned by photolithography to form a channel of the TFT.

Next, a non-doped hydrogenated amorphous silicon film having a thickness of 0.1 μm was formed as the semiconductor thin film layer 4 by PECVD. Silane gas was used as the reaction gas, and hydrogen was used as the diluent gas.
0 sccm, gas pressure 1 Torr, substrate temperature 250 ° C, R
The film was formed under the condition of F power of 60 W.

Subsequently, as the gate insulating layer 5 ', reactive deposition was performed using a chimney resistance heating method, using silicon monooxide as a deposition source and a mixed gas of oxygen and ozone as a reaction gas. The conditions are (deposition pressure: 5 × 10
^-6 Torr / evaporation rate: 20 nm / sec).

Subsequently, Cr was formed as a metal thin film to a thickness of 0.2 μm by a sputtering method (FIG. 3A).

Step (b) Next, the third conductive layer 6 was patterned by photolithography to form a gate of the TFT. Further, the gate insulating layer 5 'and the semiconductor thin film layer 4 were patterned by photolithography to expose the second conductive layer 3 and form a TFT island. Here, the resist pattern used for the photolithography was left as the protective layer 11 of the TFT in the subsequent steps (FIG. 3).
(B)).

Step (c) Next, n is used as the emitter material 8 'by PECVD.
A hydrogenated amorphous silicon film having a thickness of 0.8 μm was formed. A silane gas and a phosphine gas (dope concentration: 3000 ppm) were used as a reaction gas, and hydrogen was used as a diluent gas.
The film was formed under the conditions of Torr, substrate temperature of 350 ° C., and RF power of 60 W.

Subsequently, a silicon oxide film having a thickness of 0.2 μm was formed as an etching mask material layer 10 ′ by a vapor deposition method (FIG. 3C).

Step (d) Next, a circular pattern having a gate opening diameter of 1.2 μm is formed by using a usual photolithography method to obtain an etching mask layer 10, and then the emitter material 8 ′ is formed by reactive ion etching. Was etched until the semiconductor thin film layer 4 was exposed. The etching conditions at this time were (introduced gas: SF _{6 60} sccm
/ Power 100W / gas pressure 4.5Pa).

Subsequently, silicon oxide was used as an insulating material 5 ″ by anisotropic vapor deposition from a direction perpendicular to the substrate,
Nb is 0.6 μm each as a gate electrode material 7 ′.
And a film thickness of 0.2 μm. Here, as a method of forming the insulating material 5 ″, reactive evaporation was performed by using a chimney resistance heating method and using silicon monooxide as an evaporation source and a mixed gas of oxygen and ozone as a reaction gas.
The conditions are as follows (deposition pressure: 5 × 10 ^-6 Torr / deposition rate: 2
0 nm / sec) (FIG. 3D).

Step (e) Next, the silicon oxide of the etching mask layer 10 is wet-etched using a buffered hydrofluoric acid solution to be peeled off together with the upper insulating material 5 ″ and the gate electrode material 7 ′.
And a gate electrode 7 were formed.

Finally, the gate electrode 7 was patterned into a predetermined shape by photolithography. Here, when the resist pattern used in the photolithography method was stripped, the protective layer 11 was also stripped at the same time (FIG. 3).
(E)). Thus, the cold electron-emitting device shown in FIG. 1A was obtained.

Example 2 (Example of manufacturing another cold electron-emitting device according to the embodiment of FIG. 1A (see FIG. 4)) Step (a ') First, Cr was sputtered on insulating substrate 1 as a metal thin film. After that, the first conductive layer 2 and the second conductive layer 3 were patterned by photolithography to form a TFT channel.

Next, a non-doped hydrogenated amorphous silicon film having a thickness of 0.1 μm was formed as the semiconductor thin film layer 4 by PECVD. Silane gas was used as the reaction gas, and hydrogen was used as the diluent gas.
0 sccm, gas pressure 1 Torr, substrate temperature 250 ° C, R
The film was formed under the condition of F power of 60 W.

Next, PECVD is used as the emitter material 8 '.
The n-type hydrogenated amorphous silicon film is set to 0.
The film was formed with a thickness of 8 μm. A silane gas and a phosphine gas (dope concentration: 3000 ppm) are used as a reaction gas, and hydrogen is used as a diluent gas.
m, gas pressure of 1 Torr, substrate temperature of 350 ° C., and RF power of 60 W.

Subsequently, a silicon oxide film having a thickness of 0.2 μm was formed as an etching mask material layer 10 ′ by vapor deposition (FIG. 4 (a ′)).

Step (b ′) Next, a circular pattern having a gate opening diameter of 1.2 μm is formed by using ordinary photolithography to obtain an etching mask layer 10, and then the emitter material 8 is formed by reactive ion etching. 'Hydrogenated amorphous silicon was etched until the semiconductor thin film layer 4 was exposed. The etching conditions at this time were (introduced gas: SF _{6 60} sccm
/ Power 100 W / gas pressure 4.5 Pa) (FIG. 4).
(B ')).

Step (c ') Next, silicon oxide is used as the insulating material 5 ", Nb is used as the gate electrode material 7', 0.6 μm and 0 μm, respectively, by anisotropic vapor deposition from the direction perpendicular to the substrate. .2μ
m was deposited. Here, as a method of forming the insulating material 5 ″, reactive deposition was performed by using a chimney resistance heating method and using silicon monooxide as a deposition source and a mixed gas of oxygen and ozone as a reaction gas. Deposition pressure: 5 × 10 ⁻⁶ Torr / deposition rate: 20 nm / se
c) (FIG. 4 (c ')).

Step (d ') Next, the silicon oxide of the etching mask layer 10 is wet-etched by using a buffered hydrofluoric acid solution, and peeled off together with the upper insulating material 5 "and the gate electrode material 7'.
And a gate electrode 7 were formed (FIG. 4 (d ')).

Step (e ') Finally, the gate electrode 7 and the insulating layer 5 were etched by 0.5 .mu.m by photolithography to leave a thickness of 0.1 .mu.m, thereby forming a gate insulating layer 5'. Next, after forming a resist negative pattern of the third conductive layer 6 pattern by photolithography, Cr was deposited to a thickness of 0.2 μm, and the resist was peeled off together with Cr to form a third conductive layer 6. (FIG. 4 (e ')). Thus, the cold electron-emitting device shown in FIG. 1A was obtained.

Example 3 (Example of manufacturing a cold electron-emitting device according to the embodiment of FIG. 1B (see FIG. 5)) Step (a ″) First, Cr was deposited as a metal thin film on the insulating substrate 1 by sputtering. After forming the first conductive layer 2 and the second conductive layer 3 by photolithography, a channel of the TFT was formed.

Next, a non-doped hydrogenated amorphous silicon film having a thickness of 0.1 μm was formed as the semiconductor thin film layer 4 by PECVD. Silane gas was used as the reaction gas, and hydrogen was used as the diluent gas.
0 sccm, gas pressure 1 Torr, substrate temperature 250 ° C, R
The film was formed under the condition of F power of 60 W.

Next, PECVD is used as the gate insulating layer 5 '.
A silicon nitride film was formed to a thickness of 0.1 μm by the method. Using a mixed gas of silane and ammonia as a reaction gas and hydrogen as a diluting gas, a total gas flow rate of 540 sc
cm, gas pressure of 1 Torr, substrate temperature of 350 ° C., and RF power of 60 W.

Subsequently, a Cr thin film having a thickness of 0.2 μm was formed as a metal thin film by sputtering, and then the third conductive layer 6 was patterned by photolithography to form a TFT.
Gate was formed. Further, an emitter hole B was formed by patterning the gate insulating layer 5 'and the semiconductor thin film layer 4 by photolithography (FIG. 5).
(A ″)).

Step (b ″) Next, an n-type hydrogenated amorphous silicon film having a thickness of 0.8 μm was formed as a material for the emitter by PECVD using a silane gas and a phosphine gas (doping concentration: 3000 ppm) as reaction gases. Also, hydrogen was used as a diluent gas, the total gas flow rate was 560 sccm, and the gas pressure was 1 To.
The film was formed under the conditions of rr, substrate temperature of 350 ° C., and RF power of 60 W.

Subsequently, a silicon oxide film having a thickness of 0.2 μm was formed as an etching mask material layer by an evaporation method. Next, a circular pattern having a gate opening diameter of 1.2 μm is formed using a normal photolithography method, and hydrogenated amorphous silicon as an emitter material is etched by reactive ion etching until the semiconductor thin film layer 4 is exposed. An emitter 8 was obtained. The etching conditions at this time were (introduced gas: SF _{6 60} sccm / power 100 W / gas pressure 4.5 Pa) (FIG. 5).
(B ″)).

Step (c ″) Next, silicon oxide is used as the insulating material 5 ″, Nb is used as the gate electrode material 7 ′, and 0.6 μm and 0 μm are formed by anisotropic vapor deposition from the direction perpendicular to the substrate. .2μ
m was deposited. Here, as a method of forming the insulating material 5 ″, reactive deposition was performed by using a chimney resistance heating method and using silicon monooxide as a deposition source and a mixed gas of oxygen and ozone as a reaction gas. Deposition pressure: 5.times.10@-6 Torr / deposition rate: 20 nm / se
c) (FIG. 5 (c ″)).

Step (d ″) Next, the etching mask layer 10 is wet-etched with silicon oxide using a buffered hydrofluoric acid solution, and peeled off together with the upper insulating material 5 ″ and the gate electrode material 7 ′.
And a gate electrode 7 were formed (FIG. 5 (d ″)).

Step (e ″) Finally, the gate electrode 7 and the insulating layer 5 were further patterned by photolithography to expose the third conductive layer 6 (FIG. 5 (e ″)). Thus, the cold electron-emitting device shown in FIG. 1B was obtained.

Example 4 (Example of manufacturing a cold electron-emitting device according to the embodiment of FIG. 2C (see FIG. 6)) Step (f) First, Cr was deposited as a metal thin film on the insulating substrate 1 by sputtering to a thickness of 0.1 mm. After forming a film with a thickness of 1 μm, the third conductive layer 3 is patterned by photolithography to form TF
A T gate was formed.

Next, PECVD is used as the gate insulating layer 5 '.
A silicon nitride film was formed to a thickness of 0.1 μm by the method. Using a mixed gas of silane and ammonia as a reaction gas and hydrogen as a diluting gas, a total gas flow rate of 540 sc
cm, gas pressure of 1 Torr, substrate temperature of 350 ° C., and RF power of 60 W.

Subsequently, PECVD is used as the semiconductor thin film layer 4.
A non-doped hydrogenated amorphous silicon film having a thickness of 0.1 μm was formed by the method. Using silane gas as the reaction gas and hydrogen as the diluent gas, the total gas flow rate is 3
00 sccm, gas pressure 1 Torr, substrate temperature 250 ° C,
The film was formed under the condition of RF power of 60 W.

Subsequently, Cr was formed as a metal thin film 3 'with a thickness of 0.2 μm by sputtering (FIG. 6).
(F)).

Step (g) Next, the first conductive layer 2 and the second conductive layer 3 are patterned on the metal thin film 3 'by photolithography,
An FT channel was formed. Furthermore, patterning by photolithography method to form a resist pattern,
In the subsequent steps, the protective layer 11 of the TFT was formed (FIG. 6).
(G)).

Step (h) Next, an amorphous silicon film having a thickness of 0.8 μm was formed as the emitter material 8 ′ by sputtering. The film was formed at room temperature.

Subsequently, a silicon oxide film having a thickness of 0.2 μm was formed as an etching mask material layer 10 ′ by vapor deposition (FIG. 6H).

Step (i) Next, a circular pattern having a gate opening diameter of 1.2 μm is formed by a usual photolithography method to obtain an etching mask layer 10, and then the emitter material 8 is formed by reactive ion etching. 'Hydrogenated amorphous silicon was etched until the semiconductor thin film layer 4 was exposed. The etching conditions at this time were (introduced gas: SF _{6 60} scc)
m / power 100 W / gas pressure 4.5 Pa).

Subsequently, silicon oxide was used as an insulating material 5 ″ by anisotropic vapor deposition from a direction perpendicular to the substrate.
Nb is 0.6 μm each as a gate electrode material 7 ′.
And a film thickness of 0.2 μm. Here, as a method of forming the insulating material 5 ″, reactive evaporation was performed by using a chimney resistance heating method and using silicon monooxide as an evaporation source and a mixed gas of oxygen and ozone as a reaction gas.
The conditions are as follows (deposition pressure: 5 × 10 ^-6 Torr / deposition rate: 2
0 nm / sec) (FIG. 6 (i)).

Step (j) Next, the silicon oxide of the etching mask layer 10 is wet-etched by using a buffered hydrofluoric acid solution to be peeled off together with the upper insulating material 5 ″ and the gate electrode material 7 ′.
And a gate electrode 7 were formed.

[0161] Finally, the gate electrode 7 was patterned into a predetermined shape by photolithography. Here, when the resist pattern used for the photolithography was stripped, the protective layer 11 was also stripped at the same time (FIG. 6).
(J)). As a result, the cold electron-emitting device shown in FIG. 2C was obtained.

(Evaluation) The above-mentioned cold electron-emitting device was fabricated as a prototype, and tested and evaluated as follows. That is, the distance between the emitter and the gate electrode of each element is 0.6 μm, and the height of the emitter is 0.1 μm.
A glass plate member having a transparent electrode (anode) coated with a phosphor was opposed at a distance of 30 mm to an element having a structure having a channel length L / channel width W: 1/10 as a TFT parameter at a distance of 30 mm. When a withdrawing voltage was applied between the electrodes with a polarity such that the gate electrode side was positive, electrons were successfully and stably emitted at a switching voltage of about 10 V.

(Evaluation) The cold electron-emitting devices obtained in Examples 1, 2 and 3 were tested and evaluated as follows. That is,
The distance between the emitter and the gate electrode of each element was 0.6 μm, the height of the emitter was 0.8 μm, and the ratio (L / W) of the channel length (L) to the channel width (W) was 1 as the TFT parameter. A glass plate member having a transparent electrode (anode) coated with a phosphor is opposed to the element having a structure of / 10 at a distance of 30 mm, and an extraction voltage is applied between the emitter electrode and the gate electrode with a polarity where the gate electrode side is positive. Upon application, electrons were successfully and stably emitted at a switching voltage of about 10V.

FIG. 13 is a schematic diagram of the obtained typical emission characteristics. In the low electric field region, the current-voltage characteristic (E) of the emitter itself was exhibited, and in the high electric field region, a saturation characteristic according to the current-voltage characteristic (M) of the TFT was exhibited. That is, in a high electric field region where the emission current exceeds the drain current value of the TFT, a saturation current region is obtained by transistor control of the current. In this device, a stable emission current (ME) was obtained at an extraction voltage of 110 V or more. Further, an emission current was obtained when the gate voltage of the TFT was 4 V or more, and switching was possible at a low voltage.

[0165]

According to the present invention, by forming an emitter with a metal having a TFT structure, an emission current highly controlled by a transistor can be obtained even on an insulating substrate, and a switching electrode can be used as a gate electrode. By separately providing the cold electron emission element, it is possible to obtain a cold electron emission element that can easily reduce the driving voltage.

Therefore, it is possible to obtain a cold electron-emitting device which has high current stability and can be driven at a low voltage on a glass substrate which can be made large in area at low cost. Further, even when applied to a flat panel display, a high-speed, high-definition image can be obtained with low power consumption.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view (FIGS. (A), (b), (a ′), (b ′)) of a cold electron emission element of the present invention.

FIG. 2 is a cross-sectional view (FIGS. (C) and (c ′)) of another cold electron-emitting device of the present invention.

FIG. 3 is a manufacturing process diagram of the cold electron emission device of the present invention.

FIG. 4 is a manufacturing process diagram of another cold electron-emitting device of the present invention.

FIG. 5 is a manufacturing process diagram of another cold electron-emitting device of the present invention.

FIG. 6 is a manufacturing process diagram of another cold electron-emitting device of the present invention.

FIG. 7 is a cross-sectional view of a conventional cold electron emission element.

FIG. 8 is a manufacturing process diagram of a conventional cold electron-emitting device.

FIG. 9 is a cross-sectional view of another conventional cold electron emission element.

FIG. 10 is a cross-sectional view of a conventional cold electron-emitting device.

FIG. 11 is a manufacturing process diagram of another conventional cold electron-emitting device.

FIG. 12 is a manufacturing process diagram of another conventional cold electron emission element.

FIG. 13 is a schematic diagram illustrating an example of electrical characteristics of the cold electron emission element of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Insulating substrate 2 First conductive layer 3 Second conductive layer 4 Semiconductor thin film layer 5 Insulating layer 5 ′ Gate insulating layer 6 Third conductive layer 7 Gate electrode 8 Emitter 9 Ohmic layer

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masago Kanamaru 1-1-4 Umezono, Tsukuba, Ibaraki Pref. Within the Institute of Electronics and Technology (72) Inventor Junji Ito 1-4-1, Umezono, Tsukuba, Ibaraki Inside the Electronic Technology Research Institute, Industrial Technology Institute

Claims (46)

[Claims] A first conductive layer, an insulating layer, and a gate electrode are sequentially laminated on an insulating substrate, an opening is provided in the gate electrode and the insulating layer, and an emitter is provided in the opening in the gate electrode. In the field emission type cold electron emission element formed so as not to contact with the substrate, the emitter is made of non-single-crystal silicon, and the insulating substrate is arranged so that the second conductive layer does not directly contact with the first conductive layer. A semiconductor thin film layer made of non-single-crystal silicon is provided on at least an insulating substrate between the first conductive layer and the second conductive layer; and a third conductive layer Is provided above or below the semiconductor thin film layer via a gate insulating layer so as not to contact with the first conductive layer and the second conductive layer. 2. The cold electron-emitting device according to claim 1, wherein the third conductive layer is provided on the semiconductor thin film layer via a gate insulating layer. 3. The cold electron-emitting device according to claim 1, wherein the third conductive layer is provided below the semiconductor thin film layer via a gate insulating layer. 4. The cold electron-emitting device according to claim 1, wherein the non-single-crystal silicon constituting the emitter and the semiconductor thin film layer is amorphous silicon or polysilicon. 5. The cold electron-emitting device according to claim 4, wherein the emitter is made of n-type hydrogenated amorphous silicon. 6. The cold electron-emitting device according to claim 4, wherein the semiconductor thin film layer is made of non-doped hydrogenated amorphous silicon. 7. The ohmic layer according to claim 1, wherein an ohmic layer is sandwiched between the first conductive layer and the semiconductor thin film layer and between the second conductive layer and the semiconductor thin film layer. Cold electron emission device. 8. The cold electron-emitting device according to claim 7, wherein the ohmic layer is made of n-type hydrogenated amorphous silicon. 9. The cold electron-emitting device according to claim 1, wherein an emitter is provided directly on the first conductive layer. 10. A first conductive layer, a second conductive layer, and a third conductive layer surrounding a semiconductor thin film layer form a thin film transistor structure functioning as a drain electrode, a source electrode, and a gate electrode, respectively. 2. The thin film transistor operates in an n-channel enhancement mode.
10. The cold electron-emitting device according to any one of claims 9 to 9. 11. The cold electron emission device according to claim 1, wherein the shape of the emitter is a conical shape, a truncated cone shape, or a truncated polygonal shape. 12. The cold electron-emitting device according to claim 1, wherein the insulating substrate is a glass substrate. 13. The method for manufacturing a cold electron emission device according to claim 2, wherein: (a) forming a metal thin film layer on an insulating substrate, and patterning the metal thin film layer by photolithography. Forming a first conductive layer and a second conductive layer simultaneously so as not to directly contact each other, and then sequentially forming a semiconductor thin film material layer, a gate insulating material layer, and a third conductive material layer; b) patterning by a photolithography method to form a third conductive layer, and then sequentially patterning by a photolithography method to form a gate insulating layer and a semiconductor thin film layer and leave a resist layer; (c) at least An emitter material layer on the second conductive layer,
(D) patterning the etching mask material layer into holes having a shape corresponding to the opening diameter of the gate by photolithography to form an etching mask layer, and forming the emitter by reactive ion etching. Forming an emitter by etching the material until the first conductive layer is exposed; and (e) an insulating material and a gate on the semiconductor thin film layer by anisotropic vapor deposition perpendicular to the insulating substrate. Depositing the electrode material in a self-aligned manner, peeling off the etching mask layer, peeling off the insulating material layer and the gate electrode material on the emitter, forming the insulating layer and the gate electrode, and photolithography of the insulating layer and the gate electrode Patterning to form an insulating layer, and at the same time, a resist layer and an insulating material on the resist layer and A manufacturing method comprising a step of peeling off together with a gate electrode material. 14. The step (a) wherein at least the semiconductor thin film material layer is a hydrogenated amorphous silicon layer formed by a plasma enhanced CVD method.
The manufacturing method of the cold electron-emitting device according to the above. 15. The method according to claim 1, wherein in the step (a), the semiconductor thin film layer is a polysilicon layer formed by performing an annealing process after forming an amorphous silicon film by a thermal CVD method or a plasma enhanced CVD method.
4. The method for manufacturing a cold electron-emitting device according to item 3. 16. The method according to claim 13, wherein in step (c), the emitter material is non-single-crystal silicon. 17. The method according to claim 13, wherein in step (c), the emitter material is amorphous silicon. 18. In the step (a), after forming a metal thin film layer on an insulating substrate, an ohmic layer is subsequently formed, and the metal thin film layer and the ohmic layer are patterned by photolithography. 14. The method for manufacturing a cold electron emitting device according to claim 13, wherein the first conductive layer and the second conductive layer are simultaneously formed. 19. The method according to claim 18, wherein in the step (a), the ohmic layer is an n-type hydrogenated amorphous silicon layer formed by a plasma enhanced CVD method using at least a mixed gas of silane and phosphine as a reaction gas. A method for manufacturing a cold electron-emitting device. 20. In the step (b), after sequentially forming a gate insulating layer and a semiconductor thin film layer by patterning by photolithography, forming a protective layer material and patterning by photolithography to form a protective layer. A method for manufacturing a cold electron-emitting device according to claim 20. 21. In the step (b), the protective layer material comprises:
14. The method for manufacturing a cold electron-emitting device according to claim 13, which is a silicon nitride layer or a silicon oxide layer formed by a plasma enhanced CVD method. 22. The method of manufacturing a cold electron emission device according to claim 2, wherein: (a ′) forming a metal thin film layer on an insulating substrate, and patterning the metal thin film layer by photolithography. Forming a first conductive layer and a second conductive layer simultaneously so as not to directly contact each other, and subsequently forming a semiconductor thin film layer, an emitter material, and an etching mask material layer sequentially; (b ') etching The mask material layer is patterned by photolithography into holes having a shape corresponding to the opening diameter of the gate to form an etching mask layer, and the emitter is etched by reactive ion etching until the semiconductor thin film layer is exposed. (C ') forming an insulating layer material and a gate electrode on the semiconductor thin film layer by anisotropic vapor deposition in a direction perpendicular to the insulating substrate; (D ') peeling off the etching mask layer and simultaneously peeling off the insulating material layer and the gate electrode material on the emitter;
Forming an insulating layer and a gate electrode; and (e ') patterning the insulating layer and the gate electrode by photolithography to form a gate insulating layer, and subsequently forming a third conductive layer by a lift-off method. A production method comprising a step. 23. The method according to claim 22, wherein in the step (a ′), the semiconductor thin film layer and the emitter material are a hydrogenated amorphous silicon layer formed by a plasma enhanced CVD method. 24. The method according to claim 22, wherein in the step (a ′), the emitter material is amorphous silicon. 25. In the step (a ′), the emitter material is n-type hydrogenated amorphous silicon formed by a plasma enhanced CVD method using at least a mixed gas of silane and phosphine as a reaction gas.
3. The method for manufacturing a cold electron-emitting device according to item 2. 26. The method according to claim 26, wherein in the step (a ′), the semiconductor thin film layer is a polysilicon layer formed by performing an annealing process after forming an amorphous silicon film by a thermal CVD method or a plasma enhanced CVD method. 2
3. The method for manufacturing a cold electron-emitting device according to item 2. 27. In the step (a ′), after forming a metal thin film layer on an insulating substrate, subsequently forming an ohmic layer, and patterning the metal thin film layer and the ohmic layer by photolithography. 23. The method according to claim 22, wherein the first conductive layer and the second conductive layer are formed at the same time. 28. The method according to claim 27, wherein in the step (a ′), the ohmic layer is an n-type hydrogenated amorphous silicon layer formed by a plasma enhanced CVD method using at least a mixed gas of silane and phosphine as a reaction gas. The method for manufacturing a cold electron-emitting device of the present invention. 29. The method for manufacturing a cold electron emission device according to claim 2, comprising: (a ″) forming a metal thin film layer on an insulating substrate, and patterning the metal thin film layer by photolithography. The first conductive layer and the second conductive layer are simultaneously formed so as not to directly contact each other, and subsequently, a semiconductor thin film layer, a gate insulating material, and a third conductive material are sequentially formed and patterned by photolithography. Forming a third conductive layer by photolithography, and further patterning by photolithography to form a gate insulating layer; (b ″) forming an emitter material and an etching mask material layer sequentially, An etching mask layer is formed by patterning holes with a shape corresponding to the opening diameter of the gate by photolithography, and reactive ion etching is used. The emitter material insulating layer or the first
(C ″) an insulating layer material and a gate electrode material are formed on the semiconductor thin film layer by anisotropic vapor deposition in a direction perpendicular to the insulating substrate; (D ″) a step of forming an insulating layer and a gate electrode by peeling off the etching mask layer and simultaneously removing an insulating material and a gate electrode material on the emitter; and (e ″). A method comprising: patterning an insulating layer and a gate electrode by photolithography to expose a third conductive layer and a gate insulating layer. 30. In the step (a ″), the semiconductor thin film layer and the emitter material are hydrogenated amorphous silicon formed by a plasma enhanced CVD method.
10. The method for manufacturing a cold electron emitting device according to item 9. 31. The method according to claim 29, wherein in the step (a ″), the emitter material is amorphous silicon. 32. In the step (a ″), the emitter material is n-type hydrogenated amorphous silicon formed by a plasma enhanced CVD method using a mixed gas of at least silane and phosphine as a reaction gas.
10. The method for manufacturing a cold electron emitting device according to item 9. 33. In the step (a ″), the semiconductor thin film layer is a polysilicon layer formed by forming an amorphous silicon film by a thermal CVD method or a plasma enhanced CVD method and then performing an annealing process. 2
10. The method for manufacturing a cold electron emitting device according to item 9. 34. The method according to claim 29, wherein in the step (a ″), the gate insulating material is a silicon nitride layer or a silicon oxide formed by a plasma enhanced CVD method. 35. In a step (a ″), after forming a metal thin film layer on an insulating substrate, subsequently forming an ohmic layer, and patterning the metal thin film layer and the ohmic layer by photolithography. 30. The method according to claim 29, wherein the first conductive layer and the second conductive layer are simultaneously formed. 36. The step (a ″), wherein the ohmic layer is an n-type hydrogenated amorphous silicon layer formed by a plasma enhanced CVD method using at least a mixed gas of silane and phosphine as a reaction gas. The method for manufacturing a cold electron-emitting device of the present invention. 37. The method for manufacturing a cold electron emission device according to claim 3, wherein: (f) forming a metal thin film layer on an insulating substrate, and patterning the metal thin film layer by photolithography. Forming a conductive layer of No. 3 and then sequentially forming a gate insulating layer, a semiconductor thin film layer and a metal thin film layer; (g) patterning the metal thin film layer by photolithography to form a first conductive layer and Forming a resist layer at least over a gap between the first conductive layer and the second conductive layer by photolithography after forming the second conductive layers simultaneously so as not to directly contact each other; (h) an emitter material; An etching mask material layer is sequentially formed, and the etching mask material layer is patterned into holes having a shape corresponding to the opening diameter of the gate by a photolithography method. Forming a layer and etching the emitter material by reactive ion etching until the insulating layer or the first conductive layer is exposed to form an emitter; (i) anisotropy perpendicular to the insulating substrate A step of forming an insulating layer material and a gate electrode material at least on the second conductive layer in a self-aligned manner by vapor deposition; and After the insulating layer and the gate electrode are formed, the insulating layer material and the gate electrode material are further patterned by photolithography to form the insulating layer and the gate electrode. A step of removing the insulating material and the gate electrode material. 38. The method according to claim 37, wherein in the step (f), the semiconductor thin film layer material is hydrogenated amorphous silicon formed by a plasma enhanced CVD method. 39. The method according to claim 37, wherein in step (h), the emitter material is amorphous silicon. 40. In the step (h), the emitter material is n-type hydrogenated amorphous silicon formed by a plasma enhanced CVD method using at least a mixed gas of silane and phosphine as a reaction gas.
The manufacturing method of the cold electron-emitting device according to the above. 41. In the step (f), the semiconductor thin film layer is a polysilicon layer formed by forming an amorphous silicon film by a thermal CVD method or a plasma enhanced CVD method and then performing an annealing treatment.
8. The method for manufacturing a cold electron-emitting device according to claim 7. 42. The method according to claim 37, wherein in the step (f), the gate insulating layer is a silicon nitride layer or a silicon oxide formed by a plasma enhanced CVD method. 43. In a step (f), after forming a semiconductor thin film layer material on the gate insulating layer, an ohmic layer is subsequently formed, and in the step (g), the metal thin film layer and the ohmic layer are 38. The method according to claim 37, wherein the first conductive layer and the second conductive layer are simultaneously formed by patterning by a method. 44. The method according to claim 37, wherein in the step (f), the ohmic layer is an n-type hydrogenated amorphous silicon layer formed by a plasma enhanced CVD method using at least a mixed gas of silane and phosphine as a reaction gas. A method for manufacturing a cold electron-emitting device. 45. In the step (g), the first conductive layer and the second conductive layer are patterned by photolithography.
Are formed simultaneously so that they do not directly contact each other, then a protective film material is formed, and the protective film material is left by photolithography so as to remain at least in the gap between the first conductive layer and the second conductive layer. 38. The method for manufacturing a cold electron emitting device according to claim 37, wherein the forming is performed. 46. In the step (g), the protective layer material comprises:
38. The method for manufacturing a cold electron-emitting device according to claim 37, wherein the cold electron-emitting device is a silicon nitride layer or a silicon oxide layer formed by a plasma enhanced CVD method.