KR20010003752A - Method of manufacturing field emission display device - Google Patents

Method of manufacturing field emission display device Download PDF

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Publication number
KR20010003752A
KR20010003752A KR1019990024183A KR19990024183A KR20010003752A KR 20010003752 A KR20010003752 A KR 20010003752A KR 1019990024183 A KR1019990024183 A KR 1019990024183A KR 19990024183 A KR19990024183 A KR 19990024183A KR 20010003752 A KR20010003752 A KR 20010003752A
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South Korea
Prior art keywords
film
etching
forming
display device
field emission
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KR1019990024183A
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Korean (ko)
Inventor
윤석신
김병진
김정근
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김영환
현대전자산업 주식회사
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Priority to KR1019990024183A priority Critical patent/KR20010003752A/en
Publication of KR20010003752A publication Critical patent/KR20010003752A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/022Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/304Field-emissive cathodes
    • H01J1/3042Field-emissive cathodes microengineered, e.g. Spindt-type

Abstract

PURPOSE: A method for fabricating a field emission display device is provided to simplify a process and to improve uniformity of a film by forming a gate electrode layer and an insulating film with a sputtering process. CONSTITUTION: A method for fabricating a field emission display device comprises the steps of: forming a protrusion by etching a silicone substrate(10) using a tip shaping mask; forming a first oxidation film(11) by performing a thermal oxidation of the silicone substrate and forming an emitter tip(10B) using the protrusion simultaneously; forming a second oxidation film(12) and a gate metal film on a top face of the first oxidation film; forming a gate electrode layer(13A,13B) by etching the gate metal film to expose the second oxidation film; exposing the emitter tip by etching the first and second oxidation films. The etching of the silicone substrate is achieved in isotropic manner. The second oxidation film is formed by a chemical vapor deposition. The gate metal film is formed using a sputtering process.

Description

전계방출 표시소자의 제조방법{Method of manufacturing field emission display device}Method of manufacturing field emission display device

본 발명은 전계방출 표시소자의 제조방법에 관한 것으로, 특히 공정을 단순화시키고 대면적화에 적용할 수 있는 전계방출 표시소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field emission display device, and more particularly, to a method for manufacturing a field emission display device that can be applied to simplify the process and to increase the area.

일반적으로 전계방출 표시소자(Field Emission Display ; FED)는 FEA(field emission array)를 매트릭스-어드세스할 수 있고, CRT와 같이 전자빔으로 형광체를 자극하여 음극선 발광을 일으키는 원리를 이용한 표시기이다. 또한, FED는 액정 표시 장치(liquid crystal display; LCD) 및 CRT와는 달리 평판과 해상도를 동시에 실현할 수 있을 뿐만 아니라 해상도 및 시약각이 우수한 정점이 있다.In general, a field emission display (FED) is a display using a principle of matrix-accessing a field emission array (FEA) and generating cathode ray emission by stimulating a phosphor with an electron beam like a CRT. In addition, unlike a liquid crystal display (LCD) and a CRT, the FED not only realizes a flat plate and a resolution at the same time, but also has a vertex having excellent resolution and reagent angle.

이러한 FED는 캐소드판과 애노드판과, 그들 사이에 스페이서가 개재된다. 또한, 캐소드판에는 게이트 전극과 전자를 방출하는 수개의 에미터팁(emitter tip)이 구비되어 FEA가 형성되고, 애노드판에는 ITO(indium tin oxide) 전극과 형광체가 구비되어 전계방출 표시장치의 컬러화를 실현한다.This FED has a cathode plate and an anode plate, and a spacer is interposed therebetween. In addition, the cathode plate is provided with a gate electrode and several emitter tips for emitting electrons to form FEA. The anode plate is provided with an indium tin oxide (ITO) electrode and a phosphor to colorize the field emission display device. To realize.

한편, 전계방출 표시소자의 밝기를 결정하는 에미터 팁은 게이트 전극 층에 소정의 홀을 형성한 다음, 그 홀 내부에 금속 또는 실리콘을 원추형태로 증착하여 형성한다.On the other hand, the emitter tip for determining the brightness of the field emission display device is formed by forming a predetermined hole in the gate electrode layer, and then depositing a metal or silicon in the hole in the shape of a cone.

그러나, 상기한 바와 같은 원추형의 에미터팁을 형성하기 위해서는 많은 마스크 공정이 요구될 뿐만 아니라 게이트 전극층 및 절연막과 같은 막들을 대부분 전자빔 증착(E-beam evaporation) 장비를 이용하여 증착하기 때문에 대면적 표시 소자에 적용하는데 어려움이 있다.However, in order to form a conical emitter tip as described above, not only a large number of mask processes are required but also a large area display device is deposited by using an electron beam evaporation (E-beam evaporation) equipment. Difficult to apply to

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 공정을 단순화시키고 대면적화에 적용할 수 있는 전계방출 표시소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a field emission display device which can solve the above-mentioned problems and can be applied to simplify the process and increase the area.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 전계방출 표시소자의 제조방법을 설명하기 위한 단면도.1A to 1F are cross-sectional views illustrating a method of manufacturing a field emission display device according to an exemplary embodiment of the present invention.

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

10 : 실리콘 기판 10B : 에미터팁10: silicon substrate 10B: emitter tip

11 : 제 1 산화막 12 : 제 1 산화막11: first oxide film 12: first oxide film

13 : 게이트용 금속막 13A, 13B : 게이트 전극층13 gate metal film 13A, 13B: gate electrode layer

100 : 제 1 포토레지스트막 패턴100: first photoresist film pattern

상기한 목적을 달성하기 위하여, 본 발명에 따라 도핑된 실리콘 기판을 팁형성용 마스크를 이용하여 식각하여 돌출부를 형성하고, 돌출부가 구비된 실리콘 기판을 열산화하여 제 1 산화막을 형성함과 동시에 돌출부를 에미터팁으로 형성한다. 그런 다음, 제 1 산화막 상부에 제 2 산화막 및 게이트용 금속막을 형성하고, 게이트용 금속막을 게이트용 마스크를 이용하여 에미터팁 상부의 제 2 산화막이 노출되도록 식각하여 게이트 전극층을 형성한다. 그리고 나서, 게이트 전극층을 식각 마스크로하여 제 2 및 제 1 산화막을 식각하여 에미터팁을 노출시킨다.In order to achieve the above object, according to the present invention, the doped silicon substrate is etched using a mask for forming a tip to form protrusions, and the silicon substrate having the protrusions is thermally oxidized to form a first oxide film and at the same time, the protrusions. Form an emitter tip. Next, a second oxide film and a gate metal film are formed on the first oxide film, and the gate metal film is etched using the gate mask to expose the second oxide film on the emitter tip to form a gate electrode layer. Then, the second and first oxide films are etched using the gate electrode layer as an etching mask to expose the emitter tip.

본 실시예에서, 실리콘 기판의 식각은 등방성 식각으로 진행하고, 제 2 산화막은 화학기상증착으로 형성하고, 게이트 금속막은 스퍼터링으로 형성한다.In this embodiment, the etching of the silicon substrate proceeds by isotropic etching, the second oxide film is formed by chemical vapor deposition, and the gate metal film is formed by sputtering.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 전계방출 표시소자의 제조방법을 설명하기 위한 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a field emission display device according to an exemplary embodiment of the present invention.

도 1a를 참조하면, 실리콘 기판(10)에 POCl3를 도핑하고 웰 드라이브-인을 수행하여 실리콘 기판(10)을 도핑한 후, 실리콘 기판(10) 상부에 팁형성용 제 1 마스크를 이용하여 제 1 포토레지스트막 패턴(100)을 형성한다. 그런 다음, 제 1 포토레지스트막 패턴(100)을 식각 마스크로하여 실리콘 기판(10)을 등방성 식각하여 돌출부(10A)를 형성하고, 도 1b에 도시된 바와 같이, 공지된 방법으로 제 1 포토레지스트막 패턴(100)을 제거하여 돌출부(10A)를 노출시킨다.Referring to FIG. 1A, after doping POCl 3 to a silicon substrate 10 and performing a well drive-in to dope the silicon substrate 10, a tip forming first mask is formed on the silicon substrate 10. The first photoresist film pattern 100 is formed. Then, the silicon substrate 10 isotropically etched using the first photoresist film pattern 100 as an etch mask to form the protrusions 10A, and as shown in FIG. 1B, the first photoresist in a known manner. The film pattern 100 is removed to expose the protrusion 10A.

도 1c를 참조하면, 돌출부(10A)가 구비된 실리콘 기판(10)의 표면을 열산화(thermal oxidation)하여 제 1 절연막으로서 제 1 산화막(11)을 형성함과 동시에 에미터팁(10B)을 형성한다. 즉, 제 1 산화막(11)은 실리콘 기판(10)의 표면 하부에서 약 45% 정도 형성되고, 표면 상부에서 약 55% 정도 형성된다. 이에 따라, 돌출부(10A)의 표면이 뾰족해진다.Referring to FIG. 1C, the surface of the silicon substrate 10 having the protrusion 10A is thermally oxidized to form the first oxide film 11 as the first insulating film and the emitter tip 10B. do. That is, about 45% of the first oxide film 11 is formed under the surface of the silicon substrate 10 and about 55% is formed above the surface. As a result, the surface of the protrusion 10A becomes sharp.

도 1d에 도시된 바와 같이, 제 1 산화막(11) 상부에 제 2 절연막으로서 제 2 산화막(12)을 형성하고, 그 상부에 게이트용 금속막(13)을 형성한다. 바람직하게, 제 2 산화막(12)은 화학기상증착(Chemical Vapor Deposition; CVD)로 형성하고, 게이트용 금속막(13)은 Mo막을 스퍼터링 방식으로 증착하여 형성한다. 여기서, 제 1 및 제 2 산화막(11, 12)는 캐소드 라인(미도시)과 이후 형성될 게이트 전극층을 서로 절연시킨다.As shown in FIG. 1D, the second oxide film 12 is formed as the second insulating film on the first oxide film 11, and the gate metal film 13 is formed thereon. Preferably, the second oxide film 12 is formed by Chemical Vapor Deposition (CVD), and the gate metal film 13 is formed by depositing an Mo film by sputtering. Here, the first and second oxide films 11 and 12 insulate the cathode line (not shown) from the gate electrode layer to be formed later.

도 1e를 참조하면, 게이트용 금속막(13) 상에 게이트용 마스크를 이용하여 제 2 포토레지스트막 패턴(미도시)을 형성하고, 상기 제 2 포토레지스트막 패턴을 식각 마스크로하여 게이트용 금속막(13)을 식각하여 에미터팁(10B) 상부의 제 2 산화막(12)을 노출시키는 게이트 전극층(13A, 13B)을 형성한다. 그리고 나서, 공지된 방법으로 제 2 포토레지스트막 패턴을 제거하고, 도 1f에 도시된 바와 같이, 게이트 전극층(13A, 13B)를 식각 마스크로하여 제 2 및 제 1 산화막(12, 11)을 식각하여 에미터팁(10B)을 노출시킨다.Referring to FIG. 1E, a second photoresist film pattern (not shown) is formed on the gate metal film 13 using a gate mask, and the gate metal is formed by using the second photoresist film pattern as an etching mask. The film 13 is etched to form gate electrode layers 13A and 13B exposing the second oxide film 12 on the emitter tip 10B. Then, the second photoresist film pattern is removed by a known method, and the second and first oxide films 12 and 11 are etched using the gate electrode layers 13A and 13B as an etching mask, as shown in FIG. 1F. To expose the emitter tip 10B.

상기한 본 발명에 의하면, 에미터팁 및 게이트용 마스크의 2개의 마스크를 이용하고, 전자빔 증착장비를 이용하는 것 없이, 스퍼터를 이용하여 게이트 전극층을 형성하고, 열산화 및 스퍼터링을 이용하여 산화막과 같은 절연막을 형성하기 때문에, 공정이 단순해질 뿐만 아니라 막 표면이 균일해지고, 대면적 표시에 적용하는 것이 가능해진다.According to the present invention described above, the gate electrode layer is formed by using a sputter without using two masks of an emitter tip and a gate mask and using an electron beam deposition apparatus, and an insulating film such as an oxide film using thermal oxidation and sputtering. In addition, not only the process is simple but also the surface of the film becomes uniform, and it is possible to apply to large-area display.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (4)

도핑된 실리콘 기판을 팁형성용 마스크를 이용하여 식각하여 돌출부를 형성하는 단계;Etching the doped silicon substrate using a tip forming mask to form protrusions; 상기 돌출부가 구비된 실리콘 기판을 열산화하여 제 1 산화막을 형성함과 동시에 상기 돌출부를 에미터팁으로 형성하는 단계;Thermally oxidizing the silicon substrate having the protrusion to form a first oxide film and simultaneously forming the protrusion as an emitter tip; 상기 제 1 산화막 상부에 제 2 산화막 및 게이트용 금속막을 형성하는 단계;Forming a second oxide film and a gate metal film on the first oxide film; 상기 게이트용 금속막을 게이트용 마스크를 이용하여 상기 에미터팁 상부의 상기 제 2 산화막이 노출되도록 식각하여 게이트 전극층을 형성하는 단계; 및Etching the gate metal layer to expose the second oxide layer on the emitter tip by using a gate mask to form a gate electrode layer; And 상기 게이트 전극층을 식각 마스크로하여 상기 제 2 및 제 1 산화막을 식각하여 상기 에미터팁을 노출시키는 단계를 포함하는 것을 특징으로 하는 전계방출 표시소자의 제조방법.And etching the second and first oxide layers using the gate electrode layer as an etch mask to expose the emitter tips. 제 1 항에 있어서, 상기 실리콘 기판의 식각은 등방성 식각으로 진행하는 것을 특징으로 하는 전계방출 표시소자의 제조방법.The method of claim 1, wherein the etching of the silicon substrate is performed by isotropic etching. 제 1 항에 있어서, 상기 제 2 산화막은 화학기상증착으로 형성하는 것을 특징으로 하는 전계방출 표시소자의 제조방법.2. The method of claim 1, wherein the second oxide film is formed by chemical vapor deposition. 제 1 항에 있어서, 상기 게이트 금속막은 스퍼터링으로 형성하는 것을 특징으로 하는 전계방출 표시소자의 제조방법.The method of manufacturing a field emission display device according to claim 1, wherein the gate metal film is formed by sputtering.
KR1019990024183A 1999-06-25 1999-06-25 Method of manufacturing field emission display device KR20010003752A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100438835B1 (en) * 2001-12-18 2004-07-05 삼성에스디아이 주식회사 Method of manufacturing a floated structure from a substrate and floated gate electrode and Field Emission Device adopting the same

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Publication number Priority date Publication date Assignee Title
KR920008961A (en) * 1990-10-30 1992-05-28 오가 노리오 Field emission emitter and method of manufacturing the same
JPH08321255A (en) * 1995-03-20 1996-12-03 Nec Corp Field emission cold cathode and its manufacture
KR19980019609A (en) * 1996-09-02 1998-06-25 양승택 Field emission device manufacturing method
KR19980019610A (en) * 1996-09-02 1998-06-25 양승택 Field emission device manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920008961A (en) * 1990-10-30 1992-05-28 오가 노리오 Field emission emitter and method of manufacturing the same
JPH08321255A (en) * 1995-03-20 1996-12-03 Nec Corp Field emission cold cathode and its manufacture
KR19980019609A (en) * 1996-09-02 1998-06-25 양승택 Field emission device manufacturing method
KR19980019610A (en) * 1996-09-02 1998-06-25 양승택 Field emission device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100438835B1 (en) * 2001-12-18 2004-07-05 삼성에스디아이 주식회사 Method of manufacturing a floated structure from a substrate and floated gate electrode and Field Emission Device adopting the same

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