JPH1154025A - Cold electron emitting element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cold electron emitting element of an electric field radiating type, which can reduce electric current fluctuation to its minimum limit while suppressing a local big current without raising an actuating voltage, and can realize a low cost and a large area easily. SOLUTION: On a base board 1 of this element, a semiconductor thin film layer 2, an insulating layer 3 and a gate electrode 4 are laminated in order, and an emitter 5 is made in an opening part A provided in the gate electrode 4 and the insulating layer 3 so as not touch the gate 4. In this case, a T F T structure, which has the emitter 5 as a drain, a first conductive layer 6 as a source and the semiconductor thin film between them as a channel, is made, by using non-single crystal silicon for the emitter 5 and forming the first conductive layer 6 so as not to touch the emitter 5 on the same plane on the semiconductor thin film layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a field emission type cold electron emitting device that emits cold electrons by a strong electric field and a method of manufacturing the same. More specifically, as an electron source or electron gun such as an optical printer, an electron microscope, an electron beam exposure device, or as a micro illumination source of an illumination lamp,
Array-like FEA (Field E
The present invention relates to a cold electron emission element useful as an electron source of a mitter array and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube has been widely used as an electronic display device. However, the cathode ray tube consumes a large amount of energy to emit thermoelectrons from a cathode of an electron gun, and is structurally large. There were problems such as requiring a volume.

[0003] For this reason, there has been a demand for a flat display in which cold electrons can be used instead of thermoelectrons, thereby reducing the energy consumption as a whole and further reducing the size of the device itself. There is also a strong demand for such a flat display to realize high-speed response and high resolution.

As a structure of such a flat display utilizing cold electrons, a structure in which minute cold electron-emitting devices are arranged in an array in a flat plate cell in a high vacuum is considered to be promising. As a cold electron-emitting device used therefor, a field-emission cold electron-emitting device utilizing a field emission phenomenon has been receiving attention. In this field emission type cold electron-emitting device, when the intensity of an electric field applied to a substance is increased, the width of an energy barrier on the surface of the substance is gradually reduced according to the intensity,
When the electric field intensity becomes a strong electric field of 10 ⁷ V / cm or more, electrons in a substance can break through the energy barrier by a tunnel effect, and the phenomenon that electrons are emitted from the substance is used. In this case, since the electric field complies with Poisson's equation, if a portion where the electric field is concentrated is formed on a member (emitter) that emits electrons, cold electrons can be efficiently emitted with a relatively low extraction voltage.

As a general example of such a field emission type cold electron emitting device, a conical cold electron emitting device having a sharp tip as shown in FIG. 5 can be exemplified. In this device, a conductive layer 52, an insulating layer 53, and a gate electrode 54 are sequentially laminated on an insulating substrate 51, and an opening A reaching the conductive layer 52 is formed in the insulating layer 53 and the gate electrode 54. Have been. And the opening A
A conical emitter 55 having a point-like projection Po is formed on the conductive layer 52 in such a manner as not to contact at least the gate electrode 54.

Among such conical emitters, Spindt-type emitters are widely known.

An example of manufacturing a cold electron emitting device having a Spindt-type emitter will be described with reference to FIGS. 6 (a) to 6 (d).

First, as shown in FIG. 6A, an insulating layer 63 and a gate electrode 64 are sequentially formed on an insulating substrate 61 on which a conductive layer 62 has been formed by sputtering or vacuum evaporation. . Subsequently, the insulating layer 6 is formed using photolithography and reactive ion etching (RIE).
3 and a part of the gate electrode 64 are etched such that a circular hole (gate hole) is opened until the conductive layer 62 is exposed.

Next, as shown in FIG. 6B, a lift-off material 65 is formed only on the upper surface and side surfaces of the gate electrode 64 by oblique evaporation. The material of the lift-off material 65 is A
1, MgO and the like are often used.

Subsequently, as shown in FIG. 6C, a metal material for the emitter 66 is deposited on the conductive layer 62 by a normal anisotropic deposition from a perpendicular direction. At this time,
As the deposition proceeds, the conical emitter 66 is formed on the conductive layer 62 in a self-aligned manner at the same time as the opening diameter of the gate hole is reduced. The vapor deposition is performed until the gate hole is finally closed. As a material of the emitter, Mo, Ni, or the like is used.

Finally, as shown in FIG. 6D, the lift-off material 65 is peeled off by etching, and the gate electrode 64 is patterned if necessary. Thus, a cold electron emitting device having a Spindt-type emitter is obtained.

The cold electron emission device having such a Spindt-type emitter has the advantages that a conical emitter can be easily formed in a self-aligned manner by anisotropic vapor deposition, and that the material of the emitter can be selected over a wide range. Have.

When a cold electron emitting device utilizing a fine processing technique represented by a Spindt-type emitter is applied to a flat display or the like in particular, a small fluctuation of the emission current from the emitter is required to obtain a high quality image. Is essential.

The fluctuation of the emission current can be reduced to some extent by integrating the emitter.
This is because the effect of variations in emission characteristics of individual emitters is reduced by integration. However, in this method, the emission current from each emitter is merely averaged, so that it is impossible to suppress an abnormally large emission current that appears locally.

As a means for reducing such a variation in emission current, US Pat. No. 3,787,471 discloses a technique in which a resistive layer is provided between a conductive layer and an emitter in a Spindt-type emitter.

An example of the configuration of a cold electron emission device having such a resistance layer will be described with reference to FIG.

A conductive layer 72 and a resistance layer 7 are formed on an insulating substrate 71.
3, an insulating layer 74 and a gate electrode 75 are sequentially laminated, and the insulating layer 74 and the gate electrode 75
An opening A reaching 3 is formed. Then, at least the gate electrode 7 is provided on the resistance layer 73 in the opening A.
A conical emitter 76 is formed so as not to come into contact with 5.

In this case, the resistance layer 73 is electrically inserted between the conductive layer 72 and the emitter 76 in series. The resistance layer 73 provides an effect of equalizing the current between the elements, and further reduces a large current that may lead to element destruction, and also reduces a variation in emission current in proportion to the resistance value of the resistance layer 73. It becomes possible. It is appropriate that the specific resistance of the resistance layer 73 is 10 ² to 10 ⁶ Ω · cm.

On the other hand, a silicon emitter to which a semiconductor integrated circuit manufacturing technology is applied is also widely known (Tech. Dig. IV).
MC., (1991) p26).

An example of manufacturing a cold electron-emitting device having a silicon emitter will be described with reference to FIGS.

First, as shown in FIG. 8A, a single crystal silicon substrate 81 is thermally oxidized to form a silicon oxide layer on the surface, and the silicon oxide layer is patterned into a circular shape by using photolithography. Thus, a circular silicon oxide layer 82 for an etching mask is formed. This silicon oxide layer 82 also functions as a lift-off material as described later. Note that the diameter of the silicon oxide layer 82 substantially corresponds to the gate diameter.

Next, as shown in FIG. 8B, the reactive ion etching method (R
The emitter 83 is formed by etching the silicon substrate 81 by IE).

Subsequently, as shown in FIG. 8C, a silicon oxide layer 84 for sharpening the tip of the emitter is formed on the surfaces of the silicon substrate 81 and the emitter 83 by thermal oxidation. Due to the stress generated when the silicon oxide layer 84 is formed, the tip of the emitter 83 inside the silicon oxide layer 84 is easily sharpened.

Then, as shown in FIG. 8D, an insulating layer 85 and a gate electrode 86 are laminated by anisotropic vapor deposition.

Finally, as shown in FIG. 8E, the silicon oxide layer 82 for the etching mask, which also functions as a lift-off material, is lifted off by etching, and the silicon oxide layer 84 on the surface of the emitter 83 is removed by etching. . Then, the gate electrode 86 is patterned as necessary. Thereby, a cold electron emission device having a silicon emitter is obtained.

More recently, in silicon emitters,
It has been shown that advanced current control is possible using the properties of silicon as a semiconductor (Jpn.J. Appl.Phys.v.
ol. 35 (1996) p6637). A silicon emitter equipped with such a current control function is called a MOSFET structure emitter. The configuration of the cold electron-emitting device having the MOSFET structure emitter will be described with reference to FIG.

On the same plane of the p-type silicon substrate 91, n
An emitter wiring layer 94 is provided via a conical emitter 92 of n-type silicon and an n-type silicon layer 93, and a gate electrode 96 is provided between the emitter 92 and the emitter wiring layer 94 via an insulating layer 95. . That is, in this emitter, a MOSFET (metal-oxide-semiconductor field
-effect-transistor) structure in the cold electron-emitting device.
The source and emitter 92 of the OSFET function as a drain, the gate electrode 96 functions as a gate, and the insulating layer 95 functions as a gate insulating film.

An example of manufacturing a cold electron emitting device having a MOSFET structure emitter will be described with reference to FIGS.

First, as shown in FIG. 10A, a single-crystal p-type silicon substrate 101 is thermally oxidized to form a silicon oxide layer (not shown) on the surface, and the silicon oxide layer is formed by photolithography. The silicon oxide layer 102 for a circular etching mask is formed by performing circular patterning using This silicon oxide layer 102 also functions as a lift-off material as described later. Note that the diameter of the silicon oxide layer 102 substantially corresponds to the gate diameter.

Next, as shown in FIG. 10B, the p-type silicon substrate 101 is etched by reactive ion etching (RIE) under a condition of a high side etch rate to form an emitter 103.

Subsequently, as shown in FIG. 10C, a silicon oxide layer 104 for sharpening the tip of the emitter and for the insulating layer is formed on the surfaces of the p-type silicon substrate 101 and the emitter 103 by thermal oxidation. The tip of the emitter 103 inside the silicon oxide layer 104 is easily sharpened by the stress generated when the silicon oxide layer 104 is formed.

Then, as shown in FIG. 10D, a gate electrode 105 is formed, and a circular hole pattern for the emitter wiring is formed on the gate electrode 105 by using photolithography.

Next, as shown in FIG. 10E, the silicon oxide layer 102 for an etching mask, which also functions as a lift-off material, is lifted off by etching, and the silicon oxide layer 104 on the surface of the emitter 103 is removed by etching. At the same time, an emitter wiring hole is formed.

Subsequently, as shown in FIG. 10F, diffusion annealing is performed after phosphorus is ion-implanted, and
3 is made n-type, and an n-type silicon layer 106 is formed on the surface of the emitter wiring hole.

Finally, as shown in FIG. 10 (g), after a metal thin film 107 such as aluminum is formed as an electrode material for the emitter wiring and the gate wiring, the gate electrode 105 is patterned as necessary. This allows MOSF
A cold electron emission device having an ET structure emitter is obtained.

In a cold electron emission device comprising a silicon emitter having such a MOSFET structure, although a MOS transistor can be easily manufactured in substantially the same manufacturing process as a conventional silicon emitter, a MOS transistor is built in the device. An extremely stable emission current controlled by a transistor can be obtained, and the generation of a local large current can be eliminated.

[0037]

However, in a cold electron emitting device provided with a resistance layer for stabilizing a current, a larger current reducing characteristic is required to obtain a sufficient current reduction characteristic with respect to a local large current. In addition to the necessity of providing a resistance, there has been a problem that the current fluctuation can be reduced only relative to the characteristics of the individual elements, and further, an increase in the operating voltage cannot be avoided in principle.

On the other hand, a MOSFE equipped with a current control function
In a silicon emitter having a T structure, a stable current at a very high level can be obtained by transistor control. However, since a single crystal silicon substrate is required, it is difficult to reduce the cost and increase the area. was there.

The present invention is intended to solve the above-mentioned problems of the prior art. By mounting a current control function on a device itself using a semiconductor thin film, a local large scale operation can be performed without increasing the operating voltage. It is an object of the present invention to provide a field emission type cold electron emitting element that can suppress current and reduce current fluctuation to a minimum, and can easily reduce cost and increase area by using a glass substrate or the like. .

[0040]

The inventor of the present invention has provided a semiconductor thin film layer on an insulating substrate, and a first conductive layer (emitter wiring layer) and non-single-crystal silicon on the same plane of the semiconductor thin film layer. Are formed without directly contacting each other, thereby forming a thin film transistor (TFT) structure including a source (first conductive layer), a drain (emitter) and a channel (semiconductor thin film layer) on a single crystal silicon substrate. They have found that they can be easily incorporated into an electron-emitting device without using them, and have completed the present invention.

That is, according to the present invention, an insulating layer and a gate electrode are sequentially laminated on an insulating substrate, an opening is provided in the gate electrode and the insulating layer, and an emitter is provided in the opening in the gate electrode. In a field emission type cold electron emission element formed so as not to contact, the material of the emitter is non-single-crystal silicon, and the first conductive layer is formed on an insulating substrate other than the opening, A semiconductor thin film layer is formed between the insulating substrate and the emitter and between the insulating substrate and the first conductive layer, and the emitter and the first conductive layer are in direct contact with each other on the same plane of the semiconductor thin film layer. Provided is a cold electron emission element characterized by being formed without performing.

In particular, when a plurality of the cold electron emitting elements described above are integrated to form a matrix array, a second conductive layer made of a metal thin film is provided between the emitter and the semiconductor thin film layer, and each emitter is connected to each other. Are preferably connected to each other.

The present invention also relates to a method for manufacturing a cold electron emitting device as described above: (a) After forming a semiconductor thin film layer and a metal thin film layer on an insulating substrate, the metal thin film layer is formed by photolithography. Patterning to form a first conductive layer, and then successively forming an emitter material layer and an etching mask material layer; (b) forming the etching mask material layer in a circular shape having a gate opening diameter by photolithography. Or forming a polygonal pattern and etching the emitter material layer by reactive ion etching until the semiconductor thin film layer is exposed while leaving the first conductive layer, thereby forming an emitter; An insulating layer material and a gate electrode material are formed on the semiconductor thin film layer by a vertical anisotropic vapor deposition method, and the insulating layer and the gate electrode are self-aligned. A step of forming; and (d) at the same time peeling off the etching mask layer, to provide a manufacturing method characterized by comprising the step of flaking the insulating layer material and the gate electrode material on the gate electrode.

In particular, when a plurality of the cold electron-emitting devices described above are integrated to form a matrix array, the first conductive layer is formed by patterning the metal thin film layer by photolithography in the step (a). When doing
At the same time, a second conductive layer is formed on the insulating substrate on which the emitter is to be formed, and in the step (b), the etching mask material layer is formed by photolithography into a circular or polygonal pattern having a gate opening diameter. Forming
The emitter material layer is formed by reactive ion etching.
It is preferable to form the emitter by etching until the semiconductor thin film layer is exposed while leaving the conductive layer and the second conductive layer.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1A is a cross-sectional view of the cold electron emitting device of the present invention. As shown in FIG. 1, the cold electron emission element has a structure in which a semiconductor thin film layer 2, an insulating layer 3, and a gate electrode 4 are sequentially stacked on an insulating substrate 1. And
An opening A (emitter hole) reaching the semiconductor thin film layer 2 is provided in the gate electrode 4 and the insulating layer 3, and the semiconductor thin film layer 2 in the opening A is made of non-single-crystal silicon. The conical or frustoconical emitter 5 is a gate electrode 4
It is formed so as not to contact with. Further, the first conductive layer 6 is provided on the semiconductor thin film layer 2 outside the opening A. In this case, as shown in FIG. 1A, a mode in which the insulating layer 3 and the gate electrode 4 are stacked on the first conductive layer 6 is preferable from the viewpoint of device integration. 3), the insulating layer 3 and the gate electrode 4 are formed on the first conductive layer 6.
May not be stacked.

In the present invention, the insulating substrate 1 is used as a supporting insulating substrate for a cold electron emitting device, and an insulating substrate that can be easily enlarged can be preferably used. As such an insulating substrate, a glass substrate, a ceramic substrate, a quartz substrate, or the like can be used.
Note that a substrate in which an insulating film is formed over the surface of single crystal silicon can also be used.

The semiconductor thin film layer 2 functions as a TFT channel. Such a semiconductor thin film layer 2 can be formed from a known material similar to a TFT widely used as a switching element of a liquid crystal display. For example, particularly when a glass substrate is used as the insulating substrate 1, hydrogenated amorphous silicon or polysilicon obtained by laser annealing can be used.

The thickness of the semiconductor thin film layer 2 is, for example, 0.2 μm so that it can operate as a TFT channel.
To 2 μm, preferably 0.3 to 0.7 μm.

The insulating layer 3 is a layer for electrically insulating the gate electrode 4 from the emitter 5 and the first conductive layer 6.
Further, they are used simultaneously to electrically insulate the semiconductor thin film layer 2 and the gate electrode 4. That is, it also functions as a TFT gate insulating film. Such an insulating layer 3 is desirably anisotropic vapor deposition in order to form it in a self-aligned manner, and is particularly preferably silicon oxide by a reactive chimney resistance heating vapor deposition method using a mixed gas of ozone and oxygen as a reaction gas. High insulation properties can be obtained.

The thickness of the insulating layer 3 may be such that sufficient insulation between the emitter 5, the first conductive layer 6, and the semiconductor thin film layer 2 and the gate electrode 4 is maintained. 2
μm, preferably 0.3 to 0.7 μm.

The gate electrode 4 is an electrode for concentrating a strong electric field on the emitter 5 and functions as a gate electrode of the TFT. As a material for the gate electrode 4, a material having a high melting point from the viewpoint of current resistance and having resistance to an etching solution used when forming the emitter 5 can be used, and preferably Cr, W, Ta, or Nb can be mentioned. Above all, it is preferable to use Nb from the viewpoint of adhesion to the base.

The thickness of the gate electrode 4 can be appropriately determined as needed, and is set to 0.1 to 0.5 μm.

The emitter 5 is a member that emits cold electrons directly from its surface, and is made of non-single-crystal silicon. Here, when the emitter 5 is made of non-single-crystal silicon, for example, polysilicon or amorphous silicon, more stable emission characteristics can be obtained because the emitter 5 itself has a certain degree of resistance.

The thickness (height) of the entire emitter 5 can be appropriately determined as required, and is usually 0.3 to 2 μm.
m is preferable.

The shape of the emitter 5 is preferably a cone or a cylinder, or a truncated cone or a truncated polygon.

The first conductive layer 6 functions as an emitter wiring layer and also functions as a source of the TFT. As a material of such a first conductive layer 6, a material having a low wiring resistance, a high adhesiveness to the underlying semiconductor thin film layer 2, and an ohmic contact is appropriate. Such a material is particularly preferably a Cr or Al, Cr laminated film. However, depending on the manufacturing method, the material may be the same as the material of the emitter 5, but in that case, a material that satisfies the required characteristics of both the emitter 5 and the first conductive layer 6 is used. Examples of such a material include a laminated film of the material of the emitter 5 and Al, Cu, and Au.

The thickness of the first conductive layer 6 is not particularly limited as long as sufficient wiring resistance and adhesion can be obtained, but is usually 0.05 to 2.0 μm, preferably 0.1 to 1.0 μm.
And

FIG. 2 is a sectional view of a cold electron emitting device according to another embodiment of the present invention. This cold electron emitting device has a second conductive layer 8 (emitter connection layer) made of a metal thin film between the emitter 5 and the semiconductor thin film layer 2 of the cold electron emitting device shown in FIG.
Is equivalent to the case where. By providing such a second conductive layer 8, when a plurality of electron-emitting devices are integrated into a matrix array structure, a plurality of emitters 5 can be electrically connected to each other. Current control can be performed on the emitters 5 at the same time.

Next, a method of manufacturing the cold electron-emitting device of the embodiment shown in FIG. 1A will be described with reference to FIG.

Step (a) First, a semiconductor thin film layer 2 made of non-single-crystal silicon or the like is formed on an insulating substrate 1 by a CVD method or the like.
After forming a metal thin film for the conductive layer 6 by vapor deposition or the like,
The first conductive layer 6 is formed by patterning by photolithography so as to realize a desired TFT channel length. Here, the non-single-crystal silicon as the material of the semiconductor thin film layer 2 is plasma enhanced (PE) C
Hydrogenated amorphous silicon formed by the VD method, or polysilicon formed by annealing an amorphous silicon film formed by the thermal CVD or PECVD method by, for example, laser annealing can be preferably used.

Further, an emitter material layer 5 'is formed.
Here, as a method for forming the emitter material layer 5 ', n-type hydrogenated amorphous silicon formed by PECVD using a mixed gas of silane or disilane and phosphine as a reaction gas is used. Subsequently, a silicon oxide film is formed as the etching mask layer 7 using a normal film forming method such as an evaporation method or a sputtering method. (FIG. 3A) Step (b) Next, a circular or polygonal pattern having a gate opening diameter is formed in the etching mask layer 7 by photolithography, and the emitter material layer 5 'is formed by reactive ion etching. Then, etching is performed until the semiconductor thin film layer 2 is exposed while leaving the first conductive layer 6, thereby forming the emitter 5. (FIG. 3B) Step (c) Subsequently, the insulating layer 3 and the gate electrode 4 are formed on the first conductive layer 6 by normal anisotropic vapor deposition from the perpendicular direction. At this time, it is desirable that the insulating layer 3 is formed by anisotropic vapor deposition in order to form the insulating layer 3 in a self-aligned manner.
For example, a silicon oxide film formed by a reactive chimney resistance heating evaporation method using a mixed gas of ozone and oxygen as a reaction gas is used. (FIG. 3C) Step (d) Finally, the etching mask layer 7 is peeled off by etching to form the insulating layer 3 and the gate electrode 4. The gate electrode 4 is patterned as needed. As a result, FIG.
(D), that is, the cold electron-emitting device shown in FIG.

A method of manufacturing the cold electron-emitting device of FIG. 2 having a plurality of emitters and having a matrix array structure will be described in detail with reference to FIG.

Step (a) First, a semiconductor thin film layer 2 made of non-single-crystal silicon or the like is formed on an insulating substrate 1 by a CVD method or the like.
After forming a metal thin film which also serves as the conductive layer 6 and the second conductive layer 8 by a vapor deposition method or the like, the first conductive layer 6 and the second conductive layer 8 correspond to the channel length of the TFT by a photolithography method. Patterning is performed with a gap provided. Here, non-single-crystal silicon as a material of the semiconductor thin film layer 2 includes:
Hydrogenated amorphous silicon formed by PECVD, or polysilicon formed by annealing an amorphous silicon film formed by thermal CVD or PECVD, for example, by laser annealing can be preferably used.

Further, an emitter material layer 5 'is formed.
Here, as a method for forming the emitter material layer 5 ', n-type hydrogenated amorphous silicon formed by PECVD using a mixed gas of silane or disilane and phosphine as a reaction gas is used. Subsequently, a silicon oxide film is formed as the etching mask layer 7 using a normal film forming method such as an evaporation method or a sputtering method. (FIG. 4A) Step (b) Next, a circular or polygonal pattern having a gate opening diameter is formed in the etching mask layer 7 by photolithography, and the emitter material layer 5 'is formed by reactive ion etching. The emitter 5 is formed by etching until the semiconductor thin film layer 2 is exposed while leaving the first conductive layer 6 and the second conductive layer 8. (FIG. 4B) Step (c) Subsequently, the insulating layer 3 and the gate electrode 4 are formed on the second conductive layer 8 by normal anisotropic vapor deposition from the perpendicular direction. At this time, it is desirable that the insulating layer 3 is formed by anisotropic vapor deposition in order to form the insulating layer 3 in a self-aligned manner.
For example, a silicon oxide film formed by a reactive chimney resistance heating evaporation method using a mixed gas of ozone and oxygen as a reaction gas is used. (FIG. 4C) Step (d) Finally, the etching mask layer 7 is peeled off by etching to form the insulating layer 3 and the gate electrode 4. The gate electrode 4 is patterned as needed. As a result, FIG.
(D), that is, the cold electron-emitting device of FIG. 2 is obtained.

As described above, the cold electron-emitting device according to the present invention does not use a single-crystal silicon
Since the T structure is formed in the element, an emission current highly controlled by the transistor can be obtained even on the insulating substrate, and matrix wiring can be easily realized.

[0067]

EXAMPLES The production examples of the cold electron-emitting device of the present invention will be specifically described in the following examples. Note that the first embodiment is different from the one shown in FIG.
(A) is a manufacturing example of the cold electron-emitting device of the embodiment shown in FIG. 2, and Example 2 is a manufacturing example of the cold electron-emitting device of the embodiment shown in FIG.

Example 1 Step (a) First, a PECV was formed as a semiconductor thin film layer 2 on an insulating substrate 1.
0.5μ of hydrogenated amorphous silicon film by D method
The film was formed with a thickness of m. Using silane gas as a reaction gas and hydrogen as a diluting gas, a total gas flow rate of 300 scc
m, gas pressure of 1 Torr, substrate temperature of 250 ° C., and RF power of 60 W.

Next, Al for the first conductive layer 6 was formed to a thickness of 0.1 μm by vapor deposition, and then patterned by photolithography. Subsequently, an n-type hydrogenated amorphous silicon film having a thickness of 0.8 μm was formed as the emitter material layer 5 ′ by PECVD. Silane gas and phosphine gas (dope concentration 3000)
ppm), hydrogen as a diluent gas, a total gas flow rate of 560 sccm, a gas pressure of 1 Torr, and a substrate temperature of 350
The film was formed under the conditions of C. and RF power of 60 W (FIG. 3).
(A)).

Step (b) Next, a circular pattern having a gate opening diameter of 1.2 μm is formed by using ordinary photolithography, and hydrogenated amorphous silicon as the emitter material layer 5 ′ is formed by reactive ion etching. While leaving one conductive layer 6,
The etching was performed until the semiconductor thin film layer 2 was exposed. The etching conditions at this time were (introduced gas: SF6 60 scc)
m / power 100 W / gas pressure 4.5 Pa) (FIG. 3B).

Step (c) Next, by anisotropic vapor deposition from the direction perpendicular to the substrate, silicon oxide as the insulating layer 3, Nb as the gate electrode 4, and a film of 0.6 μm and 0.2 μm, respectively. Thickness was deposited (FIG. 3 (c)).

Step (d) Next, the silicon oxide of the etching mask layer 7 was wet-etched using a buffered hydrofluoric acid solution and lifted off to obtain a cold electron-emitting device as shown in FIG.

The cold electron emission device described above was fabricated as a prototype, and the following tests were performed and evaluated. That is, the distance between the emitter and the gate electrode of each element is about 0.7 μm, and the emitter height is about 0.8 μm.
m, a glass plate member having a transparent electrode (anode) coated with a phosphor was placed at a distance of 3 from an element having a structure in which channel length L / channel width W was 10/1 as a TFT parameter.
When opposing at 0 mm and applying an extraction voltage between the emitter electrode and the gate electrode with a polarity where the gate electrode side was positive, cold electrons could be emitted satisfactorily and stably.

In the low electric field region, the current-voltage characteristic (E) of the emitter itself was exhibited, and in the high electric field region, the characteristic followed the current-voltage characteristic (M) of the TFT. That is, a transistor control region of a current is obtained in a high electric field region where the emission current exceeds the drain current value of the TFT. In this device, a stable emission current (ME) is obtained at a gate voltage of 70 V or more.
was gotten.

Example 2 Step (a) First, a PECV was formed as a semiconductor thin film layer 2 on an insulating substrate 1.
0.5μ of hydrogenated amorphous silicon film by D method
The film was formed with a thickness of m. Using silane gas as a reaction gas and hydrogen as a diluting gas, a total gas flow rate of 300 scc
m, gas pressure of 1 Torr, substrate temperature of 250 ° C., and RF power of 60 W. Next, Al as a material of the first conductive layer 6 and the second conductive layer 8 is 0.1 μm by vapor deposition.
After forming the m film, patterning was performed by a photolithography method. Subsequently, PECV is used as the emitter material layer 5 '.
An N-type hydrogenated amorphous silicon film having a thickness of 0.8 μm was formed by Method D. Silane gas and phosphine gas (dope concentration 3000 ppm) as reaction gas,
In addition, hydrogen is used as the diluent gas, and the total gas flow rate is 560s.
The film was formed under the conditions of ccm, gas pressure of 1 Torr, substrate temperature of 350 ° C., and RF power of 60 W (FIG. 4A).

Step (b) Next, a circular pattern having a gate opening diameter of 1.2 μm is formed by using ordinary photolithography, and hydrogenated amorphous silicon, which is the emitter material layer 5 ′, is formed by reactive ion etching. Etching was performed until the second conductive layer 8 was exposed. The etching conditions at this time were (introduced gas: SF6 60 sccm / power 100 W / gas pressure 4.5 Pa) (FIG. 4B).

Step (c) Next, a silicon oxide film as the insulating layer 3, Nb as the gate electrode 4, and a film of 0.6 μm and 0.2 μm, respectively, by anisotropic vapor deposition from a direction perpendicular to the substrate. Thickness was deposited (FIG. 4C).

Step (d) Next, the silicon oxide of the etching mask layer 7 was wet-etched using a buffered hydrofluoric acid solution and lifted off to obtain a cold electron-emitting device as shown in FIG. 4D.

The above-mentioned cold electron-emitting device was manufactured as a prototype and tested and evaluated as follows. That is, the distance between the emitter and the gate electrode of each element is about 0.7 μm, and the emitter height is about 0.8 μm.
m, a glass plate member having a transparent electrode (anode) coated with a phosphor was placed at a distance of 3 from an element having a structure in which channel length L / channel width W was 10/1 as a TFT parameter.
When opposing at 0 mm and applying an extraction voltage between the emitter electrode and the gate electrode with a polarity where the gate electrode side was positive, cold electrons could be emitted satisfactorily and stably.

FIG. 11 is a schematic diagram of the obtained typical emission characteristics. In the low electric field region, the current-voltage characteristic (E) of the emitter itself was exhibited, and in the high electric field region, the characteristic followed the current-voltage characteristic (M) of the TFT. That is, a transistor control region of current can be obtained in a high electric field region where the emission current exceeds the drain current value of the TFT. In this device, a stable emission current (M
E) was obtained.

[0081]

According to the present invention, by forming an emitter from a metal having a TFT structure or non-single-crystal silicon, an emission current highly controlled by a transistor can be obtained even on an insulating substrate, and a matrix can be obtained. Cold electron emission that easily realizes wiring can be obtained.

Therefore, a cold electron-emitting device having high current stability and easy matrix formation can be obtained on a glass substrate which can be formed at a low cost and can have a large area. Further, even when applied to a flat panel display, a high-speed, high-definition image can be obtained with low power consumption.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a cold electron emission device of the present invention.

FIG. 2 is a sectional view of another cold electron-emitting device according to the present invention.

FIG. 3 is a manufacturing process diagram of the cold electron emission device of the present invention.

FIG. 4 is a manufacturing process diagram of the cold electron emitting device of the present invention.

FIG. 5 is a cross-sectional view of a conventional cold electron-emitting device.

FIG. 6 is a manufacturing process diagram of a conventional cold electron emission element.

FIG. 7 is a cross-sectional view of another conventional cold electron emission element.

FIG. 8 is a cross-sectional view of a conventional cold electron emission element.

FIG. 9 is a manufacturing process diagram of another conventional cold electron-emitting device.

FIG. 10 is a manufacturing process diagram of another conventional cold electron-emitting device.

FIG. 11 is a schematic diagram illustrating an example of electrical characteristics of the cold electron emission element of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 insulating substrate 2 semiconductor thin film layer 3 insulating layer 4 gate electrode 5 emitter 6 first conductive layer 7 etching mask layer 8 second conductive layer 51 insulating substrate 52 conductive layer 53 insulating layer 54 gate electrode 55 emitter 61 insulating Substrate 62 Conductive layer 63 Insulating layer 64 Gate electrode 65 Lift-off material 66 Emitter 71 Insulating substrate 72 Conductive layer 73 Resistive layer 74 Insulating layer 75 Gate electrode 76 Emitter 81 Silicon substrate 82 Silicon oxide layer 83 Emitter 84 Silicon oxide layer 85 Insulating layer 86 Gate electrode 91 p-type silicon substrate 92 emitter 93 n-type silicon layer 94 emitter wiring layer 95 insulating layer 96 gate electrode 101 p-type silicon substrate 102 silicon oxide layer 103 emitter 104 silicon oxide layer 105 gate electrode 106 n-type silicon layer 107 Genus film A opening

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masago Kanamaru 1-1-4 Umezono, Tsukuba, Ibaraki Pref. Within the Institute of Electronics and Technology (72) Inventor Junji Ito 1-4-1, Umezono, Tsukuba, Ibaraki Inside the Electronic Technology Research Institute, Industrial Technology Institute

Claims (14)

[Claims] An insulating layer and a gate electrode are sequentially laminated on an insulating substrate, and an opening is provided in the gate electrode and the insulating layer so that an emitter does not contact the gate electrode in the opening. In the formed field emission type cold electron emission element, the material of the emitter is non-single-crystal silicon, and the first conductive layer is formed on the insulating substrate other than the opening, and A semiconductor thin film layer is formed between the emitter and between the insulating substrate and the first conductive layer, and the emitter and the first conductive layer are formed on the same plane of the semiconductor thin film layer without directly contacting each other. A cold electron-emitting device, comprising: 2. The cold electron-emitting device according to claim 1, wherein a second conductive layer made of a metal thin film is provided between the emitter and the semiconductor thin film layer. 3. The cold electron-emitting device according to claim 1, wherein the non-single-crystal silicon of the emitter material is amorphous silicon or polysilicon. 4. The cold electron-emitting device according to claim 1, wherein the emitter material is n-type hydrogenated amorphous silicon. 5. The cold electron-emitting device according to claim 1, wherein an insulating layer and a gate electrode are laminated on the first conductive layer. 6. The cold electron-emitting device according to claim 1, wherein the semiconductor thin film layer is made of non-single-crystal silicon. 7. The cold electron-emitting device according to claim 1, wherein the shape of the emitter is a cone, a truncated cone, or a truncated polygon. 8. The cold electron-emitting device according to claim 1, wherein a glass substrate is used as the insulating substrate. 9. The method for manufacturing a cold electron emitting device according to claim 1, wherein: (a) forming a semiconductor thin film layer and a metal thin film layer on an insulating substrate, and then forming the metal thin film layer by photolithography; Patterning to form a first conductive layer, and then sequentially forming an emitter material layer and an etching mask material layer; (b) the etching mask material layer is formed in a circular shape having a gate opening diameter by photolithography. Or forming a polygonal pattern and etching the emitter material layer by reactive ion etching until the semiconductor thin film layer is exposed while leaving the first conductive layer, thereby forming an emitter; (c) for the insulating substrate An insulating layer material and a gate electrode material are formed on the semiconductor thin film layer by a vertical anisotropic vapor deposition method, and the insulating layer and the gate electrode are formed in a self-aligned manner. And (d) peeling off the insulating layer material on the gate electrode and the gate electrode material at the same time as peeling off the etching mask layer. 10. In the step (a), when forming a first conductive layer by patterning a metal thin film layer by photolithography, a second conductive layer is simultaneously formed on an insulating substrate on which an emitter is to be formed. And step (b)
Forming a circular or polygonal pattern having an opening diameter of a gate on the etching mask material layer by photolithography, and forming the emitter material layer on the first conductive layer and the second conductive layer by reactive ion etching. The method according to claim 9, wherein the emitter is formed by etching until the semiconductor thin film layer is exposed while leaving the emitter. 11. The method according to claim 9, wherein in the step (a), the emitter material layer is made of hydrogenated amorphous silicon formed by a plasma enhanced CVD method. 12. In the step (a), the emitter material layer is made of n-type hydrogenated amorphous silicon formed by a plasma enhanced CVD method using at least a mixed gas of silane and phosphine as a reaction gas. A method for manufacturing the cold electron emitting device according to the above. 13. The method according to claim 9, wherein in the step (a), the semiconductor thin film layer is made of hydrogenated amorphous silicon formed by a plasma enhanced CVD method. 14. The method according to claim 9, wherein in the step (a), the semiconductor thin film layer is made of polysilicon formed by forming an amorphous silicon film by a thermal CVD method or a plasma enhanced CVD method and then performing an annealing treatment. 11. The method for manufacturing a cold electron-emitting device according to item 10.