JPH11224595A - Cold electron emission element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cold electron emission element of a field emission type, in which a localized big current is suppressed without raising an operating voltage, a current variation can be reduced to the minimum, and in addition, a low cost and a large area can be easily obtained by using a glass board, by loading a current limiting function in an element itself by using semiconductor thin film, and its manufacturing method. SOLUTION: As for a cold electron emission element of field emission type, in which a conductive layer 6, an insulating layer 3 and a gate electrode 4 are laminated on an insulating board 1, an opening part A reaching a conductive board is provided in the gate electrode and the insulating layer, and an emitter is formed on the conductive board in the opening part so as not to come in contact with the gate electrode, a semiconductor thin film layer 2 is provided on the insulating board, and the emitter 5 and the conductive layer 6 are formed on the same plane on the semiconductor thin film layer electrically through the semiconductor thin film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type cold electron-emitting device that emits electrons by a strong electric field and a method of manufacturing the same. More specifically, as an electron source or an electron gun of an optical printer, an electron microscope, an electron beam exposure device, or the like, or as a micro illumination source of an illumination lamp, particularly, an array-shaped FEA (so-called FEA) constituting a flat display.
Field of the Invention The present invention relates to a cold electron emitting element useful as an electron source of a field emitter array and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube has been widely used as an electronic display device. However, the cathode ray tube consumes a large amount of energy to emit thermoelectrons from a cathode of an electron gun, and is structurally large. There were problems such as requiring a volume.

[0003] For this reason, there has been a demand for a flat display in which cold electrons can be used instead of thermoelectrons, thereby reducing the energy consumption as a whole and further reducing the size of the device itself. There is also a strong demand for such a flat display to realize high-speed response and high resolution.

As a structure of such a flat display utilizing cold electrons, a structure in which minute cold electron-emitting devices are arranged in an array in a flat plate cell in a high vacuum is considered to be promising. As a cold electron-emitting device used therefor, a field-emission cold electron-emitting device utilizing a field emission phenomenon has been receiving attention. In this field emission type cold electron-emitting device, when the intensity of an electric field applied to a substance is increased, the width of an energy barrier on the surface of the substance is gradually reduced according to the intensity,
When the electric field intensity becomes a strong electric field of 10 ⁷ V / cm or more, electrons in a substance can break through the energy barrier by a tunnel effect, and the phenomenon that electrons are emitted from the substance is used. In this case, since the electric field complies with Poisson's equation, if a portion where the electric field is concentrated is formed on a member (emitter) that emits electrons, cold electrons can be efficiently emitted with a relatively low extraction voltage.

As a general example of such a field emission type cold electron emitting device, a conical cold electron emitting device having a sharp tip as shown in FIG. 5 can be exemplified. In this device, a conductive layer 52, an insulating layer 53, and a gate electrode 54 are sequentially laminated on an insulating substrate 51, and an opening A reaching the conductive layer 52 is formed in the insulating layer 53 and the gate electrode 54. Have been. And the opening A
A conical emitter 55 having a point-like projection Po is formed on the conductive layer 52 in such a manner as not to contact at least the gate electrode 54.

Among such conical emitters, Spindt-type emitters are widely known.

An example of manufacturing a cold electron emitting device having a Spindt-type emitter will be described with reference to FIGS. 6 (a) to 6 (d).

First, as shown in FIG. 6A, an insulating layer 63 and a gate electrode 64 are sequentially formed on an insulating substrate 61 on which a conductive layer 62 has been formed by sputtering or vacuum evaporation. . Subsequently, the insulating layer 6 is formed using photolithography and reactive ion etching (RIE).
3 and a part of the gate electrode 64 are etched such that a circular hole (gate hole) is opened until the conductive layer 62 is exposed.

Next, as shown in FIG. 6B, a lift-off material 65 is formed only on the upper surface and side surfaces of the gate electrode 64 by oblique evaporation. The material of the lift-off material 65 is A
1, MgO and the like are often used.

Subsequently, as shown in FIG. 6C, a metal material for the emitter 66 is deposited on the conductive layer 62 by a normal anisotropic deposition from a perpendicular direction. At this time,
As the deposition proceeds, the conical emitter 66 is formed on the conductive layer 62 in a self-aligned manner at the same time as the opening diameter of the gate hole is reduced. The vapor deposition is performed until the gate hole is finally closed. As a material of the emitter, Mo, Ni, or the like is used.

Finally, as shown in FIG. 6D, the lift-off material 65 is peeled off by etching, and the gate electrode 64 is patterned if necessary. Thus, a cold electron emitting device having a Spindt-type emitter is obtained.

The cold electron emission device having such a Spindt-type emitter has the advantages that a conical emitter can be easily formed in a self-aligned manner by anisotropic vapor deposition, and that the emitter material can be selected over a wide range. doing. Also, after emitter wiring

When a cold electron emitting device utilizing a fine processing technique represented by a Spindt-type emitter is applied to a flat display or the like in particular, a small fluctuation of the emission current from the emitter is required to obtain a high quality image. Is essential.

The fluctuation of the emission current can be reduced to some extent by integrating the emitter.
This is because the effect of variations in emission characteristics of individual emitters is reduced by integration. However, in this method, the emission current from each emitter is merely averaged, so that it is impossible to suppress an abnormally large emission current that appears locally.

As a means for reducing such a variation in emission current, US Pat. No. 3,787,471 discloses a technique in which a resistive layer is provided between a conductive layer and an emitter in a Spindt-type emitter.

An example of the configuration of a cold electron emission device having such a resistance layer will be described with reference to FIG.

A conductive layer 72 and a resistance layer 7 are formed on an insulating substrate 71.
3, an insulating layer 74 and a gate electrode 75 are sequentially laminated, and the insulating layer 74 and the gate electrode 75
An opening A reaching 3 is formed. Then, at least the gate electrode 7 is provided on the resistance layer 73 in the opening A.
A conical emitter 76 is formed so as not to come into contact with 5.

In this case, the resistance layer 73 is electrically inserted between the conductive layer 72 and the emitter 76 in series. The resistance layer 73 provides an effect of equalizing the current between the elements, and further reduces a large current that may lead to element destruction, and also reduces a variation in emission current in proportion to the resistance value of the resistance layer 73. It becomes possible. Generally, the resistivity of the resistance layer 73 is appropriately set to 10 ² to 10 ⁶ Ω · cm.

On the other hand, silicon emitters to which semiconductor integrated circuit manufacturing technology is applied are also widely known. (Tech.Dig.
IVMC., (1991) p26)

An example of manufacturing a cold electron-emitting device having a silicon emitter will be described with reference to FIGS.

First, as shown in FIG. 8A, a single crystal silicon substrate 81 is thermally oxidized to form a silicon oxide layer on the surface, and the silicon oxide layer is patterned into a circular shape by using photolithography. Thus, a circular silicon oxide layer 82 for an etching mask is formed. This silicon oxide layer 82 also functions as a lift-off material as described later. Note that the diameter of the silicon oxide layer 82 substantially corresponds to the gate diameter.

Next, as shown in FIG. 8B, the reactive ion etching method (R
The emitter 83 is formed by etching the silicon substrate 81 by IE).

Subsequently, as shown in FIG. 8C, a silicon oxide layer 84 for sharpening the tip of the emitter is formed on the surfaces of the silicon substrate 81 and the emitter 83 by thermal oxidation. Due to the stress generated when the silicon oxide layer 84 is formed, the tip of the emitter 83 inside the silicon oxide layer 84 is easily sharpened.

Then, as shown in FIG. 8D, an insulating layer 85 and a gate electrode 86 are laminated by anisotropic vapor deposition.
Finally, as shown in FIG. 8E, the silicon oxide layer 82 for an etching mask, which also functions as a lift-off material, is lifted off by etching, and the silicon oxide layer 84 on the surface of the emitter 83 is removed by etching. Then, the gate electrode 86 is patterned as necessary. Thereby, a cold electron emission device having a silicon emitter is obtained.

More recently, in silicon emitters,
It is shown that advanced current control is possible by utilizing the properties of silicon as a semiconductor. (Jpn.J.Appl.Phy
s.vol.35 (1996) p6637). A silicon emitter equipped with such a current control function is called a MOSFET structure emitter. The configuration of the cold electron-emitting device having the MOSFET structure emitter will be described with reference to FIG.

On the same plane of the p-type silicon substrate 91, n
An emitter wiring layer 94 is provided via a conical emitter 92 of n-type silicon and an n-type silicon layer 93, and a gate electrode 96 is provided between the emitter 92 and the emitter wiring layer 94 via an insulating layer 95. . That is, a MOSFET (so-called metal oxide semicon-d
The emitter wiring layer 94 of the cold electron emission element is a MOSFET source, the emitter 92 is a drain, the gate electrode 96 is a gate, and the insulating layer 95 is a gate insulating film. Function as each.

An example of manufacturing a cold electron emitting device having a MOSFET structure emitter will be described with reference to FIGS.

First, as shown in FIG. 10A, a single-crystal p-type silicon substrate 101 is thermally oxidized to form a silicon oxide layer 102 on the surface, and the silicon oxide layer 102 is formed by photolithography. Then, a circular silicon oxide layer 102 for an etching mask is formed by patterning in a circular shape. This silicon oxide layer 102 also functions as a lift-off material as described later. Note that the diameter of the silicon oxide layer 102 corresponds to the diameter of the gate.

Next, as shown in FIG. 10B, the p-type silicon substrate 101 is etched by reactive ion etching (RIE) under a condition of a high side etch rate to form an emitter 103.

Subsequently, as shown in FIG. 10C, a silicon oxide layer 104 for sharpening the tip of the emitter and for the insulating layer is formed on the surface of the p-type silicon substrate 101 and the emitter 103 by thermal oxidation. The tip of the emitter 103 inside the silicon oxide layer 104 is easily sharpened by the stress generated when the silicon oxide layer 104 is formed.

Then, as shown in FIG. 10D, a material for the gate electrode 105 is formed, and a circular hole pattern for the emitter wiring is formed using the material of the gate electrode 106 by photolithography.

Next, as shown in FIG. 10E, the silicon oxide layer 102 for an etching mask, which also functions as a lift-off material, is lifted off by etching, and the silicon oxide layer 104 on the surface of the emitter 103 is removed by etching. At the same time, an emitter wiring hole is formed.

Subsequently, as shown in FIG. 10 (f), phosphorus is ion-implanted and then diffusion annealing is performed.
3 is made n-type, and an n-type silicon layer 106 is formed on the surface of the emitter wiring hole.

Finally, as shown in FIG. 10 (g), after a metal thin film 107 such as aluminum is formed as an electrode material for the emitter wiring and the gate wiring, the gate electrode 105 is patterned as necessary. This allows MOSF
A cold electron emission device having an ET structure emitter is obtained.

In a cold electron emission device including a silicon emitter having such a MOSFET structure, although a MOS transistor can be easily manufactured in substantially the same manufacturing process as a conventional silicon emitter, a MOS transistor is built in the device. An extremely stable emission current controlled by a transistor can be obtained, and the generation of a local large current can be eliminated.

However, in a cold electron emission element provided with a resistance layer for current stabilization, it is necessary to provide a larger resistance in order to obtain a sufficient current reduction characteristic with respect to a local large current. At the same time, current fluctuations can be reduced only relative to the characteristics of individual elements,
Further, there is a problem that an increase in operating voltage cannot be avoided in principle.

On the other hand, a MOSFE equipped with a current control function
In a silicon emitter having a T structure, a stable current at a very high level can be obtained by transistor control. However, since a single crystal silicon substrate is required, it is difficult to reduce the cost and increase the area. was there.

[0038]

SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned problems of the prior art, and the operating voltage is reduced by mounting a current control function on the element itself using a semiconductor thin film. Suppress local large currents without raising them, minimize current fluctuations, and make it possible to use glass substrates etc. to easily reduce costs and increase area. It is an object of the present invention to provide a field emission type cold electron emitting device capable of performing the method and a method for manufacturing the same.

[0039]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a semiconductor device, comprising: a conductive layer, an insulating layer, and a gate electrode sequentially laminated on an insulating substrate; In the field emission type cold electron emitting element, an opening reaching the conductive substrate is provided, and an emitter is formed on the conductive substrate in the opening so as not to contact the gate electrode. A cold electron emission element, wherein a semiconductor thin film layer is provided on a substrate, and an emitter and a conductive layer are electrically formed on the same plane on the semiconductor thin film layer via the semiconductor thin film. .

A second aspect of the present invention is based on the configuration of the first aspect, wherein an emitter connection layer made of a metal thin film is interposed between the emitter and the semiconductor thin film layer.

A third aspect of the present invention is based on any one of the first and second aspects, and is characterized in that an insulating layer and a gate electrode are laminated on a conductive layer.

A fourth aspect of the present invention is based on any one of the first to third aspects and is characterized in that the semiconductor thin film layer is made of non-single-crystal silicon.

A fifth aspect of the present invention is based on any one of the first to fourth aspects, wherein the emitter material is metal or non-single-crystal silicon.

According to a sixth aspect of the present invention, based on any one of the first to fifth aspects, the shape of the emitter is conical,
It is a polygonal pyramid, a truncated cone, or a truncated polygon.

A seventh aspect of the present invention is based on any one of the first to sixth aspects, and is characterized in that a glass substrate is used as an insulating substrate.

The invention described in claim 8 is the first invention.
7. A method for manufacturing a cold electron-emitting device according to any one of (1) to (7), wherein (a) a semiconductor thin film material layer, an insulating material layer,
A step of sequentially forming a gate electrode material layer; (b) forming a pattern of holes having openings for gate formation by a photolithography method, and reacting the gate electrode material layer and the insulating material layer until the semiconductor thin film layer is exposed; Etching by ion etching to form a hole for an emitter, a hole for a conductive layer, and a gate electrode and an insulating layer; (c) depositing a lift-off material on the upper and side surfaces of the gate electrode by oblique deposition. A self-aligned emitter and conductive layer are formed by forming a lift-off layer with an anisotropic vapor deposition method having anisotropy in a direction substantially perpendicular to the insulating substrate and forming an emitter material in the emitter hole. (D) peeling off the lift-off layer to peel off the emitter material on the gate electrode; characterized in that it comprises all of the above steps (a) to (d). It is a manufacturing method of the field emission device according to.

The invention according to claim 9 is based on claim 1
(E) forming a semiconductor thin film material layer and a metal thin film layer on an insulating substrate, and then forming the metal thin film layer by a photolithography method. Forming a conductive layer and an emitter connection layer by patterning, and then sequentially forming an insulating material layer and a gate electrode material layer; (f) photolithographically forming a pattern of holes having openings for forming gates. Forming a gate electrode material layer and an insulating material layer by reactive ion etching until the semiconductor thin film layer is exposed, thereby forming an emitter hole, and a gate electrode and an insulating layer; (g) A lift-off layer is formed by obliquely depositing a lift-off material on the upper and side surfaces of the gate electrode, and is formed in a direction substantially perpendicular to the insulating substrate. A step of forming an emitter in a self-aligned manner by forming an emitter material in an emitter hole by anisotropic anisotropic vapor deposition; (h) peeling off the lift-off layer and peeling off the emitter material on the gate electrode; A method of manufacturing a cold electron-emitting device, comprising: all of the above steps (e) to (h).

The tenth aspect of the present invention is the eighth or ninth aspect.
In the above step (a) or step (e), the semiconductor thin film material is made of amorphous silicon hydride, and the semiconductor thin film material is formed by a PECVD method.

The eleventh aspect of the present invention relates to the eighth or ninth aspect.
In either of the above steps (a) and (e), the semiconductor thin film material is made of polysilicon, and the semiconductor thin film material is made amorphous by either a thermal CVD method or a PECVD method. It is characterized in that polysilicon is generated by performing an annealing process after forming silicon.

The twelfth aspect of the present invention relates to the eighth to first aspects.
1. In any one of the above steps (a) and (e), the insulating layer material is made of amorphous silicon nitride, and a mixed gas of either silane or disilane and ammonia is used. It is characterized by being formed by a PECVD method used as a reaction gas.

[0051]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a cold electron emitting device of the present invention. As shown in FIG. 1, the cold electron emission element has a structure in which a semiconductor thin film layer 2, an insulating layer 3, and a gate electrode 4 are sequentially stacked on an insulating substrate 1. The gate electrode 4 and the insulating layer 3 are provided with an emitter hole A and a conductive layer hole B reaching the semiconductor thin film layer 2 with an appropriate gap therebetween. On the semiconductor thin film layer 2 in B, a conical or truncated conical emitter 5 and a conductive layer 6 are formed so as not to contact the gate electrode 4.

In the present invention, the insulating substrate 1 is used as a supporting insulating substrate of a cold electron emission element, and an insulating substrate that can be easily enlarged can be preferably used. As such an insulating substrate, a glass substrate, a ceramic substrate, a quartz substrate, or the like can be used.
Note that a substrate in which an insulating film is formed over the surface of single crystal silicon can also be used.

The semiconductor thin film layer 2 includes a thin film transistor (T
FT). Such a semiconductor thin film layer 2 can be formed from a known material similar to a TFT widely used as a switching element of a liquid crystal display. For example, particularly when a glass substrate is used as the insulating substrate 1, hydrogenated amorphous silicon or polysilicon obtained by laser annealing can be used.

The thickness of the semiconductor thin film layer 2 is, for example, 0.2 μm so that it can operate as a channel of the TFT.
To 2 μm, preferably 0.3 to 0.7 μm.

The insulating layer 3 is a layer for electrically insulating the emitter 5 and the conductive layer 6 from the gate electrode 4. Further, they are used simultaneously to electrically insulate the semiconductor thin film layer 2 and the gate electrode 4. That is, it also functions as a TFT gate insulating film. Such an insulating layer 3 can be formed from a known material used as a cold electron emitting element and an insulating layer of a TFT, and shows a particularly good insulating property and obtains a pinhole-free film. PECVD (so-called Plasma Enhanced Chemi-cal V
Silicon oxide and silicon nitride films formed by the apor deposition method.

The thickness of the insulating layer 3 may be such that sufficient insulation between the emitter 5, the conductive layer 6, and the semiconductor thin film layer 2 and the gate electrode 4 is maintained, for example, 0.2 to 2 μm.
Preferably, it is 0.3 to 0.7 μm.

The gate electrode 4 functions as an electrode for concentrating a strong electric field on the emitter 5 and as a gate electrode of the TFT. As a material for the gate electrode 4, a material having a high melting point in view of current resistance and having resistance to an etching solution used for forming an emitter can be used. Preferably, Cr, W, Ta or Nb is used. Can be mentioned. Above all, it is preferable to use Nb from the viewpoint of adhesion to the base.

The thickness of the gate electrode 4 can be appropriately determined as needed, and is set to 0.1 to 0.5 μm.

The emitter 5 is a member that emits electrons directly from its surface, and can be formed from a known material used as an emitter of a cold electron emission element.
A metal thin film or a non-single-crystal silicon thin film can be used. Here, the emitter is a non-single-crystal silicon thin film,
For example, when formed of a polysilicon thin film or an amorphous silicon thin film, more stable emission characteristics can be obtained because the emitter itself has a certain degree of resistance.

The thickness (height) of the entire emitter 5 can be appropriately determined as required, and is usually 0.3 to 2 μm.
m is preferable.

The shape of the emitter 5 is preferably a cone or a column, or a truncated cone or a truncated polygon.

The conductive layer 6 functions as the emitter wiring of the cold electron emission element and the source of the TFT. As a material of such a conductive layer 6, a material having low wiring resistance, high adhesion to the underlying semiconductor thin film layer 2 and ohmic contact is appropriate. Such a material is particularly preferably Cr
Alternatively, an Al, Cr laminated film can be used. However,
Depending on the manufacturing method, the material may be the same as the emitter material. In this case, a material that satisfies the required characteristics of both the emitter 5 and the conductive layer 6 is used. Such materials include:
The material used for the emitter 5 and a laminated film of Al, Cu and Au can be used.

The thickness of the conductive layer 6 is not particularly limited as long as sufficient wiring resistance and adhesion can be obtained.
The thickness is 5 to 2.0 μm, preferably 0.1 to 1.0 μm.

FIG. 2 is a sectional view of another cold electron-emitting device according to the present invention. As shown in FIG. 1, the cold electron emission element has a structure in which a semiconductor thin film layer 2, an insulating layer 3, and a gate electrode 4 are sequentially stacked on an insulating substrate 1. And
A plurality of emitter holes A reaching the semiconductor thin film layer 2 are provided in the gate electrode 4 and the insulating layer 3, and an emitter connection layer 8 made of a metal thin film is disposed on the semiconductor thin film layer 2 in the emitter hole A. A plurality of conical or frustoconical emitters 5 are formed on the emitter connection layer 8 so as not to contact the gate electrode 4. When there are a plurality of emitters 5, the emitters 5 are electrically connected by the emitter connection layer 8. Further, a conductive layer 6 is arranged with an appropriate gap from the emitter connection layer 8, and has a structure in which an insulating layer 3 and a gate electrode 4 are sequentially laminated on the conductive layer 6. By providing the emitter connection layer 8 in this manner, current control can be performed particularly on a plurality of emitters at the same time. Further, it has a structure in which the insulating layer 3 and the gate electrode 4 are stacked on the conductive layer 6. Thereby, matrix wiring can be performed.

Next, a method of manufacturing the cold electron emitting device of the present invention will be described in detail with reference to FIG.

Step (a) First, a material for the semiconductor thin film layer 2 such as non-single-crystal silicon and a material for the insulating layer 3 are formed on the insulating substrate 1 by a CVD method or the like. Film,
A laminated film is formed. (FIG. 3A) Here, as a method of forming the material of the insulating layer 3, various methods that can be used to obtain a film having a high electrical insulating property can be used. Amorphous silicon nitride formed by a PECVD method using a mixed gas of silane or disilane exhibiting characteristics and ammonia as a reaction gas can be used.

Step (b) Next, a circular or polygonal hole pattern having a gate opening diameter and a through hole for a conductive layer are formed by photolithography, and the material of the gate electrode 4 and the insulating layer are formed by reactive ion etching. The three materials are etched until the semiconductor thin film layer 2 is exposed to form a hole A for an emitter and a hole B for a conductive layer, and a gate electrode 4 and an insulating layer 3. (FIG. 3 (b))

Step (c) Subsequently, a lift-off material 7 is applied to the gate electrode 4 by oblique evaporation.
Formed only on the top and side surfaces. As the material of the lift-off material 7, Al, MgO, or the like having high releasability at the time of lift-off can be preferably used. Subsequently, a metal material for the emitter 5 is deposited on the semiconductor thin film layer 2 in the hole A for the emitter and the hole B for the conductive layer by normal anisotropic deposition from the perpendicular direction. At this time, as the vapor deposition progresses, the conical emitter 5 is formed on the semiconductor thin film layer 2 in a self-aligning manner at the same time as the opening diameter of the emitter hole A decreases. The vapor deposition is performed until the emitter hole A is finally closed. At this time, the conductive layer 6 is simultaneously formed in the conductive layer hole B. The material of the emitter can be selected from a wide range of materials that can be deposited, such as metals, semiconductors, and ceramics. Further, when amorphous silicon or polysilicon formed by a vapor deposition method is used as an emitter material, more stable emission characteristics can be obtained. (FIG. 3 (c))

At this time, for example, when the total thickness of the insulating layer 3 and the gate electrode 4 is 1 μm, and when the diameter of the emitter hole A is 1 μm or less, the emitter shape is conical and larger than 1 μm, and When the deposition of the emitter material is completed before the emitter hole A is closed, the shape becomes substantially a truncated cone. When the shape of the emitter hole A is not a circle but a polygon, it can be a polygonal pyramid or a truncated polygonal cone, respectively. Here, it has been confirmed from experiments by the inventor that, for example, a trapezoidal conical shape can obtain more uniform emission characteristics over a large area than a conical shape. Thereby, for example, the emitter 5 having a sharpened tip is formed.

Step (d) Finally, the lift-off material 7 is removed by etching, and the gate electrode 4 is patterned as necessary. Thus, the cold electron-emitting device shown in FIG.

Next, another method of manufacturing a cold electron-emitting device of the present invention, which is particularly effective when a plurality of emitters are provided and when a matrix array is formed, will be described in detail with reference to FIG.

Step (a) First, a material for the semiconductor thin film layer 2 such as non-single-crystal silicon is formed on the insulating substrate 1 by a CVD method or the like.
After forming a metal thin film also serving as the emitter connection layer 8 by vapor deposition or the like, the conductive layer 6 is formed by photolithography.
And an emitter connection layer 8 is provided with a gap corresponding to the channel length of the TFT to perform patterning. Here, the material of the semiconductor thin film 2 is hydrogenated amorphous silicon formed by PECVD, thermal CVD (so-called Chemical Vapor Deposition), or PEC.
Polysilicon produced by annealing an amorphous silicon film formed by the VD method by, for example, laser annealing or the like can be preferably used.

Further, a material for the insulating layer 3 and a material for the gate electrode 4 are formed. (FIG. 4 (a)) Here, as a method of forming the material of the insulating layer 3, various methods that can be used to obtain a film having a high electric insulating property can be used. Using a mixed gas of silane or disilane having a characteristic and ammonia as a reaction gas;
Amorphous silicon nitride formed by an ECVD method can be used.

Step (b) Next, a circular hole or polygonal hole pattern having a gate opening diameter is formed by photolithography, and the material of the gate electrode 4 and the material of the insulating layer 3 are removed by reactive ion etching. Etching is performed until 8 is exposed, thereby forming an emitter hole A and forming a gate electrode 4 and an insulating layer 3. (FIG. 4 (b))

Step (c) Subsequently, a lift-off material 7 is applied to the gate electrode 4 by oblique evaporation.
Formed only on the top and side surfaces. As the material of the lift-off material 7, Al, MgO, or the like having high releasability at the time of lift-off can be preferably used. Subsequently, a metal material for the emitter 5 is deposited on the emitter connection layer 8 in the emitter hole A by normal anisotropic deposition from the vertical direction. At this time, as the vapor deposition progresses, the conical emitter 5 is formed on the semiconductor thin film layer 2 in a self-aligning manner at the same time as the opening diameter of the emitter hole A decreases. The vapor deposition is performed until the emitter hole A is finally closed. The material of the emitter can be selected from a wide range of materials that can be deposited, such as metals, semiconductors, and ceramics. Further, when amorphous silicon or polysilicon formed by a vapor deposition method is used as an emitter material, more stable emission characteristics can be obtained. (FIG. 4 (c))

Step (d) Finally, the lift-off material 7 is peeled off by etching, and the gate electrode 4 is patterned if necessary. Thus, the cold electron-emitting device shown in FIG. 4D is obtained.

As described above, in the cold electron-emitting device of the present invention, the emitter is made of metal having a TFT structure or non-single-crystal silicon, so that the transistor is highly controlled even on the insulating substrate by the transistor. An emission current can be obtained and matrix wiring can be easily realized.

[0079]

EXAMPLES The production examples of the cold electron-emitting device of the present invention will be specifically described in the following examples.

Step (a) First, a PECV is formed as a semiconductor thin film layer 2 on an insulating substrate 1.
0.5μ of hydrogenated amorphous silicon film by D method
m was formed. Using silane gas as a reaction gas and hydrogen as a diluting gas, a total gas flow rate of 300 scc
m, gas pressure of 1 Torr, substrate temperature of 250 ° C., and RF power of 60 W. Next, an amorphous silicon nitride film having a thickness of 0.5 μm was continuously formed as a material of the insulating layer 3 by PECVD. Using a mixed gas of silane and ammonia as a reaction gas and hydrogen as a diluting gas, a total gas flow rate of 540 sccm and a gas pressure of 1
The film was formed under the conditions of Torr, substrate temperature of 350 ° C., and RF power of 60 W. Subsequently, Nb was formed in a thickness of 0.2 μm as a gate electrode material by a vacuum evaporation method. (FIG. 3
(A))

Step (b) Next, a circular hole pattern having a gate opening diameter of 1 μm is formed by using a usual photolithography method, and the material Nb of the gate electrode 4 and the material of the amorphous silicon nitride 3 are formed by reactive ion etching. Was etched until the semiconductor thin film layer 2 was exposed. The etching conditions at this time were (introduced gas: SF ₆ was ₆₀ sccm / power 100 W / gas pressure 4.5 Pa). (FIG. 3
(B))

Step (c) Next, as the lift-off material 7, Al was obliquely deposited to a thickness of 0.3 μm. Subsequently, Mo was deposited as a material of the emitter 5 by an anisotropic vapor deposition method from a direction perpendicular to the substrate until the emitter hole A was closed. (FIG. 3 (c))

Step (d) Next, Al of the lift-off material 7 was wet-etched using an acid-based etchant and peeled off together with the upper layer emitter material to obtain a cold electron emitting device as shown in FIG.

The cold electron emission device described above was manufactured as a prototype, and the following tests were performed and evaluated. That is, the distance between the emitter and the gate electrode of each element is about 0.6 μm, and the emitter height is about 0.8 μm.
m, a glass plate member having a transparent electrode (anode) coated with a phosphor was placed at a distance of 3 from an element having a structure in which channel length L / channel width W was 10/1 as a TFT parameter.
When the electrodes were opposed to each other at 0 mm, and a drawing voltage was applied between the emitter electrode and the gate electrode with a positive polarity on the gate electrode side, electrons were successfully and stably emitted.

FIG. 11 is a schematic diagram of the obtained typical emission characteristics. In the low electric field region, the current-voltage characteristic (E) of the emitter itself was exhibited, and in the high electric field region, the characteristic followed the current-voltage characteristic (M) of the TFT. That is, a transistor control region of current can be obtained in a high electric field region where the emission current exceeds the drain current value of the TFT. In this device, a stable emission current (M
E) was obtained.

[0086]

According to the present invention, by forming an emitter from a metal having a TFT structure or non-single-crystal silicon, an emission current highly controlled by a transistor can be obtained even on an insulating substrate, and a matrix can be obtained. Cold electron emission that easily realizes wiring can be obtained.

Therefore, it is possible to obtain a cold electron-emitting device having high current stability and easy matrix formation on a glass substrate which can be formed at a low cost and can have a large area. Further, even when applied to a flat panel display, a high-speed, high-definition image can be obtained with low power consumption.

After all, according to the present invention, by mounting a current control function on the device itself using a semiconductor thin film, a local large current can be suppressed without increasing the operating voltage, and the current fluctuation can be reduced to a minimum. To provide a field emission type cold electron-emitting device and a method for manufacturing the same, which can facilitate cost reduction and large area by using a glass substrate or the like. Was completed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a cold electron emission device of the present invention.

FIG. 2 is a sectional view of another cold electron-emitting device according to the present invention.

FIG. 3 is a manufacturing process diagram of the cold electron emission device of the present invention.

FIG. 4 is a manufacturing process diagram of another cold electron-emitting device of the present invention.

FIG. 5 is a cross-sectional view of a conventional cold electron-emitting device.

FIG. 6 is a manufacturing process diagram of a conventional cold electron emission element.

FIG. 7 is a cross-sectional view of another conventional cold electron emission element.

FIG. 8 is a cross-sectional view of a conventional cold electron emission element.

FIG. 9 is a manufacturing process diagram of another conventional cold electron-emitting device.

FIG. 10 is a manufacturing process diagram of another conventional cold electron-emitting device.

FIG. 11 is a schematic diagram illustrating an example of electrical characteristics of the cold electron emission element of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Semiconductor thin film layer 3 ... Insulating layer 4 ... Gate electrode 5 ... Emitter 6 ... Conductive layer 7 ... Lift-off material 8 ... Emitter connection layer 51 ... insulating substrate 52 ... conductive layer 53 ... insulating layer 54 ... gate electrode 55 ... emitter 61 ... insulating substrate 62 ... conductive layer 63 ... insulating layer 64 ... Gate electrode 65 ... Lift-off material 66 ... Emitter 71 ... Insulating substrate 72 ... Conductive layer 73 ... Resistive layer 74 ... Insulating layer 75 ... Gate electrode 76 ... -Emitter 81 ... silicon substrate 82 ... silicon oxide layer 83 ... emitter 84 ... silicon oxide layer 85 ... insulating layer 86 ... gate electrode 91 ... p-type silicon substrate 92 ...・ Emitter 93 ・ ・ ・ n-type silicon Layer 94: Emitter wiring layer 95: Insulating layer 96: Gate electrode 101: p-type silicon substrate 102: Silicon oxide layer 103: Emitter 104: Silicon oxide layer 105: Gate electrode 106 · N-type silicon layer 107 · · · metal thin film A · · · emitter hole B · · · emitter wiring hole E · · · emitter characteristics M · · · MOSFET characteristics ME · emission characteristics

Claims (12)

[Claims] A conductive layer, an insulating layer, and a gate electrode are sequentially laminated on an insulating substrate, and an opening reaching the conductive substrate is provided between the gate electrode and the insulating layer. In a field emission type cold electron emitting element in which an emitter is formed on a substrate so as not to contact the gate electrode, a semiconductor thin film layer is provided on an insulating substrate, and on the same plane on the semiconductor thin film layer, A cold electron-emitting device, wherein an emitter and a conductive layer are electrically formed through the semiconductor thin film. 2. The cold electron emission device according to claim 1, wherein an emitter connection layer made of a metal thin film is interposed between the emitter and the semiconductor thin film layer. 3. The cold electron-emitting device according to claim 1, wherein an insulating layer and a gate electrode are laminated on the conductive layer. 4. The cold electron-emitting device according to claim 1, wherein the semiconductor thin film layer is made of non-single-crystal silicon. 5. The cold electron-emitting device according to claim 1, wherein the emitter material is metal or non-single-crystal silicon. 6. The cold electron-emitting device according to claim 1, wherein the shape of the emitter is any one of a cone, a polygonal pyramid, a truncated cone, and a truncated pyramid. 7. The cold electron-emitting device according to claim 1, wherein a glass substrate is used as the insulating substrate. 8. A method for manufacturing a cold electron-emitting device according to claim 1, wherein: (a) a semiconductor thin film material layer, an insulating material layer,
A step of sequentially forming a gate electrode material layer; (b) forming a pattern of holes having openings for gate formation by a photolithography method, and reacting the gate electrode material layer and the insulating material layer until the semiconductor thin film layer is exposed; Etching by ion etching to form a hole for an emitter, a hole for a conductive layer, and a gate electrode and an insulating layer; (c) depositing a lift-off material on the upper and side surfaces of the gate electrode by oblique deposition. A self-aligned emitter and conductive layer are formed by forming a lift-off layer with an anisotropic vapor deposition method having anisotropy in a direction substantially perpendicular to the insulating substrate and forming an emitter material in the emitter hole. (D) peeling off the lift-off layer to peel off the emitter material on the gate electrode; characterized in that it comprises all of the above steps (a) to (d). Method of manufacturing a field emission device according to. 9. A method for manufacturing a cold electron emitting device according to claim 1, wherein: (e) forming a semiconductor thin film material layer and a metal thin film layer on an insulating substrate; Forming a conductive layer and an emitter connecting layer by patterning the metal thin film layer by photolithography, and then sequentially forming an insulating material layer and a gate electrode material layer; (f) an opening for forming a gate By forming a pattern of holes with a photolithography method, and etching the gate electrode material layer and the insulating material layer by reactive ion etching until the semiconductor thin film layer is exposed, the emitter hole, and the gate electrode and the insulating layer (G) forming a lift-off layer on the upper and side surfaces of the gate electrode by oblique vapor deposition to form a lift-off layer; A step of forming an emitter in a self-aligned manner by forming an emitter material in an emitter hole by an anisotropic vapor deposition method having anisotropy in a direction substantially perpendicular to the plate; (h) removing the lift-off layer Removing the emitter material on the gate electrode; and a method for manufacturing a cold electron-emitting device, comprising all of the above steps (e) to (h). 10. The method according to claim 1, wherein in either the step (a) or the step (e), the semiconductor thin film material is made of hydrogenated amorphous silicon, and the semiconductor thin film material is formed by a PECVD method. 10. The method for manufacturing a cold electron-emitting device according to any one of 8 and 9. 11. In either the step (a) or the step (e), the semiconductor thin film material is made of polysilicon, and the semiconductor thin film material is formed into an amorphous silicon film by a thermal CVD method or a PECVD method. 10. The method according to claim 8, wherein polysilicon is generated by performing an annealing process after the annealing. 12. In either the step (a) or the step (e), the insulating layer material is composed of amorphous silicon nitride, and a mixed gas composed of either silane or disilane and ammonia is used as a reaction gas. P
The method of manufacturing a cold electron emitting device according to claim 8, wherein the cold electron emitting device is formed by an ECVD method.