JPH09129123A - Electron emitting element and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an emitter having a sharp tip of an electron emitting element by the reactive ion etching method, not by the anisotropic deposition method, use a glass substrate capable of easily increasing the area other than single a crystal Si substrate, and maintain the homogeneity of the characteristics of multiple electron emitting elements in the substrate even when the area of the substrate is increased. SOLUTION: This element is laminated with a substrate 1, an emitter wiring layer 2, an insulating layer 4, and a gate electrode 5 in sequence, an opening section A reaching the emitter wiring layer 2 is provided on the gate electrode 5 and the insulating layer 4, and a conical emitter 3 is formed in no contact with the gate electrode 5 on the emitter wiring layer 2 in the opening section A. The emitter wiring layer 2 is made of a metal thin film, and the emitter 3 is made of amorphous silicon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type electron-emitting device that emits electrons by a strong electric field and a method for manufacturing the same. More specifically, optical printers, electron microscopes,
As an electron source and electron gun such as an electron beam exposure device,
Alternatively, as an ultra-compact illumination source for an illumination lamp, in particular, an array-shaped FEA (Field Emitt) that constitutes a flat display.
The present invention relates to an electron-emitting device which is useful as an electron generation source of an electron array and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube has been widely used as an electronic display device. However, the cathode ray tube consumes a large amount of energy to emit thermoelectrons from a cathode of an electron gun, and is structurally large. There were problems such as requiring a volume.

[0003] For this reason, there has been a demand for a flat display in which cold electrons can be used instead of thermoelectrons, thereby reducing the energy consumption as a whole and further reducing the size of the device itself. There is also a strong demand for such a flat display to realize high-speed response and high resolution.

As a structure of such a flat-type display utilizing cold electrons, it is considered promising to arrange minute electron-emitting devices in an array in a high vacuum flat plate cell. And as an electron-emitting device used for that,
A field emission type electron-emitting device utilizing the field emission phenomenon has been attracting attention. In this field emission type electron-emitting device, when the intensity of the electric field applied to the substance is increased, the width of the energy barrier on the surface of the substance is gradually narrowed according to the intensity, and the electric field intensity becomes a strong electric field of 10 ⁷ V / cm or more. Then, the phenomenon that electrons in the substance can break through the energy barrier due to the tunnel effect and the electron is emitted from the substance is used. In this case, since the electric field complies with Poisson's equation, if a portion where the electric field is concentrated is formed on a member (emitter) that emits electrons, cold electrons can be efficiently emitted with a relatively low extraction voltage.

As a general example of such a field emission type electron-emitting device, as shown in FIG. 4, a cone-type electron-emitting device having a pointed tip can be exemplified. In this element, the insulating layer 42 and the gate electrode 43 are sequentially stacked on the conductive layer 41, and the opening A reaching the conductive layer 41 is formed in the insulating layer 42 and the gate electrode 43. Then, on the conductive layer 41 in the opening A, a cone-shaped (cone-shaped) emitter 4 having point projections Po at least so as not to contact the gate electrode 43.
4 are formed.

Such a cone-type emitter has a Spindt-type emitter (J. Vac. Sci. And Tec.
h.Bll.468 (1993)) and Si cone type emitter (Tech.Di.
g.IVMC., p26).

First, an example of manufacturing an electron-emitting device having a Spindt-type emitter will be described with reference to FIGS.

First, as shown in FIG. 5A, an insulating layer 53 and a gate electrode 54 are sequentially formed on a glass substrate 51 on which an emitter wiring 52 is formed by a sputtering method or a vacuum evaporation method. Then, a part of the insulating layer 53 and the gate electrode 54 is partially removed by using the photolithography method and the reactive ion etching method (RIE).
Etching is performed so that a circular hole (gate hole) is opened until 2 is exposed.

Next, as shown in FIG. 5B, a lift-off material 55 is formed only on the gate electrode 54 by oblique evaporation. The material of the lift-off material 55 is Al, MgO
And so on.

Subsequently, as shown in FIG. 5C, the substrate 5
1, on the perpendicular direction by ordinary anisotropic deposition
A metal material for the emitter 56 is deposited. At this time, as the vapor deposition progresses, the opening diameter of the gate hole becomes narrower, and at the same time, the cone-shaped emitter 56 is formed on the emitter wiring 52 in a self-aligned manner. The vapor deposition is performed until the gate hole is finally closed. As a material of the emitter, Mo, Ni, or the like is used.

Finally, as shown in FIG. 5D, the lift-off material 55 is peeled off by etching, and the gate electrode 54 is patterned if necessary. As a result, an electron-emitting device having a Spindt-type emitter is obtained.

In such a Spindt-type emitter, a cone-shaped emitter can be easily formed in a self-aligned manner by anisotropic vapor deposition, so that a wide range of emitter materials can be selected. This has the advantage that any type of substrate, in particular, a glass substrate that can have a large area can be used.

Next, an example of manufacturing an electron-emitting device having a Si cone type emitter will be described with reference to FIGS. 6 (a) to 6 (e).

First, as shown in FIG. 6A, a single crystal S
The i-substrate 61 is thermally oxidized to form a silicon oxide layer on the surface, and the silicon oxide layer is patterned into a circular shape using a photolithography method, thereby forming a circular silicon oxide layer 62 for an etching mask. This silicon oxide layer 62 also functions as a lift-off material as described later. Note that the diameter of the silicon oxide layer 62 corresponds to the gate diameter.

Next, as shown in FIG. 6B, the reactive ion etching method (R
The Si substrate 61 is etched by IE) and the emitter 6
Form 3

Subsequently, as shown in FIG. 6C, a silicon oxide layer 64 for sharpening the tip of the emitter is formed on the surfaces of the Si substrate 61 and the emitter 63 by thermal oxidation. Due to the stress generated when the silicon oxide layer 64 is formed, the tip of the emitter 63 inside the silicon oxide layer 64 is easily sharpened.

Then, as shown in FIG. 6D, an insulating film 65 and a gate electrode 66 are laminated by a vapor deposition method.

Finally, as shown in FIG. 6E, the silicon oxide layer 62 for the etching mask, which also functions as a lift-off material, is lifted off by etching, and the silicon oxide layer 64 on the surface of the emitter 63 is removed by etching. . Then, the gate electrode 66 is patterned as necessary. Thereby, an electron-emitting device having a Si cone type emitter is obtained.

Such a Si-cone type emitter has an advantage that it can have a very sharp tip shape which is difficult to obtain by a physical method.

[0020]

However, in the case of the Spindt-type emitter, it is formed by using the anisotropic vapor deposition method. However, since the vapor deposition particles that diffuse during vapor deposition are not present at all, the entire substrate is Therefore, it is difficult to perform uniform vapor deposition, and thus it is difficult to maintain the uniformity of the characteristics of a plurality of electron-emitting devices on the same substrate. In particular, the tendency becomes more remarkable when the substrate has a large area.

On the other hand, in the case of the Si cone type emitter,
Uniformity of the characteristics of multiple electron-emitting devices in the substrate because the reactive ion etching method that enables uniform etching over the entire substrate without utilizing the anisotropic deposition method at the time of its formation is used. It is possible to keep However, there is a problem in that the substrate used is limited to a very expensive single crystal Si substrate because the thermal oxidation treatment of the single crystal Si is indispensable at the time of its formation. Further, there is a problem in that it is substantially impossible to increase the area of the electron-emitting device because single crystal Si having a large area such as a glass substrate is not available.

From the viewpoint of concentrating an electric field on the emitter, it is desirable that the tip shape of the cone-type emitter has a radius of curvature as small as possible, but in the current fine processing technology, this ideal shape is large. It is not easy to make a uniform area.

The present invention is intended to solve the above-mentioned problems of the prior art, and when forming an emitter of a field emission type electron-emitting device, reactive ion etching is performed without utilizing anisotropic deposition. By using the method or the like, the tip can be sharpened, and a substrate other than the single crystal Si substrate, which can be easily enlarged, such as a glass substrate, can be used, and the substrate is enlarged. Even in such a case, it is an object of the present invention to maintain the uniformity of the characteristics of the plurality of electron-emitting devices in the substrate.

[0024]

The inventor has found that non-single-crystal instead of single-crystal Si is used as an emitter material of an electron-emitting device.
For example, polysilicon or amorphous silicon is used, and an emitter wiring layer made of a metal material that is more difficult to etch than non-single-crystal silicon is provided below the non-single-crystal silicon layer formed to form the emitter. With such a structure, it was found that the non-single-crystal silicon layer can be processed into a cone shape having a sharp tip by RIE having a high side etching rate and, if necessary, wet etching, and the present invention has been completed.

That is, according to the present invention, the substrate, the emitter wiring layer,
An insulating layer and a gate electrode are sequentially laminated, an opening reaching the emitter wiring layer is provided in the gate electrode and the insulating layer, and a cone-shaped emitter is formed on the emitter wiring layer in the opening. In a field emission type electron-emitting device formed so as not to come into contact with an emitter, the emitter wiring layer is formed of a thin metal film, and the emitter is formed of non-single-crystal silicon. I will provide a.

The present invention also provides a method of manufacturing an electron-emitting device in which polysilicon is used as the non-single-crystal silicon constituting the emitter: (a) A metal thin film for forming an emitter wiring is formed on a substrate, A step of forming an emitter wiring layer by patterning; (b) a step of forming a polysilicon layer on the emitter wiring layer; (c) a step of forming an etching mask pattern layer on the polysilicon layer; (d) a reaction A step of etching the polysilicon layer by a reactive ion etching method until the emitter wiring layer is exposed; (e) An emitter is formed by sequentially laminating an insulating material and a gate electrode material on the surface of the substrate on the side of the emitter wiring layer. An insulating layer and a gate electrode are formed on the etching mask pattern layer while an insulating layer and a gate electrode are formed on the wiring layer. A step of forming a material layer; (f) a polysilicon layer located under the etching mask pattern layer is etched by using an alkaline etching solution to sharpen the tip of the polysilicon layer and to be laminated thereon. Etching mask pattern layer,
There is provided a manufacturing method including a step of stripping an insulating material layer and a gate electrode material layer.

The present invention also provides a method of manufacturing an electron-emitting device in which amorphous silicon is used as the non-single-crystal silicon constituting the emitter: (a) forming a metal thin film for forming an emitter wiring on a substrate, Forming an emitter wiring layer by patterning; (b) forming an amorphous silicon layer on the emitter wiring layer; (c) forming an etching mask pattern layer on the amorphous silicon layer; (d) reaction Etching until the emitter wiring layer is exposed while sharpening the amorphous silicon layer by reactive ion etching; (e) By sequentially laminating an insulating material and a gate electrode material on the surface of the substrate on the emitter wiring layer side. Forming an insulating layer and a gate electrode on the emitter wiring layer and etching Forming an insulating material layer and a gate electrode material layer on the mask pattern layer; and (f) using an etching solution for the etching mask pattern layer to remove the etching mask pattern layer as the lift-off material, and then There is provided a manufacturing method including a step of peeling off the insulating material layer and the gate electrode material layer which are stacked.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional perspective view of the electron-emitting device of the present invention. As shown in the figure, this electron-emitting device has a structure in which a substrate 1, an emitter wiring layer 2, an insulating layer 4, and a gate electrode 5 are sequentially stacked. Further, an opening A reaching the emitter wiring layer 2 is provided in the gate electrode 5 and the insulating layer 4, and a cone type of non-single crystal silicon is formed on the emitter wiring layer 2 in the opening A. The emitter 3 is formed so as not to contact the gate electrode 5.

In the present invention, the substrate 1 is used as a supporting substrate for an electron-emitting device, and an insulating substrate whose area can be easily enlarged can be preferably used. As such an insulating substrate, a quartz substrate, a ceramic substrate,
A glass substrate or the like can be used. A substrate having an insulating film formed on the surface of single crystal Si can also be used.

The emitter wiring layer 2 is formed of a material having a low wiring resistance and a good adhesion to the substrate 1. Further, it is formed of a material having resistance to RIE used when forming the emitter 3 described later and an etching solution used, for example, an alkaline etching solution or etching with buffered hydrofluoric acid. This is because the emitter wiring layer 2 functions as an etching stopper at the time of forming the emitter. As such a material, Cr or Al / Cr alloy can be particularly preferably cited.

The thickness of the emitter wiring layer 2 is not particularly limited as long as sufficient wiring resistance and adhesion can be obtained, but it is usually 0.05 to 0.5 μm, preferably 0.1 to 0.3 μm.
m.

The emitter 3 is a member that directly emits electrons from the surface thereof. In the present invention, non-single crystal silicon, for example, polysilicon having a resistivity of about 10 ⁵ Ω · cm or a resistivity of 10 ^{-1 is used.} Amorphous silicon of about 10 ¹⁰ Ω · cm is used. Therefore, it also functions as a resistance layer when driving the element, and the emission current can be stabilized.

Here, the amorphous silicon used in the present invention means silicon in which a peak showing crystallinity is not observed in the analysis by the thin film X-ray diffraction method. Therefore, amorphous silicon includes silicon that is partially microcrystalline.

The resistivity of amorphous silicon can be easily controlled by adjusting the type of dopant and the dose amount of the silicon sputter target used during the film formation.

Further, when hydrogenated amorphous silicon is used as the amorphous silicon, it becomes possible to obtain an electron-emitting device which is excellent in both structural controllability and electrical characteristics as described below.

First, in terms of structural control, hydrogenated amorphous silicon has an amorphous state in which microcrystals are particularly small as compared with ordinary amorphous silicon, so that more uniform etching is possible when forming a cone by RIE. Therefore, the process tolerance is increased, and it is easy to increase the area. Regarding the electrical characteristics, the doping of impurities becomes easier, and the impurity control comparable to that of single crystal silicon becomes possible. Therefore, the resistance value control in a wide range becomes easy. In particular, a highly concentrated phosphorus-doped hydrogenated amorphous silicon film exhibits n-type conductivity, and it is possible to reduce the specific resistance to several Ω · cm or more. This makes it possible to increase the emission current of the electron-emitting device and reduce the emission voltage.

The thickness (height) of the emitter 3 can be appropriately determined as necessary, but is usually 0.5 to 1.5 μm.
m is preferable.

The insulating layer 4 is a layer for electrically insulating the emitter wiring layer 2 and the gate electrode 5. Such an insulating layer 4 can be formed of a known material used as an insulating layer of an electron-emitting device, but silicon oxide that exhibits good insulating properties and can be formed by an anisotropic vapor deposition method is used. Can be mentioned.

The thickness of the insulating layer 4 is as follows:
It is sufficient that sufficient insulation is maintained between the gate electrode 5 and the gate electrode 5, for example, 0.2 to 2 μm, preferably 0.3 to 0.
7 μm.

The gate electrode 5 is an electrode for concentrating a strong electric field on the emitter 3. As a material of the gate electrode 5, a material having a high melting point from the viewpoint of heat resistance and having resistance to an etching solution used for forming an emitter can be used, and preferably Cr, W, Ta or Nb is used. be able to. Especially, it is preferable to use Nb.

The thickness of the gate electrode 5 can be appropriately determined according to need, but is 0.1 to 0.5 μm.

Next, a method of manufacturing an electron-emitting device of the present invention using polysilicon as non-single crystal silicon will be described with reference to FIG.
Will be described in detail.

Step (a) First, a metal thin film for emitter wiring is formed on the substrate 1 and then patterned into a predetermined shape by photolithography to form an emitter wiring layer 2 (FIG. 2A). In this case, as the emitter wiring layer 2, a Cr film or an Al / Cr alloy film formed by a sputtering method can be preferably used.

Step (b) Next, a polysilicon layer 3a is formed on the emitter wiring layer 2 (FIG. 2B). In this case, in order to form the polysilicon layer 3a, first, it is preferable that amorphous silicon or polysilicon is formed on the emitter wiring layer 2 by a sputtering method capable of forming a film in a temperature range from room temperature to about 300 ° C. When the film is formed at such a temperature, the thermal expansion of the substrate 1 can be kept within a small range, so that the glass substrate can be used and the characteristics of the plurality of electron-emitting devices in the substrate are made uniform. be able to.

Subsequently, the amorphous silicon or the polysilicon thus formed on the emitter wiring layer 2 is replaced with 2
Anneal under high vacuum at a temperature of 00 ° C. or higher. As a result, the amorphous silicon is converted into polysilicon, the crystallinity of the polysilicon is improved, and the polysilicon layer 3a suitable for the emitter is formed.

Step (c) Next, an etching mask material is formed on the polysilicon layer 3a by a vapor deposition method, a sputtering method or the like, and is patterned into a circle by using a photolithography method to form an etching mask pattern layer. 6 (FIG. 2)
(C)).

As the etching mask pattern layer 6,
It is formed of a material having resistance to RIE described later. As such a material, preferably Cr or SiO
_{There are two} .

The diameter of the circular pattern is set to about 1.0 to 2.0 μm in consideration of the characteristics of the electron-emitting device, the difficulty of the operation according to the design rule of the photolithography method, the yield of the etching process, and the like. Is preferred.

Step (d) Next, the polysilicon layer 3a is etched by RIE under the condition that the side etch rate is high until the emitter wiring layer 2 is exposed. As a result, the emitter 3 whose tip is not sharpened is formed (FIG. 2D). Such R
As an example of the IE conditions, [introduced gas SF ₆ , O _2, etc .: 3
0-70 sccm / power 80-120 W / gas pressure 4-
5 Pa] can be shown.

Step (e) Next, on the surface of the substrate 1 on the emitter wiring layer 2 side, SiO 2 is formed.
By stacking an insulating material such as _x and a gate electrode material such as Nb by a vapor deposition method or the like, an insulating layer 4 and a gate electrode 5 are formed on the emitter wiring layer 2, and an etching mask pattern layer 6 is formed. The insulating material layer 4a and the gate electrode material layer 5a are formed (FIG. 2E). here,
When the insulating layer 4 is formed by a vapor deposition method, oxygen gas containing about 10% ozone as a reaction gas is introduced, and a film is formed by a chimney resistance heating method in which SiO is filled as a vapor deposition material. preferable. The insulating layer 4 formed by such a method shows good insulating properties.

Step (f) Next, the emitter 3 under the etching mask pattern layer 6 is etched with an alkaline etching solution to sharpen the tip. As a result, the laminated body including the etching mask pattern layer 6, the insulating material layer 4a, and the gate electrode material layer 5a laminated thereon is peeled off. As a result, an electron-emitting device having the sharp-edged emitter 3 is obtained (FIG. 2 (f)).

As the alkaline etching solution,
In terms of etching characteristics and alkali metal ion non-contamination,
It is preferable to use a solution or melt of a quaternary ammonium compound. Above all, it is particularly preferable to use the melt of tetramethylammonium hydroxide.

Step (g) Further, if necessary, the gate electrode 5 is patterned into a predetermined shape by a photolithography method to obtain the electron-emitting device of FIG. 2 (g).

Next, a method of manufacturing the electron-emitting device of the present invention using amorphous silicon as the non-single crystal silicon will be described in detail with reference to FIG.

Step (a) First, a metal thin film for emitter wiring is formed on the substrate 1 and then patterned into a predetermined shape by photolithography to form the emitter wiring layer 2 (FIG. 3A). Also in this case, a Cr film or an Al / Cr alloy film formed by the sputtering method can be preferably used as the emitter wiring layer 2.

Step (b) Next, the amorphous silicon layer 3 is formed on the emitter wiring layer 2.
b is formed (FIG. 3B). In this case, the amorphous silicon layer 3b is formed by the sputtering method capable of forming a film in the temperature range of room temperature to 300 ° C.
It is preferable to form a film thereon. When the film is formed at such a temperature, the thermal expansion of the substrate 1 can be kept within a small range, so that the glass substrate can be used and the characteristics of the plurality of electron-emitting devices in the substrate are made uniform. be able to.

Further, in this step, the amorphous silicon layer 3
When b is a hydrogenated amorphous silicon layer, preferably an impurity-doped (particularly phosphorus-doped) hydrogenated amorphous silicon layer, it is preferable to use a plasma CVD method instead of the sputtering method.
Here, as an example of film forming conditions of the phosphorus-doped amorphous silicon film having a specific resistance of several to several tens Ω · m, [substrate temperature 250 ° C., introduced gas SiH ₄ (diluted with 10% hydrogen) 300
sccm, H ₂ gas 150 sccm, PH ₃ gas (100
0 ppm hydrogen dilution) 90 sccm, power 60 W, gas pressure 1 Torr].

Step (c) Next, an etching mask material is formed on the amorphous silicon layer 3b by a vapor deposition method, a sputtering method or the like, and is patterned into a circle by using a photolithography method to form an etching mask pattern layer. 6 is formed (FIG. 3C).

As the etching mask pattern layer 6,
It is formed of a material having resistance to RIE described later. As such a material, preferably Cr or SiO
_{There are two} .

The diameter of the circular pattern is set to about 1.0 to 2.0 μm in consideration of the characteristics of the electron-emitting device, the difficulty of the operation according to the design rule of the photolithography method, the yield of the etching process, and the like. Is preferred.

Step (d) Next, the amorphous silicon layer 3b is etched by RIE under the condition that the side etch rate is high until the emitter wiring layer 2 is exposed. As a result, the emitter 3 having a sharpened tip is formed (FIG. 3D). This is because the entire amorphous silicon layer is isotropically etched. As an example of such RIE conditions,
[Introduced gas SF ₆ , O _2, etc .: 30 to 70 sccm / power 80 to 120 W / gas pressure 4 to 5 Pa] can be shown. In particular, by using a mixed gas of SF ₆ : O ₂ = 3: 1 (flow rate ratio), the etching surface of the amorphous silicon layer becomes flat, and the emitter 3 having a substantially triangular pyramid shape can be formed.

Step (e) Next, on the surface of the substrate 1 on the emitter wiring layer 2 side, SiO 2 is formed.
By stacking an insulating material such as _x and a gate electrode material such as Nb by a vapor deposition method or the like, an insulating layer 4 and a gate electrode 5 are formed on the emitter wiring layer 2, and an etching mask pattern layer 6 is formed. The insulating material layer 4a and the gate electrode material layer 5a are formed (FIG. 3E). here,
When the insulating layer 4 is formed by a vapor deposition method, oxygen gas containing about 10% ozone as a reaction gas is introduced, and a film is formed by a chimney resistance heating method in which SiO is filled as a vapor deposition material. preferable. The insulating layer 4 formed by such a method shows good insulating properties.

Step (f) Next, the etching mask pattern layer 6 as the lift-off material is removed by etching using a buffered hydrofluoric acid solution.
As a result, the stacked body composed of the insulating material layer 4a and the gate electrode material layer 5a stacked thereon is peeled off. As a result, an electron-emitting device having a sharp tip emitter 3 is obtained (FIG. 3 (f)).

Step (g) Further, if necessary, the gate electrode 5 is patterned into a predetermined shape by a photolithography method to obtain the electron-emitting device of FIG. 3 (g).

As described above, in the electron-emitting device of the present invention, non-single crystal silicon such as polysilicon or amorphous silicon is used as the emitter material instead of single crystal Si. In addition, an emitter wiring made of a metal material that is less likely to be etched than non-single-crystal silicon is provided below the non-single-crystal silicon layer formed to form the emitter. Therefore, the emitter used in the electron-emitting device of the present invention is R having a high side etch rate.
By IE and wet etching performed as required, a cone-shaped shape with a sharp tip is formed. As described above, in the present invention, since the emitter is formed without using the anisotropic vapor deposition method, the uniformity of the characteristics of the plurality of electron-emitting devices in the substrate can be maintained.

Further, since the non-single crystal silicon layer can be easily formed by film formation at a low temperature and annealing treatment if necessary, it is possible to use a glass substrate which can be easily enlarged as a substrate. Therefore, the electron-emitting device of the present invention is
It is possible to dispose on a large-area substrate with uniform device characteristics.

[0068]

EXAMPLES A production example of the electron-emitting device of the present invention will be specifically described in the following examples.

The first embodiment is an example in which the emitter is made of polysilicon, and the second embodiment is an example in which the emitter is made of amorphous silicon.

Example 1 Step (a) First, Cr was sputter-deposited on the glass substrate 1 as the material of the emitter wiring layer 2 to a film thickness of about 0.2 μm. continue,
The emitter wiring layer 2 was patterned into a matrix wiring shape by the photolithography method (FIG. 2A).

Step (b) Next, a silicon film was formed on the emitter wiring layer 2 with silicon as a target. Further, vacuum annealing was performed at 300 ° C. for 1 hour using a lamp annealing furnace. As a result, the silicon film was polyized to become the polysilicon layer 3a for the emitter (FIG. 2B).

Step (c) Next, Cr is deposited to a thickness of about 0.3 μm by a sputtering method, and then patterned by photolithography into a circular mask shape having a diameter of 2 μm for forming an emitter, thereby etching. A mask pattern layer 6 was formed (FIG. 2 (c)).

Step (d) Next, the polysilicon film 3 is formed by RIE (introduced gas: SF ₆ 40 sccm / power 100 W / gas pressure 4.5 Pa).
A was etched for 3 minutes (FIG. 2D).

Step (e) Next, a silicon oxide film having a thickness of about 0.7 μm (deposition source: SiO, reaction gas: oxygen + 10% ozone, deposition vacuum degree: 5 × 10 ⁻⁶ Torr) is deposited as an insulating layer 4. Then, Nb as a material for the gate electrode was vapor-deposited thereon in a thickness of about 0.3 μm. As a result, the insulating layer 4 and the gate electrode 5 located around the emitter 3 could be formed in a self-aligned manner with a slight gap with respect to the emitter 3 without contacting the emitter 3.

Step (f) The material obtained in the step (e) was immersed in a tetramethylammonium hydroxide melt (liquid temperature 80 ° C.) for 1 minute for etching, and the lower layer of the etching mask pattern layer 6 was obtained. The tip of the emitter 3 is sharpened, and as a result, the etching mask pattern layer 6 and the insulating material layer 4a are formed thereon.
And the laminated body of the gate electrode material layer 5a was peeled off. As a result, the electron-emitting device shown in FIG. 2 (f) was obtained.

Step (g) Next, the Nb film of the gate electrode 5 was patterned into a matrix wiring shape by photolithography to obtain an electron-emitting device as shown in FIG. 2 (g).

An array in which 200 electron-emitting devices described above were integrated was prototyped and tested and evaluated as follows. That is, a glass plate member having a transparent electrode (anode) coated with a phosphor is opposed to an element having a structure in which the distance between the emitter electrode and the gate electrode of each element is about 1 μm at a distance of 30 mm, and the emitter electrode-gate When a voltage was applied between the electrodes with a polarity such that the gate electrode side was positive, electrons could be well emitted.

Example 2 Step (a) First, Cr was sputter-deposited on the glass substrate 1 as the material of the emitter wiring layer 2 to a film thickness of about 0.2 μm. continue,
The emitter wiring layer 2 was patterned into a matrix wiring shape by the photolithography method (FIG. 3A).

Step (b) Next, an amorphous silicon layer 3b having a thickness of 1 μm was formed on the emitter wiring layer 2 with silicon as a target (FIG. 3B).

Step (c) Next, silicon oxide is deposited to about 0.2 μm by reactive vapor deposition.
Thick film, and then by photolithography,
An etching mask pattern layer 6 was formed by patterning into a circular mask shape having a diameter of 1.2 μm for forming an emitter (FIG. 3C).

Step (d) Next, RIE (introduced gas: SF _{6 60} sccm and O ₂ 2
The amorphous silicon layer 3b was etched for 3 minutes at 0 sccm / power 100 W / gas pressure 4.5 Pa (FIG. 3 (d)). As a result, the tip of the amorphous silicon layer 3b was sharpened.

Step (e) Next, a silicon oxide film having a thickness of about 0.7 μm (deposition source: SiO, reaction gas: oxygen + 10% ozone, deposition vacuum degree: 5 × 10 ⁻⁶ Torr) is deposited as an insulating layer 4. Then, Nb as a material for the gate electrode was vapor-deposited thereon in a thickness of about 0.3 μm. As a result, the insulating layer 4 and the gate electrode 5 located around the emitter 3 could be formed in a self-aligned manner with a slight gap with respect to the emitter 3 without contacting the emitter 3.

Step (f) The etching mask pattern layer 6 is lifted off by immersing the product obtained in the step (e) in a buffered hydrofluoric acid solution at room temperature for 2 minutes, and the insulating material layer laminated on the etching mask pattern layer 6. The laminated body of 4a and the gate electrode material layer 5a was peeled off. As a result, the electron-emitting device shown in FIG. 3 (f) was obtained.

Step (g) Next, the Nb film of the gate electrode 5 is patterned into an electrode shape by a photolithography method, as shown in FIG.
An electron-emitting device as shown in (g) was obtained.

An array in which 25 electron-emitting devices described above were integrated was manufactured as a prototype and tested and evaluated as follows. That is, the distance between the emitter electrode and the gate electrode of each element is about 0.7 μm.
The glass plate member having a transparent electrode (anode) coated with a fluorescent substance is applied with a voltage of 500 V so as to face the device having the above structure at a distance of 30 mm, and a voltage is applied between the emitter electrode and the gate electrode with a positive polarity on the gate electrode side. When a voltage of 30 V was applied, electron emission started, and a current of 1 μA stably flowed at 80 V.

Example 3 Step (a) First, as the material of the emitter wiring layer 2, Cr was sputter-deposited on the glass substrate 1 to a film thickness of about 0.2 μm. continue,
The emitter wiring layer 2 was patterned into a matrix wiring shape by the photolithography method (FIG. 3A).

Step (b) Next, a plasma CVD method [substrate temperature 250 ° C., introduced gas SiH ₄ (diluted with 10% hydrogen) 30 is formed on the emitter wiring layer 2.
0 sccm, H ₂ gas 150 sccm, PH ₃ gas (10
Phosphorus-doped hydrogenated amorphous silicon layer 3b was formed to a thickness of 1 μm by 90 sccm hydrogen dilution) 90 sccm, power 60 W, gas pressure 1 Torr] (FIG. 3).
(B)).

Step (c) Next, silicon oxide is deposited to a thickness of about 0.2 μm by reactive vapor deposition.
Thick film, and then by photolithography,
An etching mask pattern layer 6 was formed by patterning into a circular mask shape having a diameter of 1.2 μm for forming an emitter (FIG. 3C).

Step (d) Next, RIE (introduced gas: SF _{6 60} sccm and O ₂ 2
The amorphous silicon layer 3b was etched for 3 minutes at 0 sccm / power 100 W / gas pressure 4.5 Pa (FIG. 3 (d)). As a result, the tip of the amorphous silicon layer 3b was sharpened.

Step (e) Next, a silicon oxide film having a thickness of about 0.7 μm (deposition source: SiO, reaction gas: oxygen + 10% ozone, deposition vacuum degree: 5 × 10 ⁻⁶ Torr) is deposited as an insulating layer 4. Then, Nb as a material for the gate electrode was vapor-deposited thereon in a thickness of about 0.3 μm. As a result, the insulating layer 4 and the gate electrode 5 located around the emitter 3 could be formed in a self-aligned manner with a slight gap with respect to the emitter 3 without contacting the emitter 3.

Step (f) The etching mask pattern layer 6 is lifted off by immersing the product obtained in the step (e) in a buffered hydrofluoric acid solution at room temperature for 2 minutes, and the insulating material layer laminated thereon. The laminated body of 4a and the gate electrode material layer 5a was peeled off. As a result, the electron-emitting device shown in FIG. 3 (f) was obtained.

Step (g) Next, the Nb film of the gate electrode 5 is patterned into an electrode shape by a photolithography method, as shown in FIG.
An electron-emitting device as shown in (g) was obtained.

An array in which 25 electron-emitting devices described above were integrated was manufactured as a prototype and tested and evaluated as follows. That is, the distance between the emitter electrode and the gate electrode of each element is about 0.7 μm.
The glass plate member having a transparent electrode (anode) coated with a fluorescent substance is applied with a voltage of 500 V so as to face the device having the above structure at a distance of 30 mm, and a voltage is applied between the emitter electrode and the gate electrode with a positive polarity on the gate electrode side. When a voltage of 30 V is applied, the phosphor emits light to start electron emission, and as shown in FIG.
A current of μA steadily flowed.

[0094]

According to the present invention, when forming the cone-shaped shape of the emitter of the electron-emitting device, the reactive ion etching method or the like is used without utilizing anisotropic deposition, so that a sharp tip can be formed. Can be formed. Moreover, it is possible to use a substrate other than the single crystal Si substrate that can be easily enlarged, such as a glass substrate, and even if the substrate is enlarged, it is possible to maintain the uniformity of electron-emitting device characteristics within the substrate. it can.

Therefore, it is possible to obtain an electron-emitting device capable of operating at a low voltage over a large area. Further, when applied to a flat panel display, a high-quality image on a large screen can be obtained with low power consumption.

[Brief description of the drawings]

FIG. 1 is a schematic sectional perspective view of an electron-emitting device of the present invention.

FIG. 2 is a manufacturing process diagram of an electron-emitting device of the present invention.

FIG. 3 is a manufacturing process diagram of an electron-emitting device of the present invention.

FIG. 4 is a schematic sectional perspective view of a conventional electron-emitting device.

FIG. 5 is a manufacturing process diagram of a conventional electron-emitting device.

FIG. 6 is a manufacturing process diagram of another conventional electron-emitting device.

FIG. 7 is an electrical characteristic diagram of the electron-emitting device of the present invention.

[Explanation of symbols]

 1 Glass Substrate 2 Emitter Wiring Layer 3 Emitter 3a Polysilicon Layer 3b Amorphous Silicon Layer 4 Insulating Layer 5 Gate Electrode 6 Etching Mask Pattern Layer 41 Conductive Layer 42 Insulating Layer 43 Gate Electrode 44 Emitter 51 Substrate 52 Emitter Wiring 53 Insulating Layer 54 Gate Electrode 55 Lift-off material 56 Emitter 61 Single crystal Si substrate 62 Silicon oxide layer for etching mask 63 Emitter 64 Silicon oxide layer for sharpening emitter tip 65 Insulating film 66 Gate electrode A Opening

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masago Kanamaru 1-4-1 Umezono, Tsukuba-shi, Ibaraki Electronic Technology Research Institute, Industrial Technology Institute (72) Inventor Junji Ito 1-4-1, Umezono, Tsukuba-shi, Ibaraki Industrial Technology Research Institute, AIST

Claims (20)

[Claims] 1. A substrate, an emitter wiring layer, an insulating layer, and a gate electrode are sequentially laminated, and an opening reaching the emitter wiring layer is provided in the gate electrode and the insulating layer, and the emitter wiring layer in the opening. In a field emission type electron-emitting device having a cone-shaped emitter formed so as not to contact the gate electrode, the emitter wiring layer is formed of a metal thin film, and the emitter is formed of non-single-crystal silicon. An electron-emitting device characterized by being provided. 2. The electron-emitting device according to claim 1, wherein the non-single crystal silicon is polysilicon. 3. The electron-emitting device according to claim 1, wherein the non-single crystal silicon is amorphous silicon. 4. The electron-emitting device according to claim 3, wherein the amorphous silicon is hydrogenated amorphous silicon. 5. The electron emitting device according to claim 3, wherein the amorphous silicon is impurity-doped hydrogenated amorphous silicon. 6. The electron-emitting device according to claim 3, wherein the amorphous silicon is phosphorus-doped hydrogenated amorphous silicon. 7. A Cr thin film or Cr / A as the metal thin film.
The electron-emitting device according to any one of claims 1 to 6, which uses an 1-alloy thin film. 8. The electron-emitting device according to claim 1, wherein a glass substrate is used as the substrate. 9. The method of manufacturing an electron-emitting device according to claim 2, wherein: (a) a step of forming an emitter wiring layer by forming a metal thin film for forming an emitter wiring on a substrate and patterning the metal thin film; ) Step of forming a polysilicon layer on the emitter wiring layer; (c) Step of forming an etching mask pattern layer on the polysilicon layer; (d) Exposing the polysilicon layer and the emitter wiring layer by reactive ion etching. (E) An insulating layer and a gate electrode are formed on the emitter wiring layer by sequentially laminating an insulating material and a gate electrode material on the surface of the substrate on the side of the emitter wiring layer. Forming an insulating material layer and a gate electrode material layer on the etching mask pattern layer; and (f) using an alkaline etching solution, The polysilicon layer located under the etching mask pattern layer is etched to sharpen the tip of the polysilicon layer, and an etching mask pattern layer laminated thereon,
A method of manufacturing an electron-emitting device, comprising a step of stripping an insulating material layer and a gate electrode material layer. 10. The method for manufacturing an electron-emitting device according to claim 9, wherein the formation of the polysilicon layer in the step (b) is performed by forming amorphous silicon or polysilicon on the emitter wiring layer and then annealing it. 11. The method of manufacturing an electron-emitting device according to claim 10, wherein the annealing is performed in a high vacuum at a temperature of 200 ° C. or higher. 12. The method of manufacturing an electron-emitting device according to claim 9, wherein the etching mask pattern layer is formed of Cr or silicon oxide in the step (c). 13. The method of manufacturing an electron-emitting device according to claim 9, wherein a tetramethylammonium hydroxide melt is used as the alkaline etching liquid in step (f). 14. The method of manufacturing an electron-emitting device according to claim 3, wherein: (a) a step of forming a metal thin film for forming an emitter wiring on a substrate and patterning the same to form an emitter wiring layer; (b) A step of forming an amorphous silicon layer on the emitter wiring layer; (c) a step of forming an etching mask pattern layer on the amorphous silicon layer; (d) a sharpening of the amorphous silicon layer by reactive ion etching, and an emitter wiring layer (E) An insulating layer and a gate electrode are formed on the emitter wiring layer by sequentially laminating an insulating material and a gate electrode material on the surface of the substrate on the side of the emitter wiring layer. Together with the step of forming an insulating material layer and a gate electrode material layer on the etching mask pattern layer; and (f A step of removing the etching mask pattern layer as a lift-off material using an etching liquid for the etching mask pattern layer, and peeling off the insulating material layer and the gate electrode material layer laminated on the etching mask pattern layer. Method for manufacturing electron-emitting device. 15. The method of manufacturing an electron-emitting device according to claim 14, wherein the etching mask pattern layer is formed of Cr or silicon oxide in the step (c). 16. The method of manufacturing an electron-emitting device according to claim 14, wherein a buffered hydrofluoric acid solution is used as the etching solution in the step (f). 17. The method of manufacturing an electron-emitting device according to claim 14, wherein a hydrogenated amorphous silicon film is used as the amorphous silicon film in the step (b). 18. The method for manufacturing an electron-emitting device according to claim 14, wherein an impurity-doped hydrogenated amorphous silicon film is used as the amorphous silicon film. 19. The method of manufacturing an electron-emitting device according to claim 14, wherein a phosphorus-doped hydrogenated amorphous silicon film is used as the amorphous silicon film. 20. The amorphous silicon film is formed by a plasma CVD method in the step (b).
10. The method for manufacturing an electron-emitting device according to any of 9.