WO2000079556A1 - Emitter, emitter fabricating method, and cold electron emitting device fabricating method - Google Patents

Emitter, emitter fabricating method, and cold electron emitting device fabricating method Download PDF

Info

Publication number
WO2000079556A1
WO2000079556A1 PCT/JP2000/004114 JP0004114W WO0079556A1 WO 2000079556 A1 WO2000079556 A1 WO 2000079556A1 JP 0004114 W JP0004114 W JP 0004114W WO 0079556 A1 WO0079556 A1 WO 0079556A1
Authority
WO
WIPO (PCT)
Prior art keywords
emitter
columnar
film
insulating film
polycrystalline film
Prior art date
Application number
PCT/JP2000/004114
Other languages
French (fr)
Japanese (ja)
Inventor
Tetsuya Norikane
Koichi Hiranaka
Naoki Wada
Yasuyo Sato
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to KR1020017002346A priority Critical patent/KR20010072923A/en
Publication of WO2000079556A1 publication Critical patent/WO2000079556A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/304Field-emissive cathodes
    • H01J1/3042Field-emissive cathodes microengineered, e.g. Spindt-type
    • H01J1/3044Point emitters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/022Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes

Definitions

  • the present invention relates to an emitter, a method of manufacturing an emitter, and a method of manufacturing a cold electron emitting device.
  • the present invention relates to a cold electron emission emitter used as an electron source for various electron beam utilizing devices such as a flat panel image display device, various sensors, a high frequency oscillator, an ultra-high speed device, an electron microscope, and an electron beam exposure device. And a method of manufacturing the same.
  • devices such as a flat panel image display device, various sensors, a high frequency oscillator, an ultra-high speed device, an electron microscope, and an electron beam exposure device. And a method of manufacturing the same.
  • the biggest problem with this emitter is that the amount of electron emission fluctuates over time.
  • the method of manufacturing an emitter to solve this problem is roughly divided into the following two methods.
  • One is to form a metal emitter on a glass substrate and connect a large electrical resistance in series with this emitter to stabilize the emission current.
  • Another method is to form a transistor with an emitter using a semiconductor, and to actively control the amount of emission current using this transistor. Things. This method has low power consumption and high operating speed, and is expected to be developed in the future.
  • the following three types of emitter material films can be considered.
  • One is a single crystal film with no grain boundaries and the crystal orientation is aligned in a fixed direction in every part.
  • a transistor having excellent characteristics is to be formed, it is preferable to use a single crystal film or a polycrystalline film.
  • a polycrystalline film is less expensive to manufacture than a single crystal film, and can be manufactured on a large-scale tomb plate at a low temperature. Suitable for.
  • FIG. 10 is a cross-sectional view of the conventional polycrystalline film substrate.
  • FIG. 11 is a cross-sectional view of an emitter manufactured using the polycrystalline film of FIG. is there.
  • reference numeral 1 denotes a substrate made of, for example, glass or the like, on which a polycrystalline film 14 composed of fine crystal grains 13 having different crystal orientations and grains g is formed.
  • a polycrystalline film 14 composed of fine crystal grains 13 having different crystal orientations and grains g is formed.
  • An emitter 15 manufactured using the polycrystalline film 14 shown in FIG. 11 is made of a polycrystalline structure composed of fine crystal grains 13 having different crystal orientations and grain sizes on a substrate 1 such as glass.
  • the film 14 can be formed by etching.
  • the transistor and the cold electron-emitting device having good characteristics are manufactured at a low process temperature. Therefore, a large-area inexpensive glass substrate can be used. As a result, the manufacturing cost of the emitter 15 can be reduced.
  • the emitter 15 formed using the polycrystalline film 14 has a problem that the electron emission characteristics vary. This is because the crystal grain size of the polycrystalline film subjected to the etching process varies, and the crystal orientation and the crystal orientation plane of each crystal grain are greatly different. The isotropic or anisotropic etching rate differs from crystal grain to grain boundary.
  • the present invention has been made to solve such a problem. Even when a large number of emitters are formed, the uniformity of the shape of the emitter can be obtained with good reproducibility, and the shape of the emitter can be improved. It is an object of the present invention to provide an emitter capable of suppressing variations in electron emission characteristics caused by fluctuations in electron emission, and a method for manufacturing the same. Disclosure of the invention
  • An emitter according to claim 1 of the present invention is characterized in that columnar crystal grains are formed on a substrate by etching a columnar polycrystalline film grown along the same crystal axis. It is assumed that. This allows Emi Even when a large number of emitters are formed, uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the emitter shape can be suppressed.
  • the emitter according to claim 2 of the present invention forms a columnar polycrystalline film in which columnar crystal grains are grown along the same crystal axis on a substrate, and then forms the columnar polycrystalline film on the columnar polycrystalline film.
  • the method is characterized in that the first insulating film is patterned, and the columnar polycrystalline film is etched using the patterned first insulating film.
  • the emitter according to claim 3 of the present invention forms a second insulating film on the substrate, and grows columnar crystal grains on the second insulating film along the same crystal axis.
  • the first insulating film is patterned on the columnar polycrystalline film, and the columnar polycrystalline film is etched using the patterned first insulating film. It is characterized by forming by applying. As a result, even when a large number of emitters are formed, the uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the shape of the emitter can be suppressed. .
  • the emitter according to claim 4 of the present invention is the emitter according to any one of claims 1 to 3, wherein the columnar polycrystalline film is formed by:
  • the constituent columnar crystal grains are characterized in that the crystal orientation and the crystal plane are aligned in a certain direction with respect to the substrate surface.
  • the EMI according to claim 5 of the present invention is the EMI according to any one of claims 1 to 4, wherein the columnar polycrystalline film has at least Both are characterized by containing silicon.
  • columnar polycrystals can be realized on a human area substrate by a low-temperature process of 500 ° C. or less. Therefore, columnar polycrystals can be etched in a uniform shape on a large-area substrate, and even when a large number of emitters are formed on a human-area substrate, uniformity of the emitter shape can be obtained with good reproducibility. Variations in the electron emission characteristics caused by variations in the shape of the light source can be suppressed.
  • the EMI according to claim 6 of the present invention is the EMI according to any one of claims 1 to 5, wherein the orientation of the columnar polycrystalline film is The surface is characterized by being ⁇ 1 1 0 ⁇ .
  • the crystal orientation and the crystal plane can be easily aligned, so that uniform etching can be performed, and the uniformity of the emitter shape can be obtained with good reproducibility.
  • the emitter according to claim 7 of the present invention is the emitter according to any one of claims 1 to 5, wherein the columnar polycrystalline The orientation surface of the film is ⁇ 100 ⁇ .
  • the crystal orientation and the crystal orientation can be easily aligned, so that uniform etching can be performed, the uniformity of the emitter shape can be obtained with good reproducibility, and the variation of the emitter shape can be caused.
  • Variation in electron emission characteristics can be suppressed.
  • the barrier at the crystal grain boundaries can be suppressed: and the trap level formed at the interface with the insulating film can be further reduced. Therefore, the mobility of traveling electrons is increased, and efficient emission can be realized.
  • the emitter according to claim 8 of the present invention is characterized in that, in the emitter according to any one of claims 1 to 7, the columnar polycrystalline film is etched.
  • the radius of curvature of the tip of the formed emitter is 50 nm or less.
  • the emitter according to claim 9 of the present invention is the emitter according to any one of claims 1 to 8,
  • the columnar crystal grains constituting the crystal film are characterized in that the shorter grain size of the columnar crystal grains is at least 100 nm or more.
  • the number of crystal grain boundaries at the tip of the emitter which may cause variations in etching, is reduced, uniform etching is possible, and uniformity of the emitter shape is obtained with good reproducibility. Variations in electron emission characteristics due to variations in the evening shape can be suppressed.
  • the emitter according to claim 10 of the present invention is the emitter according to claim 9, wherein the angle formed by the columnar crystal grains and the substrate is 83 ° or more. It is characterized by the following. As a result, the number of crystal grain boundaries at the leading edge of the emitter, which may cause unevenness in etching, is reduced, etching with a more uniform shape is enabled, and uniformity of the emitter shape is obtained with good reproducibility. Variations in electron emission characteristics due to variations in the shape of the emitter can be suppressed.
  • the emitter according to claim 11 of the present invention is the emitter according to claim 3, wherein the second insulating film is formed of at least oxygen or nitrogen. It is characterized by including. This suppresses the diffusion of impurities from the glass into the columnar polycrystal, provides a columnar polycrystal with excellent crystallinity, and achieves uniformity of the emitter shape with good reproducibility, as well as the emitter shape. Variations in electron emission characteristics due to fluctuations in electron emission characteristics can be suppressed.
  • the emitter according to claim 12 of the present invention is the emitter according to claim 2 or claim 3, wherein the patterned first insulating film is used. Is characterized by having a circular shape. Thus, by etching the columnar polycrystalline film, a sharp-edged emitter can be easily realized.
  • the emitter described in claim 13 of the present invention is the emitter described in claim 2 or claim 3, wherein The first insulating film has a polygonal shape.
  • the exposure accuracy of the lithography can be improved, and the cost of the exposure mask can be reduced.
  • the method for manufacturing an emitter according to claim 14 of the present invention includes a step of forming a columnar polycrystalline film in which columnar crystal grains are grown along the same crystal axis on a substrate; And a column for etching the columnar polycrystalline film.
  • the method for manufacturing an emitter according to claim 15 of the present invention includes a step of forming a columnar polycrystalline film in which columnar crystal grains are grown along the same crystal axis on a substrate; Patterning a first insulating film on the columnar polycrystalline film; and etching the columnar polycrystalline film using the patterned first insulating film. is there.
  • uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the emitter shape can be suppressed.
  • the step of forming a second insulating film on the substrate and the step of forming columnar crystal grains on the second insulating film in the same crystal Forming a columnar polycrystalline film grown along the axis, patterning a first insulating film on the columnar polycrystalline film, using the first insulating film that has been buttered. And etching the columnar polycrystalline film.
  • the method for producing an emitter according to claim 17 of the present invention is a method for producing an emitter according to any one of claims 14 to 16 of the present invention.
  • the columnar crystal grains constituting the columnar polycrystalline film correspond to the substrate surface.
  • the crystal orientation and the crystal plane are aligned in a certain direction.
  • the method for producing an emitter according to claim 18 of the present invention includes the method for producing an emitter according to any one of claims 14 to 17 and claim 17.
  • the columnar polycrystalline film contains at least silicon.
  • columnar polycrystals are formed on a large area substrate at 500. It can be realized by a low temperature process of C or lower. Therefore, columnar polycrystals can be etched on a large-area substrate in a uniform shape, and even when many emitters are formed on a large-area substrate, uniformity of the emitter shape can be obtained with good reproducibility. Variations in the electron emission characteristics due to variations in the shape of the emitter can be suppressed.
  • the method for producing an emitter according to claim 19 of the present invention is the method for producing an emitter according to any one of claims 14 to 18,
  • the orientation plane of the columnar polycrystalline film is ⁇ 110 ⁇ .
  • the method for manufacturing an emitter according to claim 20 of the present invention is the method for manufacturing an emitter according to any one of claims 14 to 18.
  • the orientation plane of the columnar polycrystalline film is ⁇ 100 ⁇ .
  • the crystal orientation and the crystal plane are easily aligned, so that uniform etching can be performed, the uniformity of the emitter shape can be obtained with good reproducibility, and the electron emission caused by the fluctuation of the emitter shape can be achieved. Variations in emission characteristics can be suppressed.
  • obstacles at crystal grain boundaries can be suppressed, and trap levels formed at the interface of the insulating film can be reduced. Therefore, the mobility of the traveling electrons increases and the efficiency increases. It is possible to manufacture new emitters.
  • the method for producing an emitter according to claim 21 of the present invention includes the method for producing an emitter according to any one of claims 14 to 20.
  • the method is characterized in that the columnar polycrystalline film is etched so that the radius of curvature at the tip of the emitter is 50 nm or less. As a result, the field concentration at the tip of the emitter can be increased, and electrons can be emitted at a low voltage.
  • the method for producing an emitter according to claim 22 of the present invention is the method for producing an emitter according to any one of claims 14 to 21.
  • the columnar crystal grains in the columnar crystal film are characterized in that the shorter one of the columnar crystal grains has a particle size of at least 100 nm or more.
  • the method for producing an emitter according to claim 23 of the present invention is the method for producing an emitter according to claim ffl, wherein the angle between the columnar crystal grains and the substrate is Is characterized by being at least 83 °.
  • the number of grain boundaries at the tip of the emitter which may cause unevenness in etching, is reduced, the etching is made more uniform, and the uniformity of the emitter is obtained with good reproducibility. Variations in electron emission characteristics due to variations in the shape of the light can be suppressed.
  • an emitter manufacturing method is the emitter manufacturing method according to claim 16, wherein the second insulating film is at least , Characterized by containing oxygen or nitrogen. This suppresses the diffusion of impurities from the glass into the columnar polycrystals, provides columnar polycrystals with excellent crystallinity, and achieves uniform emitter shape with good reproducibility and changes in emitter shape. It is possible to suppress the variation in the electron emission characteristics caused by this.
  • the method for producing an emitter according to claim 25 of the present invention the method for producing an emitter according to claim 15 or claim 16 is provided.
  • the thinned first insulating film has a circular shape. Thus, by etching the columnar polycrystalline film, an emitter having a sharp tip can be easily realized.
  • the method for manufacturing an emitter according to claim 26 of the present invention is the same as the method for manufacturing an emitter according to claim 15 or claim 16.
  • the patterned first insulating film has a polygonal shape.
  • a method for manufacturing a cold electron emitting device according to claim 27 of the present invention is provided by the method for manufacturing an emitter according to claim 15 or claim 16.
  • the extraction gate electrode can be easily formed without using a photolithography process, and the manufacturing cost of the cold electron emission device can be reduced.
  • FIG. 1 is a sectional view of a columnar polycrystalline substrate according to Embodiment 1 of the present invention.
  • FIG. 2 is a process cross-sectional view of a method for manufacturing a cold electron emission wire using the columnar polycrystalline substrate shown in FIG.
  • FIG. 3 is a Raman spectrum of the columnar polycrystalline substrate according to the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a columnar polycrystalline substrate provided with an underlayer according to Embodiment 2 of the present invention.
  • FIG. 5 is a cross-sectional view of a columnar polycrystalline substrate according to Embodiments 3 and 5 of the present invention, in which crystal orientations and crystal planes are aligned in a certain direction.
  • FIG. 6 is a cross-sectional view of a cold electron emission device according to Embodiment 4 of the present invention.
  • FIG. 7 is a diagram showing an amount of electrons emitted from a cold electron emission element due to a difference in film structure according to a sixth embodiment of the present invention.
  • FIG. 8 is an XRD spectrum of a ⁇ 110 ⁇ -oriented columnar polycrystalline silicon film.
  • FIG. 9 is a diagram illustrating the relationship between the electric field intensity applied to the emitter tip and the curvature half S of the emitter tip.
  • FIG. 10 is a sectional view of a polycrystalline film according to the prior art.
  • the first is a cross-sectional view of an emitter using a polycrystalline film according to the prior art.
  • Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2.
  • FIG. 1 is a cross-sectional view of a columnar polycrystalline substrate according to Embodiment 1 of the present invention
  • FIG. 2 is a process cross-section of a method of manufacturing an emitter and a cold electron emitting device according to Embodiment 1 of the present invention.
  • reference numeral 1 denotes a substrate such as glass.
  • 2 is a columnar polycrystalline film.
  • 3 is a crystal grain boundary indicating a boundary between crystal grains.
  • 4 is columnar crystal grains.
  • a plasma chemical vapor deposition (PCVD) method using a 0.1% to 3% silane gas diluted with hydrogen gas as a material gas is formed on a substrate 1 such as a glass shown in FIG. Crystals at temperatures from 200 "C to 350 ° C, deposition pressures from 0.1 Pa to 5 Pa, and RF power from 300 W to 1 kW
  • a columnar polycrystalline film 2 is formed, which is a columnar polycrystalline silicon film having a grain size of about 10 ° nm to about 140 nm having the same orientation and crystal plane.
  • the film grown under these conditions is mainly a columnar polycrystalline film 2 having a ⁇ 110 ⁇ plane orientation.
  • a particle size having a ⁇ 100 ⁇ plane orientation is mainly about 250 nm.
  • the columnar polycrystalline film 2 is obtained.
  • the columnar polycrystalline film 2 having the ⁇ 110 ⁇ plane orientation or the ⁇ 100 ⁇ plane orientation thus produced is a cold electron emitting element having a uniform-shaped emitter, which is an effect of the present invention. Can be realized.
  • the columnar polycrystalline film 2 includes an amorphous layer, a crystallization ratio which is a ratio included in a unit area of the polycrystal and the amorphous is required to form a uniform emitter. Is preferably 80% or more.
  • This crystallization ratio can be measured by, for example, Raman spectroscopy.
  • the crystallization ratio I (520) / ⁇ 1 (520) +1 (480) ⁇ is shown in relation to the intensity I (480 ) of cm— ] (see FIG. 3).
  • typical growth conditions are specified, and a specific flow rate, a gas mixture ratio, a substrate temperature, a film forming pressure, an RF power, and the like are specified using a mixed gas containing silicon.
  • the columnar polycrystalline film 2 can be obtained under the growth conditions having the range described above, and the grain size and size can be changed according to the growth conditions.
  • Fig. 8 shows a plasma chemical vapor deposition (PCVD) method using a mixed gas of silane and hydrogen under the conditions of a substrate temperature of 300 ° C, a deposition pressure of 2 Pa, and an RF power of 300 W.
  • PCVD plasma chemical vapor deposition
  • XRD X-ray diffraction
  • the columnar polycrystalline film 2 oriented on the ⁇ 100 ⁇ plane was formed by a PCVD method using a mixed gas of silane gas and silicon tetrafluoride gas at a substrate temperature of 300 nC and a film forming pressure of 100 nm.
  • FPower obtained when the film is formed under the condition of FP power 300 W, and a beak of (400) is obtained when the 2 ⁇ of the XRD spectrum is about 63.2 ° (not shown). ) Appears.
  • each dot is Pas evening-learning so that the circular or polygonal shape.
  • a PCVD method a sputtering method, an evaporation method, or the like.
  • a first insulating film 5, such as S i 0 2 on the columnar polycrystalline film, each dot is Pas evening-learning so that the circular or polygonal shape.
  • an insulating film is deposited to a thickness of about 200 nm, and the insulating film is processed into a circular or polygonal dot pattern having a diameter of about 1 Aim by a photolithography process. .
  • the columnar polycrystalline film 2 is processed by reactive ion etching (RIE) as shown in FIG. Evening get 6.
  • RIE reactive ion etching
  • a halogen gas such as SF s gas is used if e example.
  • an upper portion is removed from the first insulating film 5 processed into the above-mentioned circular or polygonal dot pattern by a lift-off method, and an opening is formed.
  • the default Although the gate insulating layer 7 and the extraction electrode 8 are removed to form the open U portion by the ⁇ method, it can also be formed by the etch back method.
  • the emitter 6 since the emitter 6 is manufactured by performing etching using the columnar polycrystalline film 2, the crystal orientation and the crystal plane in each columnar crystal grain 4 are formed. Is the same, the isotropic or anisotropic etching rate when wet or reactive ion etching is performed can be made equal in all parts except on the crystal grain boundary 3. Therefore, the emitter 6 can be manufactured with high reproducibility, and uniformity of the shape can be obtained in the emitter 6 formed in a large number over a wide range.
  • the columnar polycrystalline film 2 contains at least silicon (silicon), specifically, a polycrystalline silicon film or polycrystalline silicon germanium.
  • a columnar polycrystalline film can be formed on an area substrate by a low-temperature process of 500 ° C. or less. Therefore, columnar polycrystals can be etched in a uniform shape on a large-area substrate, and even when a large number of emitters are formed on a large-area substrate, the uniformity of the emitter shape can be obtained with good reproducibility, and Variations in the electron emission characteristics due to variations in the shape of the electron beam can be suppressed.
  • FIG. 4 is a sectional view of a columnar polycrystalline substrate according to Embodiment 2 of the present invention.
  • the cold-emitting device according to the second embodiment forms a columnar polycrystalline film 2 in which columnar crystal grains are grown along the same crystal axis after forming an insulating film on a substrate. It differs from the cold electron-emitting device according to the first embodiment in which the columnar polycrystalline film 2 is formed without coating the substrate with an insulating film only in the production of the emitter and the cold electron-emitting device. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • FIG. 4 is a sectional view of a columnar polycrystalline substrate according to Embodiment 2 of the present invention.
  • the cold-emitting device according to the second embodiment forms a columnar polycrystalline film 2 in which columnar crystal grains are grown along the same crystal axis after forming an insulating film on a substrate. It differs from the
  • a second insulating film 9 is formed on a glass substrate 1.
  • the process of forming the second insulating film 9 on the glass substrate 1 is performed, for example, by using silane gas and N 20 gas as a material gas, or a mixed gas of TEOS and oxygen.
  • the substrate temperature was from 200 ° C to 300
  • the deposition pressure was 0.1 Pa to 10 Pa
  • the RF power was 300 W to 500 W by PCVD method.
  • n still deposited 1 0 0 0 nm of the silicon dioxide film S i 0 2 from nm the process of the second insulating film 9 formed later is the same as the above-described first embodiment will be omitted.
  • the second insulating film 9 As described above, by forming the second insulating film 9 on the substrate 1, diffusion of impurities contained in the substrate 1, for example, boron (poron) or sodium, can be suppressed, and the crystal of the columnar polycrystalline film 2 can be suppressed. Performance can be improved.
  • impurities contained in the substrate for example, boron (poron) or sodium
  • the second insulating film 9 is minimum, oxygen or nitrogen is also to a long path and often contains, for example, in addition to the silicon dioxide film S i 0 2, or or a nitride film S i N x, nitrous oxide nitride film Alternatively, n the same effect by using these composite films are obtained
  • FIG. 5 is a cross-sectional view of a columnar polycrystalline film substrate aligned in a certain direction according to Embodiment 3 of the present invention.
  • the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • the columnar polycrystalline grains 4 are aligned such that the crystal orientation and the crystal plane are in a certain direction with respect to one surface of a certain plate.
  • Reference numeral 10 denotes a crystal orientation indicating the direction of each crystal grain.
  • the crystal ⁇ is perpendicular to the crystal orientation 10, and a layer having ⁇ 110 ⁇ is oriented as ⁇ ⁇ ⁇ .
  • the alignment of the columnar polycrystalline grains of the columnar polycrystalline film column can be obtained even if the columnar polycrystalline film 2 contains an amorphous phase, if the crystallization ratio is desirably 80% or more. Note that the processes after the formation of the columnar polycrystalline film substrate composed of the columnar polycrystalline grains 4 having the uniform shape are the same as those in Embodiment 1 described above, and a description thereof will be omitted.
  • the columnar crystal grains 4 in the columnar crystal film 2 have a structure in which the crystal orientation and the crystal plane are aligned in a certain direction with respect to the substrate 1. , Not only within the same crystal grain, but also The etching isotropic or anisotropic etching speed can be made equal in all the crystal grain regions. Therefore, the emitter can be manufactured with good reproducibility, and the uniformity of the shape can be obtained in a large number of emitters.
  • FIG. 6 is a cross-sectional view of an emitter part of a cold electron-emitting device manufactured using columnar polycrystalline film 2 according to Embodiment 4 of the present invention.
  • 11 indicates the shorter particle size of the columnar crystal grains.
  • 6 is the emitter
  • 12 is the tip of the emitter.
  • the same components as those in Embodiment 1 described above are denoted by the same reference numerals, and description thereof will be omitted.
  • the radius of curvature of the emitter tip 12 is 50 nm or more, the emitter tip 12 of the emitter gate electrode 8 (see FIG. 2 (e) above) is used.
  • the drive circuit desirably has a gate voltage of 50 V or less, it is desirable that the radius of curvature of the emitter tip 12 be 50 nm or less.
  • the field strength of the field emission of silicon is needed more than 1 0 6 V / mm, pull-out applies positive voltage V (V) with respect to E Mi Tsu evening and E Mi jitter and the gate electrode
  • V positive voltage
  • the electric field strength at the tip of the emitter is expressed by equation (1).
  • FIG. 9 shows the relationship between the field intensity F and the radius of curvature of the radius of curvature Emi at the tip of 100 (V).
  • V 0.5 X 10 0 16 (m)
  • V 60, 80
  • FIG. 9 shows the relationship between the field intensity F and the radius of curvature of the radius of curvature Emi at the tip of 100 (V).
  • the condition of V> 80 V and r ⁇ 50 nm must be satisfied to obtain F of 10 G V / mm or more. So
  • the larger r is, in order to make a 1 0 6 V / mm or more electric field emitter Tsu evening tip, requires extra voltage, conversely, r is small lever, the voltage is low Help me.
  • an inexpensive low-voltage drive circuit can be provided by setting the tip curvature to 50 nm or less.
  • the radius of curvature of the emitter tip 12 can be extremely reduced to 50 nm or less, for example, several nm or less according to reactive etching using ordinary halogen gas or wet etching including hydrofluoric acid. It is very difficult to make the shape as sharp as this, usually about 50 nm. Therefore, by forming the shorter grain size 11 of the columnar crystal grains to be 100 nm or more, a cold electron emitting device having a uniform-shaped emitter can be realized.
  • the radius of curvature of the emitter tip 12 is about 50 nrn, if the shorter grain size 11 of the columnar crystal grains is smaller than 100 nm, the grain boundary The probability (possible) that 3 is located at the emitter tip becomes higher, and the emitter tip 12 having a radius of curvature of about 50 nm will not be formed with good reproducibility due to grain boundaries. .
  • the crystal grain boundary 3 has many defects, and if the defect is located at the tip 12 of the emitter, the amount of emitted electrons decreases.
  • the shorter grain size 11 of the columnar crystal grains is preferably formed to be 100 nm or more.
  • the shorter particle size 11 of the columnar crystal grains is at least 100 nm or more, the etching is performed at the tip 12 of the emitter. Since there are no crystal grain boundaries having different velocities, it becomes possible to form the emitter end 11 with good reproducibility.
  • FIG. 5 the same components as those in the above-described third embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • 10 is a crystal orientation indicating the direction of each crystal grain.
  • Each crystal grain 4 is formed at an angle of 83 ° or more with respect to substrate 1.
  • the thickness of the columnar polycrystalline film 2 having a grain size of at least 0.1 Aim must be at least about 0.8 ⁇ m.
  • tan ' 1 (0.8 / 0.1) 83 ° is required.
  • each crystal grain 4 is formed at an angle of not less than 83 ° with respect to substrate 1, crystal grains having different etching speeds are formed at the tip of the emitter. There is no field, and the emitter tip 11 can be formed with good reproducibility. Further, a cold electron-emitting device having excellent electron emission characteristics can be obtained.
  • Embodiment 6 of the present invention will be described with reference to FIGS. 1 and 7.
  • FIG. 1 has been described in the first embodiment, the description of each component will be omitted.
  • the crystal plane of the columnar crystal grain 4 was ⁇ 110 ⁇ or ⁇ 100 ⁇ plane oriented.
  • the ⁇ 110 ⁇ plane orientation is achieved by setting the orientation plane of the columnar polycrystalline film 2 to ⁇ 110 ⁇ so that the crystal orientation and the crystal plane can be easily aligned, and therefore, a uniform shape etching can be performed. This realizes a cold electron-emitting device having an emitter with excellent uniformity on a large-area substrate.
  • the orientation plane to ⁇ 110 ⁇ or ⁇ 100 ⁇ plane orientation
  • the electrons in the columnar polycrystalline film 2 are transported by the grain boundaries when traveling through the semiconductor layer.
  • the energy barrier of the child motion can be reduced, the mobility can be increased, and as a result, the amount of emitted electrons can be increased and a fast response can be realized.
  • the ⁇ 100 ⁇ plane orientation is used to lower the crystal grain boundary barrier and facilitate the flow of electrons as compared with the ⁇ 110 ⁇ plane orientation. This is because the number of carrier traps at the interface between the gate insulating layer and the surface of the semiconducting insulator is smaller than in the ⁇ 110 ⁇ plane orientation, and electrons at the interface between the conductor and the insulating layer are more likely to flow. As a result, the mobility is further increased, and as a result, the amount of emitted electrons can be increased and a fast response can be realized.
  • FIG. 7 shows the measured amount of electrons emitted from an emitter of 1,000 chips due to the difference in crystal structure, which was implemented in the present invention.
  • the voltage applied to the extraction gate electrode is the same.
  • the amount of emitted electrons is more than twice as large as that of amorphous silicon. I have.
  • the amount of emitted electrons is related to the luminance of light emitted from the phosphor, and the luminance is proportional to the amount of emitted electrons.
  • the extraction gate electrode is lower than that of amorphous silicon. Therefore, the voltage can be reduced.
  • the amount of current from the cold electron-emitting device is higher in the oriented plane ⁇ 100 ⁇ than in the case of the oriented plane ⁇ 110 ⁇ columnar polycrystalline film, and the voltage must be reduced. Can be.
  • Embodiment 6 ′ if the crystal plane of the columnar crystal grains is oriented in ⁇ 110 ⁇ or ⁇ 100 ⁇ plane, the amount of emitted electrons is increased, An efficient cold electron emitting element can be formed.
  • the emitter and the method of manufacturing an emitter according to the present invention are characterized in that etching is performed on a columnar polycrystalline film formed by growing columnar crystal grains on a substrate along the same crystal rod, whereby the tip shape is obtained.
  • a well-formed emitter can be formed with good reproducibility. Therefore, even when a large number of emitters are formed on a large-area substrate, uniformity of the emitter shape can be obtained.
  • it is possible to suppress variations in the electron emission characteristics of the cold electron emitter due to variations in the shape of the emitter, such as a flat panel dual image display device, various sensors, a high-frequency oscillator, an ultra-high-speed device, and an electron microscope. It can be used as an electron source for various electron beam utilizing devices such as an electron beam exposure device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Cold Cathode And The Manufacture (AREA)

Abstract

A cold electron emitting device comprising an emitter fabricated by etching a columnar polycrystalline film (2) formed by growing columnar crystal grains (4) along the same crystal axis on a substrate (1). Even if multiple emitters are fabricated in such a cold electron emitting device, the uniformness of the shapes of the emitters is of good reproducibility, and the variation of electron emitting characteristic due to variation of the shapes of emitters is little, thereby fabricating a cold electron emitting device having a uniform emitting characteristic and formed on a large-area substrate.

Description

明細書 ェミッタ、 ェミ ッタ製造方法、 及び冷電子放出素子製造方法 技術分野  TECHNICAL FIELD The present invention relates to an emitter, a method of manufacturing an emitter, and a method of manufacturing a cold electron emitting device.
本発明は、 平面型画像衷示装置や各種センサー、 高周波発振器、 超高 速デバイス、 電子顕微鏡、 電子ビーム露光装置など種々の電子ビーム利 用装置の電子源として用いられる冷電子放出用のェミ ッタ及びその製造 方法に関する。 背景技術  The present invention relates to a cold electron emission emitter used as an electron source for various electron beam utilizing devices such as a flat panel image display device, various sensors, a high frequency oscillator, an ultra-high speed device, an electron microscope, and an electron beam exposure device. And a method of manufacturing the same. Background art
従来の電界放出型ディスブレイ装置などの冷電子用鼋子源には、 高さ 及び底面の直径が 1 / m前後である円錐型の極微小ェミッタをカソ一ド 側に多数形成したものが用いられている。 上記ェミッタは、 その先端部 に電界を集中させることにより放出電流が得られる。 この基本構造は、 C. A. Sp i ntら ( J o u r n a l o f Ap p l i e d P h y s i c s , V o l . 47 , N o . 1 2, p. 5 248 , 1 9 76年) によって提案されている方法が知られている。 その電子放出特性は、 ェ ミ ッタ先端部の形状によって変動するため、 電子放出特性を個々のエミ ッタにおいて等しくするには、 多数形成したェミ ッタの形状、 特に先端 形状が均一に形成されることが望まれる。  Conventional electron sources for cold electrons, such as field emission display devices, use a large number of conical microemitters with a height and a bottom diameter of around 1 / m formed on the cathode side. Have been. The emitter emits an emission current by concentrating an electric field at its tip. This basic structure is known by a method proposed by CA Spint et al. (Journal of Applied Physics, Vol. 47, No. 12, p. 5248, 1976). . Since the electron emission characteristics fluctuate depending on the shape of the emitter tip, in order to make the electron emission characteristics equal in each emitter, the shape of many emitters, especially the tip shape, must be uniform. It is desired to be formed.
また、 このェミッタの最大の問題点として、 電子放出量が時間変動す ることがあり、 これを解決するためのエミッ夕製造 法は、 次の二つの 方法に大別される。  The biggest problem with this emitter is that the amount of electron emission fluctuates over time. The method of manufacturing an emitter to solve this problem is roughly divided into the following two methods.
一つは、 ガラス基板上に金属のエミ ッ夕を形成して、 このェミッタに 大きな電気抵抗を直列に接続し、 放出電流量を安定させるものである。 また、 別の方法として、 半導体によってェミツ夕と トランジスタを形成 し、 このトランジス夕によって能動的に放出電流量を制御しょうとする ものである。 この方法は、 消費電力が小さく動作速度も速いため今後の 発展が期待されている。 One is to form a metal emitter on a glass substrate and connect a large electrical resistance in series with this emitter to stabilize the emission current. Another method is to form a transistor with an emitter using a semiconductor, and to actively control the amount of emission current using this transistor. Things. This method has low power consumption and high operating speed, and is expected to be developed in the future.
上記半導体を用いてエミ ッ夕を形成する場合、 次にあげる三種類のェ ミ ヅタ材料膜が考えられる。 一つは粒界がなく、 あらゆる部分において 結晶方位が一定方向にそろった単結晶膜、 次に結晶方位がパラパラな結 晶粒が集まった多結晶膜、 そして、結晶構造をもたない非晶質膜である。 上記三種類の冷電子放出素子材料の中で、 優れた特性のトランジスタを 形成することを考えるならば、 単結晶膜あるいは多結晶膜を用いる方が よい。  When an emitter is formed using the above semiconductor, the following three types of emitter material films can be considered. One is a single crystal film with no grain boundaries and the crystal orientation is aligned in a fixed direction in every part.Next, a polycrystalline film in which crystal grains with different crystal orientations are gathered, and an amorphous material without a crystal structure Membrane. Among the three types of cold electron emission element materials described above, if a transistor having excellent characteristics is to be formed, it is preferable to use a single crystal film or a polycrystalline film.
単結晶膜を用いた場合、 粒界がなく結晶方位が一定方向となっている ために、 湿式エッチングあるいは反応性イオンエッチングの等方性、 あ るいは異方性エッチング速度が一様であり、 均一性の優れたエミ 'ソタを 製造することができる。 しかし、 単結晶膜は、 製造コス トが高くかつ安 idsなガラス基板などの大面積基板上に作製できないために実用性に乏し いのが現状である。  When a single crystal film is used, since there is no grain boundary and the crystal orientation is in a fixed direction, the isotropic or anisotropic etching rate of wet etching or reactive ion etching is uniform, It is possible to manufacture emisota with excellent uniformity. However, single crystal films are not practical because they cannot be fabricated on large-area substrates such as glass substrates with high manufacturing costs and low ids.
一方、 多結晶膜は単結晶膜を用いる場合に比べて製造コス 卜が安価で あり、 しかも大面積墓板上に低温で製造を行うことができるので、 ディ スプレイ装置等の微小な ¾子源に適している。  On the other hand, a polycrystalline film is less expensive to manufacture than a single crystal film, and can be manufactured on a large-scale tomb plate at a low temperature. Suitable for.
第 1 0図は、 上記従来の多結晶膜基板の断面図を示す図であり、 第 1 1図は、第 1 0図の多結晶膜を用いて製造したェミ ッタの断 ώ図である。 第 1 0図において、 1は、 例えばガラスなどの基板であり、 その上部 に結晶方位、 及び粒 gの異なる微小な結晶粒 1 3からなる多結晶膜 1 4 が形成されている。 該多結晶膜 1 4内は、 上記基板 1上に種々の大きさ と方向性をもった結晶粒 1 3が存在するために、 無数の粒界が存在して いる。  FIG. 10 is a cross-sectional view of the conventional polycrystalline film substrate. FIG. 11 is a cross-sectional view of an emitter manufactured using the polycrystalline film of FIG. is there. In FIG. 10, reference numeral 1 denotes a substrate made of, for example, glass or the like, on which a polycrystalline film 14 composed of fine crystal grains 13 having different crystal orientations and grains g is formed. In the polycrystalline film 14, countless grain boundaries exist because crystal grains 13 having various sizes and directions exist on the substrate 1.
また、第 1 1図に示す多結晶膜 1 4を用いて製造したエミ ッタ 1 5は、 ガラスなどの基板 1上に結晶方位、 及び粒径の異なる微小な結晶粒 1 3 からなる多結晶膜 1 4をエッチング加工することにより形成することが できる。 以上のように、 上記従来技術において、 基板上に多結晶膜 1 4を形成 させてエミ ヅ夕 1 5を製造しているので、 良好な特性のトランジスタと 冷電子放出素子を低いプロセス温度で製造することができ、 大面積の安 価なガラス基板を使用することができる。 その結果、 ェミ ッタ 1 5の製 造コス トを下げることができる。 An emitter 15 manufactured using the polycrystalline film 14 shown in FIG. 11 is made of a polycrystalline structure composed of fine crystal grains 13 having different crystal orientations and grain sizes on a substrate 1 such as glass. The film 14 can be formed by etching. As described above, in the above-described conventional technology, since the polycrystalline film 14 is formed on the substrate to manufacture the semiconductor device 15, the transistor and the cold electron-emitting device having good characteristics are manufactured at a low process temperature. Therefore, a large-area inexpensive glass substrate can be used. As a result, the manufacturing cost of the emitter 15 can be reduced.
しかしながら、 上記多結晶膜 1 4を用いて形成したエミッタ 1 5は、 電子放出特性にバラヅキを生じるという問題がある。 これは、 エツチン グ加工を行う多結晶膜の結晶粒径のパラツキ、 及び各結晶粒の結晶方位 および結晶配向面が大きく異なっているためであり、 エッチングによる エミ ッ夕 1 5形成の際に、 等方性あるいは異方性エッチング速度が、 粒 界を境として結晶粒ごとに異なることが挙げられる。  However, the emitter 15 formed using the polycrystalline film 14 has a problem that the electron emission characteristics vary. This is because the crystal grain size of the polycrystalline film subjected to the etching process varies, and the crystal orientation and the crystal orientation plane of each crystal grain are greatly different. The isotropic or anisotropic etching rate differs from crystal grain to grain boundary.
すなわち、 従来の多結晶膜 1 4では、 等方性、 あるいは異方性エッチ ング速度が結晶粒ごとに異なるため、 第 1 1図に示すように、 ェミ ッタ 1 5表 ώに規則性のない無数の凹凸が形成され、 その結果、 電子放出特 性にバラツキを生じる。 しかも、 エッチングによるエミ ッ夕 1 5の形成 に再現性が得られない。 したがって、 このような不規則性の多結晶膜 1 4では大面積基板に均一なェミ ッタ 1 5を再現性よく、 多数形成するこ とが困難であり、 エミ ッ夕 1 5を用いたデバイスの製造コス トも高くな る。  That is, in the conventional polycrystalline film 14, since the isotropic or anisotropic etching speed differs for each crystal grain, as shown in FIG. Countless irregularities are formed, and as a result, the electron emission characteristics vary. Furthermore, reproducibility cannot be obtained in the formation of the emitter 15 by etching. Therefore, it is difficult to form a large number of uniform emitters 15 with good reproducibility on a large-area substrate with such an irregular polycrystalline film 14. Device manufacturing costs will also increase.
本発明は、 かかる問題点を解決するためになされたものであり、 エミ ッ夕を多数形成した場合でも、 ェミ ッタの形状の均 性を再現性よく得 るとともに、 エミ ッ夕の形状の変動に起因する電子放出特忤のバラツキ を抑えることができるエミッ夕、 及びその製造方法を提供することを目 的とする。 発明の開示  The present invention has been made to solve such a problem. Even when a large number of emitters are formed, the uniformity of the shape of the emitter can be obtained with good reproducibility, and the shape of the emitter can be improved. It is an object of the present invention to provide an emitter capable of suppressing variations in electron emission characteristics caused by fluctuations in electron emission, and a method for manufacturing the same. Disclosure of the invention
本発明請求の範囲第 1項に記載のエミッ夕は、 基板上に柱状の結晶粒 を同じ結晶軸に沿って成長させた柱状多結晶膜に対してエッチングを施 すことにより形成することを特徴とするものである。 これにより、 エミ ッ夕を多数形成した場合でも、 エミ ッ夕の形状の均一性を再現性よく得 るとともに、 エミッ夕の形状の変動に起因する電子放出特性のバラツキ を抑えることができる。 An emitter according to claim 1 of the present invention is characterized in that columnar crystal grains are formed on a substrate by etching a columnar polycrystalline film grown along the same crystal axis. It is assumed that. This allows Emi Even when a large number of emitters are formed, uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the emitter shape can be suppressed.
次に、 本発明請求の範囲第 2項に記載のェミッタは、 基板上に柱状の 結晶粒を同じ結晶軸に沿って成長させた柱状多結晶膜を形成した後に、 上記柱状多結晶膜上に第 1の絶縁膜をパターニングし、 上記パターニン グされた第 1絶縁膜を用いて、 上記柱状多結晶膜にエッチングを施すこ とにより形成することを特徴とするものである。 これにより、 エミ ッ夕 を多数形成した場合でも、 エミ ッ夕の形状の均一性を再現性よく得ると ともに、 ェミッタの形状の変動に起因する電子放出特性のバラツキを抑 えることができる。  Next, the emitter according to claim 2 of the present invention forms a columnar polycrystalline film in which columnar crystal grains are grown along the same crystal axis on a substrate, and then forms the columnar polycrystalline film on the columnar polycrystalline film. The method is characterized in that the first insulating film is patterned, and the columnar polycrystalline film is etched using the patterned first insulating film. As a result, even when a large number of emitters are formed, uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the emitter shape can be suppressed.
次に、 本発明請求の範囲第 3項に記載のェミッタは、 基板上に第 2の 絶縁膜を形成し、 上記第 2の絶縁膜上に柱状の結晶粒を同じ結晶軸に沿 つて成長させた柱状多結晶膜を形成した後に、 上記柱状多結晶膜上に第 1の絶縁膜をパターニングし、 上記パ夕一ニングされた第 1の絶縁膜を 用いて、 上記柱状多結晶膜にエッチングを施すことにより形成すること を特徴とするものである。 これにより、 ェミ ッタを多数形成した場合で も、 ェミッタの形状の均一性を再現性よく得るとともに、 ェミ ッタの形 状の変動に起因する電子放出特性のバラツキを抑えることができる。 次に, 本発明請求の範囲第 4項に記載のェミ ッタは、 請求の範囲第 1 項乃至請求の範囲第 3項の何れかに記載のエミ ッ夕において、 上記柱状 多結晶膜を構成する柱状結晶粒は、 基板面に対してある一定の方向に結 晶方位、 及び結晶面がそろっていることを特徴とするものである。 これ により、 ェミ ッタを多数形成した場合でも、 ェミ ッタの形状の均一性を 再現性よく得るとともに、 ェミ ッタの形状の変動に起因する電子放出特 性のバラツキを抑えることができる。  Next, the emitter according to claim 3 of the present invention forms a second insulating film on the substrate, and grows columnar crystal grains on the second insulating film along the same crystal axis. After forming the columnar polycrystalline film, the first insulating film is patterned on the columnar polycrystalline film, and the columnar polycrystalline film is etched using the patterned first insulating film. It is characterized by forming by applying. As a result, even when a large number of emitters are formed, the uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the shape of the emitter can be suppressed. . Next, the emitter according to claim 4 of the present invention is the emitter according to any one of claims 1 to 3, wherein the columnar polycrystalline film is formed by: The constituent columnar crystal grains are characterized in that the crystal orientation and the crystal plane are aligned in a certain direction with respect to the substrate surface. As a result, even when a large number of emitters are formed, uniformity of the emitter shape can be obtained with good reproducibility, and variation in electron emission characteristics due to variations in the emitter shape can be suppressed. Can be.
次に、 本発明請求の範囲第 5項に記載のエミ ッ夕は、 請求の範囲第 1 項乃至請求の範囲第 4項の何れかに記載のエミッ夕において、 上記柱状 多結晶膜は、 少なく とも珪素を含むことを特徴とするものである。 これ により、 人面積基板上に柱状多結晶を 5 0 0 °C以下の低温プロセスで実 現できる。 したがって、 大面積基板上に柱状多結晶を均一形状にエッチ ングでき、 人面積基板上にエミ ッ夕を多数形成した場合でも、 ェミ ッタ の形状の均一性を再現性よく得るとともに、 エミ ッタの形状の変動に起 因する電子放出特性のバラツキを抑えることができる。 Next, the EMI according to claim 5 of the present invention is the EMI according to any one of claims 1 to 4, wherein the columnar polycrystalline film has at least Both are characterized by containing silicon. this Thus, columnar polycrystals can be realized on a human area substrate by a low-temperature process of 500 ° C. or less. Therefore, columnar polycrystals can be etched in a uniform shape on a large-area substrate, and even when a large number of emitters are formed on a human-area substrate, uniformity of the emitter shape can be obtained with good reproducibility. Variations in the electron emission characteristics caused by variations in the shape of the light source can be suppressed.
次に、 本発明請求の範囲第 6項に記載のエミ ッ夕は、 請求の範囲第 1 項乃至請求の範囲第 5項に何れかに記載のエミ ッ夕において、 上記柱状 多結晶膜の配向面は、 { 1 1 0 } であることを特徴とするものである。 これにより、 結晶方位と結晶面がそろいやすくなるため、 均一形状なェ ツチングを可能とし、 ェミ ツ夕の形状の均一性を再現性よく得るととも に、 エミ ッ夕の形状の変動に起因する電子放出特性のパラツキを抑える ことができる。  Next, the EMI according to claim 6 of the present invention is the EMI according to any one of claims 1 to 5, wherein the orientation of the columnar polycrystalline film is The surface is characterized by being {1 1 0}. As a result, the crystal orientation and the crystal plane can be easily aligned, so that uniform etching can be performed, and the uniformity of the emitter shape can be obtained with good reproducibility. The variation in the electron emission characteristics.
次に、 本発明請求の範囲第 7項に記載のェミ ッタは、 請求の範囲第 1 項乃罕請求の範 W第 5項の何れかに記載のエミ ッタにおいて、 上記柱状 多結晶膜の配向面は、 { 1 0 0 }であることを特徴とするものである。こ れにより、 結晶方位と結晶而がそろいやすくなるため、 均一形状なエツ チングを可能とし、エミ ッ夕の形状の均一性を再現性よく得るとともに、 ェミ ッ夕の形状の変動に起因する電子放出特性のバラツキを抑えること ができる。 また、 さらに、 結晶粒界の障壁を抑制:することができるとと もに、 絶緣膜界面に形成される捕獲準位がより少なくなる。 したがって、 走行電子の移動度が増大し, 効率のよいエミッ夕を実現できる。  Next, the emitter according to claim 7 of the present invention is the emitter according to any one of claims 1 to 5, wherein the columnar polycrystalline The orientation surface of the film is {100}. As a result, the crystal orientation and the crystal orientation can be easily aligned, so that uniform etching can be performed, the uniformity of the emitter shape can be obtained with good reproducibility, and the variation of the emitter shape can be caused. Variation in electron emission characteristics can be suppressed. Further, the barrier at the crystal grain boundaries can be suppressed: and the trap level formed at the interface with the insulating film can be further reduced. Therefore, the mobility of traveling electrons is increased, and efficient emission can be realized.
次に、 本発明請求の範囲第 8項に記載のェミッタは、 請求の範囲第 1 項乃至請求の範囲第 7項の何れかに記載のエミ ッ夕において、 上記柱状 多結晶膜にエッチングを施すことにより形成されたエミッタ先端の曲率 半径が 5 0 n m以下であることを特徴とするものである。 これにより、 ェミッ夕先端の電界集中を増大させ、 低鼋圧で電子を放出させることが できる。  Next, the emitter according to claim 8 of the present invention is characterized in that, in the emitter according to any one of claims 1 to 7, the columnar polycrystalline film is etched. In this case, the radius of curvature of the tip of the formed emitter is 50 nm or less. As a result, the electric field concentration at the tip of the emitter can be increased, and electrons can be emitted at a low pressure.
次に、 本発明請求の範囲第 9項に^載のエミ ッ夕は、 請求の範囲第 1 項乃至請求の範囲第 8項の何れかに記載のェミ ツ夕において、 上記柱状 結晶膜を構成する柱状結晶粒は、 該柱状結晶粒の短い方の粒径が、 少な く とも 1 0 0 n m以上であることを特徴とするものである。これにより、 エミ ッ夕先端部における、 エッチングのばらつきとなる結晶粒界の数を 減らし、 均一形状なエッチングを可能とし、 ェミ ッタの形状の均一性を 再現性よく得るとともに、 ェミ ツ夕の形状の変動に起因する電子放出特 性のバラツキを抑えることができる。 Next, the emitter according to claim 9 of the present invention is the emitter according to any one of claims 1 to 8, The columnar crystal grains constituting the crystal film are characterized in that the shorter grain size of the columnar crystal grains is at least 100 nm or more. As a result, the number of crystal grain boundaries at the tip of the emitter, which may cause variations in etching, is reduced, uniform etching is possible, and uniformity of the emitter shape is obtained with good reproducibility. Variations in electron emission characteristics due to variations in the evening shape can be suppressed.
次に、 本発明請求の範囲第 1 0項に記載のェミ ッタは、 請求の範囲第 9項に記載のエミッ夕において、 上記柱状結晶粒と基板のなす角度は 8 3 ° 以上であることを特徴とするものである。 これにより、 エミ ッ夕先 端部における、 エッチングのばらつきとなる結晶粒界の数を減らし、 さ らに均一形状なエッチングを可能とし、 エミ ッ夕の形状の均一性を再現 性よく得るとともに、 エミ ッタの形状の変動に起因する電子放出特性の バラツキを抑えることができる。  Next, the emitter according to claim 10 of the present invention is the emitter according to claim 9, wherein the angle formed by the columnar crystal grains and the substrate is 83 ° or more. It is characterized by the following. As a result, the number of crystal grain boundaries at the leading edge of the emitter, which may cause unevenness in etching, is reduced, etching with a more uniform shape is enabled, and uniformity of the emitter shape is obtained with good reproducibility. Variations in electron emission characteristics due to variations in the shape of the emitter can be suppressed.
次に、 本発明請求の範囲第 1 1項に記載のェミ ッタは、 請求の範囲第 3項に記載のェミッタにおいて、 上記第 2の絶縁膜は、 少なく とも、 酸 素かあるいは窒素を含むことを特徴とするものである。 これにより、 ガ ラスから柱状多結晶への不純物拡散を抑制し結晶性の優れた柱状多結晶 を提供し、 ェミ ツ夕の形状の均一性を再現性よく得るとともに、 ェミ ツ 夕の形状の変動に起因する電子放出特性のバラヅキを抑えることができ る。  Next, the emitter according to claim 11 of the present invention is the emitter according to claim 3, wherein the second insulating film is formed of at least oxygen or nitrogen. It is characterized by including. This suppresses the diffusion of impurities from the glass into the columnar polycrystal, provides a columnar polycrystal with excellent crystallinity, and achieves uniformity of the emitter shape with good reproducibility, as well as the emitter shape. Variations in electron emission characteristics due to fluctuations in electron emission characteristics can be suppressed.
次に, 本発明請求の範囲第 1 2項に記載のエミ ッ夕は、 請求の範囲第 2項、 または請求の範囲第 3項に記載のェミッタにおいて、 上記パター ニングされた第 1の絶縁膜は、 円形状であることを特徴とするものであ る。 これにより、 柱状多結晶膜をエッチングすることにより、 容易に先 端が先鋭なェミ ツ夕を実現できる。  Next, the emitter according to claim 12 of the present invention is the emitter according to claim 2 or claim 3, wherein the patterned first insulating film is used. Is characterized by having a circular shape. Thus, by etching the columnar polycrystalline film, a sharp-edged emitter can be easily realized.
次に, 本発明請求の範囲第 1 3項に記載のェミ ッタは、 請求の範囲第 2項または請求の範囲第 3項に記載のエミッ夕において、 上記パ夕一二 ングされた第 1の絶縁膜は、 多角形状であることを特徴とするものであ る。 これにより、 本発明請求の範囲第 1 2項の効果に加え、 さらにフォ ト リソグラフィの露光精度が上がり、 かつ、 露光マスクのコス トを下げ ることができる。 Next, the emitter described in claim 13 of the present invention is the emitter described in claim 2 or claim 3, wherein The first insulating film has a polygonal shape. As a result, in addition to the effects of Claims 12 of the present invention, furthermore, The exposure accuracy of the lithography can be improved, and the cost of the exposure mask can be reduced.
次に, 本発明請求の範囲第 1 4項に記載のェミ ッタ製造方法は、 基板 上に柱状の結晶粒を同じ結晶軸に沿って成長させた柱状多結晶膜を形成 する工程と、 上記柱状多結晶膜に対してエッチングを施すェ稈とを有す ることを特徴とするものである。 これにより、 ェミッタを多数形成した 場合でも、 ェミ ツ夕の形状の均一性を再現性よく得るとともに、 ェミ ツ タの形状の変動に起因する電子放出特性のバラツキを抑えることができ る。  Next, the method for manufacturing an emitter according to claim 14 of the present invention includes a step of forming a columnar polycrystalline film in which columnar crystal grains are grown along the same crystal axis on a substrate; And a column for etching the columnar polycrystalline film. As a result, even when a large number of emitters are formed, uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the emitter shape can be suppressed.
次に, 本発明請求の範囲第 1 5項に記載のェミ ッタ製造方法は、 基板 上に柱状の結晶粒を同じ結晶軸に沿って成長させた柱状多結晶膜を形成 する工程と、 上記柱状多結晶膜上に第 1の絶縁膜をパターニングするェ 程と、 上記パターニングされた第 1絶緣膜を用いて、 上記柱状多結晶膜 をエッチングする工程とを有することを特徴とするものである。 これに より、 ェミッタを多数形成した場合でも、 ェミッタの形状の均一性を再 現性よく得るとともに、 エミッタの形状の変動に起因する電子放出特性 のバラヅキを抑えることができる。  Next, the method for manufacturing an emitter according to claim 15 of the present invention includes a step of forming a columnar polycrystalline film in which columnar crystal grains are grown along the same crystal axis on a substrate; Patterning a first insulating film on the columnar polycrystalline film; and etching the columnar polycrystalline film using the patterned first insulating film. is there. As a result, even when a large number of emitters are formed, uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the emitter shape can be suppressed.
次に、 本発明請求の範囲第 1 6項に記載のエミッ夕製造方法は、 基板 上に第 2の絶縁膜を形成する工程と、 上記第 2の絶縁膜上に柱状の結晶 粒を同じ結晶軸に沿って成長させた柱状多結晶膜を形成する工程と、 上 記柱状多結晶膜上に第 1の絶縁膜をパターニングする工程と、 上記バタ 一二ングされた第 1の絶縁膜を用いて、 上記柱状多結晶膜をエッチング する工程とを有することを特徴とするものである。 これにより、 ェミ ツ 夕を多数形成した場合でも、 エミ ッタの形状の均一性を再現性よく得る とともに、 ェミツ夕の形状の変動に起因する電子放出特性のパラツキを 抑えることができる。  Next, in the method for producing an emitter according to claim 16 of the present invention, the step of forming a second insulating film on the substrate and the step of forming columnar crystal grains on the second insulating film in the same crystal Forming a columnar polycrystalline film grown along the axis, patterning a first insulating film on the columnar polycrystalline film, using the first insulating film that has been buttered. And etching the columnar polycrystalline film. As a result, even when a large number of emitters are formed, uniformity of the emitter shape can be obtained with good reproducibility, and variations in the electron emission characteristics due to variations in the emitter shape can be suppressed.
次に, 本允明請求の範囲笫 1 7項に記載のエミ ッ夕製造方法は、 請氺 の範囲第 1 4項乃至請求の範囲第 1 6項の何れかに記載のエミ ッ夕製造 方法において、 上記柱状多結晶膜を構成する柱状結晶粒は、 基板面に対 してある一定の方向に結晶方位、 及び結晶面がそろっていることを特徴 とするものである。 これにより、 ェミッタを多数形成した場合でも、 ェ ミッ夕の形状の均一性を再現性よく得るとともに、 エミ ッタの形状の変 動に起因する電孑放出特性のバラツキを抑えることができる。 Next, the method for producing an emitter according to claim 17 of the present invention is a method for producing an emitter according to any one of claims 14 to 16 of the present invention. Wherein the columnar crystal grains constituting the columnar polycrystalline film correspond to the substrate surface. In addition, the crystal orientation and the crystal plane are aligned in a certain direction. As a result, even when a large number of emitters are formed, the uniformity of the emitter shape can be obtained with good reproducibility, and the variation in the mosquito discharge characteristics due to the variation in the emitter shape can be suppressed.
次に、 本発明請求の範囲第 1 8項に記載のェミツ夕の製造方法は、 請 求の範囲第 1 4項及至請求の範囲第 1 7項の何れかに記載のェミ ツ夕製 造方法において、 上記柱状多結晶膜は、 少なく とも珪素を含むことを特 徴とするものである。これにより、大面積基板上に柱状多結晶を 5 0 0。C 以下の低温プロセスで実現できる。 したがって、 大面積基板上に柱状多 結晶を均一形状にエッチングでき、 大面積基板上にェミ ッタを多数形成 した場合でも、 ェミ ッタの形状の均一性を再現性よく得るとともに、 ェ ミ ッタの形状の変動に起因する電子放出特性のパラツキを抑えることが できる。  Next, the method for producing an emitter according to claim 18 of the present invention includes the method for producing an emitter according to any one of claims 14 to 17 and claim 17. In the method, the columnar polycrystalline film contains at least silicon. Thereby, columnar polycrystals are formed on a large area substrate at 500. It can be realized by a low temperature process of C or lower. Therefore, columnar polycrystals can be etched on a large-area substrate in a uniform shape, and even when many emitters are formed on a large-area substrate, uniformity of the emitter shape can be obtained with good reproducibility. Variations in the electron emission characteristics due to variations in the shape of the emitter can be suppressed.
次に、 本発明請求の範囲第 1 9項に記載のエミッ夕製造方法は、 請求 の範囲第 1 4項乃至請求の範囲第 1 8項の何れかに記載のェミッ夕製造 方法において、 上 id柱状多結晶膜の配向面は、 { 1 1 0 } であることを 特徴とするものである。 これにより、 結晶方位と結晶面がそろいやすく なるため、 均一形状なエッチングを可能とし、 ェミツ夕の形状の均一性 を再現性よく得るとともに、 エミ ッ夕の形状の変動に起因する電子放出 特性のバラツキを抑えることができる。  Next, the method for producing an emitter according to claim 19 of the present invention is the method for producing an emitter according to any one of claims 14 to 18, The orientation plane of the columnar polycrystalline film is {110}. As a result, the crystal orientation and the crystal plane are easily aligned, so that uniform etching can be performed, the uniformity of the emitter shape can be obtained with good reproducibility, and the electron emission characteristics due to the fluctuation of the emitter shape can be improved. Variation can be suppressed.
次に、 本発明の請求の範囲第 2 0項に記載のェミッタ製造方法は、 請 求の範囲第 1 4項乃至請求の範囲第 1 8項の何れかに記載のエミ ッ夕製 造方法において、 上記柱状多結晶膜の配向面は、 { 1 0 0 } であること を特徴とするものである。 これにより、 結晶方位と結晶面がそろいやす くなるため、 均一形状なエッチングを可能とし、 ェミ ッタの形状の均一 性を再現性よく得るとともに、 エミ ッタの形状の変動に起因する電子放 出特性のバラツキを抑えることができる。 また、 さらに、 結晶粒界の障 壁を抑制することができるとともに、 絶縁膜界面に形成される捕獲準位 がより少なくなる。 したがって、 走行電子の移動度が増大し, 効率のよ いエミ ッ夕を製造することができる。 Next, the method for manufacturing an emitter according to claim 20 of the present invention is the method for manufacturing an emitter according to any one of claims 14 to 18. The orientation plane of the columnar polycrystalline film is {100}. As a result, the crystal orientation and the crystal plane are easily aligned, so that uniform etching can be performed, the uniformity of the emitter shape can be obtained with good reproducibility, and the electron emission caused by the fluctuation of the emitter shape can be achieved. Variations in emission characteristics can be suppressed. In addition, obstacles at crystal grain boundaries can be suppressed, and trap levels formed at the interface of the insulating film can be reduced. Therefore, the mobility of the traveling electrons increases and the efficiency increases. It is possible to manufacture new emitters.
次に、 本発明請求の範囲第 2 1項に記載のエミ ッ夕製造方法は、 請求 の範囲第 1 4項乃至請求の範囲第 2 0項の何れかに記載のエミ ツ夕製造 方法において、 エミ 'ソ夕先端の曲率半径が 5 0 n m以下となるように、 上記柱状多結晶膜にエッチングを施すことを特徴とするものである。 こ れにより、 エミ ッ夕先端の鼋界集中を増大させ、 低電圧で電子を放出さ せることができる。  Next, the method for producing an emitter according to claim 21 of the present invention includes the method for producing an emitter according to any one of claims 14 to 20. The method is characterized in that the columnar polycrystalline film is etched so that the radius of curvature at the tip of the emitter is 50 nm or less. As a result, the field concentration at the tip of the emitter can be increased, and electrons can be emitted at a low voltage.
次に、 本発明請求の範囲第 2 2項に記載のエミ ッ夕製造方法は、 請求 の範囲第 1 4項乃至請求の範囲第 2 1項の何れかに記載のェミ ッタ製造 方法において、 上記柱状結晶膜中の柱状結晶粒は、 該柱状結晶粒の短い 方の粒径が、 少なく とも 1 0 0 n m以上であることを特徴とするもので ある。 これにより、 ェミ ッタ先端部における、 エッチングのばらつきと なる結晶粒界の数を減らし、 均一形状なエッチングを可能とし、 ェミ ツ 夕の形状の均一性を再現性よく得るとともに、 エミッタの形状の変動に 起因する電子放出特性のバラツキを抑えることができる。  Next, the method for producing an emitter according to claim 22 of the present invention is the method for producing an emitter according to any one of claims 14 to 21. The columnar crystal grains in the columnar crystal film are characterized in that the shorter one of the columnar crystal grains has a particle size of at least 100 nm or more. As a result, the number of crystal grain boundaries at the tip of the emitter, which causes variations in etching, is reduced, uniform etching is possible, and uniformity of the emitter shape is obtained with good reproducibility. Variations in electron emission characteristics due to variations in shape can be suppressed.
次に、 本発明請求の範囲第 2 3項に記載のエミ ッ夕製造方法は、 請求 の範 ffl第 2 2項に記載のェミ ッ夕製造方法において、 上記柱状結晶粒と 基板のなす角度は、 8 3 ° 以上であることを特徴とするものである。 こ れにより、 エミ ッ夕先端部における、 エッチングのばらつきとなる結 ϋ 粒界の数を減らし、 さらに均一形状なエッチングを可能とし、 エミ ッ夕 の形状の均一性を再現性よく得るとともに、 エミ ッ夕の形状の変動に起 因する電子放出特性のバラツキを抑えることができる。  Next, the method for producing an emitter according to claim 23 of the present invention is the method for producing an emitter according to claim ffl, wherein the angle between the columnar crystal grains and the substrate is Is characterized by being at least 83 °. As a result, the number of grain boundaries at the tip of the emitter, which may cause unevenness in etching, is reduced, the etching is made more uniform, and the uniformity of the emitter is obtained with good reproducibility. Variations in electron emission characteristics due to variations in the shape of the light can be suppressed.
次に、 本発明請求の範囲第 2 4項に記載のェミ ッタ製造方法は、 請求 の範囲第 1 6項に記載のエミ ッタ製造方法において、 上記第 2の絶縁膜 は、 少なく とも、 酸素かあるいは窒素を含むことを特徴とするものであ る。 これにより、 ガラスから柱状多結晶への不純物拡散を抑制し結晶性 の優れた柱状多結晶を提供し、 エミ ッ夕の形状の均一性を再現性よく得 るとともに、 エミ ッタの形状の変動に起因する電子放出特性のバラツキ を抑えることができる。 次に、 本発明請求の範囲第 2 5項に記載のエミ ッ夕製造方法は、 請求 の範囲第 1 5項または請求の範囲第 1 6項に記載のェミッタ製造方法に おいて、 上記パ夕一ニングされた第 1の絶縁膜は、 円形状であることを 特徴とするものである。 これにより、 柱状多結晶膜をエッチングするこ とにより、 容易に先端が先鋭なェミ ッタを実現できる。 Next, an emitter manufacturing method according to claim 24 of the present invention is the emitter manufacturing method according to claim 16, wherein the second insulating film is at least , Characterized by containing oxygen or nitrogen. This suppresses the diffusion of impurities from the glass into the columnar polycrystals, provides columnar polycrystals with excellent crystallinity, and achieves uniform emitter shape with good reproducibility and changes in emitter shape. It is possible to suppress the variation in the electron emission characteristics caused by this. Next, in the method for producing an emitter according to claim 25 of the present invention, the method for producing an emitter according to claim 15 or claim 16 is provided. The thinned first insulating film has a circular shape. Thus, by etching the columnar polycrystalline film, an emitter having a sharp tip can be easily realized.
次に、 本発明請求の範两第 2 6項に記載のェミ ッタ製造方法は、 請求 の範囲笫 1 5項または請求の範囲第 1 6項に記載のエミ ッ夕製造方法に おいて、 上記パターニングされた第 1の絶縁膜は、 多角形状であること を特徴とするものである。 これにより、 本発明請求の範囲第 2 5項の効 果に加え、 さらにフォ ト リソグラフィの露光精度が上がり、 かつ、 露光 マスクのコス トを下げることができる。  Next, the method for manufacturing an emitter according to claim 26 of the present invention is the same as the method for manufacturing an emitter according to claim 15 or claim 16. The patterned first insulating film has a polygonal shape. Thereby, in addition to the effect of the present invention, the exposure accuracy of photolithography can be further increased, and the cost of the exposure mask can be reduced.
次に、本発明請求の範囲第 2 7項に記載の冷電子放出素子製造方法は、 請求の範囲第 1 5項または請求の範囲第 1 6項に記載のエミ ッタ製造方 法によりェミ ッタを製造する工程と、 上記柱状多結晶膜上にパターニン グされた第 1の絶緣膜を残したまま、 第 3の絶縁層と引出しゲート電極 を形成する工程と、 上記柱状多結晶膜上にパターニングされた第 1の絶 緣膜の上部のみを除去して開口部を形成する工程とを有するものである。 これにより、 フォ ト リソ工程を用いることなく、 容易に引出ゲート電極 を形成でき、 冷電子放出素子の製造コストを下げることができる。 図面の簡 な説明  Next, a method for manufacturing a cold electron emitting device according to claim 27 of the present invention is provided by the method for manufacturing an emitter according to claim 15 or claim 16. Manufacturing a third insulating layer and an extraction gate electrode while leaving the first insulating film patterned on the columnar polycrystalline film; and Forming an opening by removing only the upper part of the first insulating film patterned in this manner. Thus, the extraction gate electrode can be easily formed without using a photolithography process, and the manufacturing cost of the cold electron emission device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
第 1図は、 本発明の実施の形態 1による柱状多結晶基板の断面図であ る。  FIG. 1 is a sectional view of a columnar polycrystalline substrate according to Embodiment 1 of the present invention.
第 2図は、 第 1図に示した柱状多結晶基板を用いた冷電子放出索子の 製造方法の工程断面図である。  FIG. 2 is a process cross-sectional view of a method for manufacturing a cold electron emission wire using the columnar polycrystalline substrate shown in FIG.
第 3図は、 本発明の実施の形態 1による柱状多結晶基板のラマンスぺ ク トルである。  FIG. 3 is a Raman spectrum of the columnar polycrystalline substrate according to the first embodiment of the present invention.
第 4図は、 本発明の実施の形態 2による下地層を設けた柱状多結晶基 板の断面図である。 第 5図は、 本発明の実施の形態 3および 5によるある一定方向に結晶 方位および結晶面がそろつた柱状多結晶基板の断面図である。 FIG. 4 is a cross-sectional view of a columnar polycrystalline substrate provided with an underlayer according to Embodiment 2 of the present invention. FIG. 5 is a cross-sectional view of a columnar polycrystalline substrate according to Embodiments 3 and 5 of the present invention, in which crystal orientations and crystal planes are aligned in a certain direction.
第 6図は、 本発明の実施の形態 4による冷電子放出素子の断面図であ る。  FIG. 6 is a cross-sectional view of a cold electron emission device according to Embodiment 4 of the present invention.
第 7図は、 本発明の実施の形態 6による膜構造の違いによる冷電子放 出素子からの放出電子量を示す図である。  FIG. 7 is a diagram showing an amount of electrons emitted from a cold electron emission element due to a difference in film structure according to a sixth embodiment of the present invention.
第 8図は、 { 1 1 0} 配向した柱状多結晶シリコン膜の XRDスぺク トルである。  FIG. 8 is an XRD spectrum of a {110} -oriented columnar polycrystalline silicon film.
第 9図は、 ェミ ッ夕先端にかかる電界強度とエミ ッ夕先端曲率半 Sと の関係を示す図である。  FIG. 9 is a diagram illustrating the relationship between the electric field intensity applied to the emitter tip and the curvature half S of the emitter tip.
第 1 0図は、 従来技術における多結晶膜の断面図である。  FIG. 10 is a sectional view of a polycrystalline film according to the prior art.
第 1 は、 従来技術における多結晶膜を用いたエミ タの断面図で ある。 発明を実施するための最良の形態  The first is a cross-sectional view of an emitter using a polycrystalline film according to the prior art. BEST MODE FOR CARRYING OUT THE INVENTION
(実施の形態 1 )  (Embodiment 1)
以下に、 発明の実施の形態 1について、 第 1図、 第 2図を用いて説明 する。  Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2.
第 1図は、 本発明の実施の形態 1による柱状多結晶基板の断面図であ り、 第 2図は、 本発明の実施の形態 1によるェミッタ、 及び冷電子放出 素子の製造方法の工程断面図である。  FIG. 1 is a cross-sectional view of a columnar polycrystalline substrate according to Embodiment 1 of the present invention, and FIG. 2 is a process cross-section of a method of manufacturing an emitter and a cold electron emitting device according to Embodiment 1 of the present invention. FIG.
第 1図において、 1は、 例えばガラスなどの基板である。 2は、 柱状 多結晶膜である。 3は、 結晶粒子間の境を示す結晶粒界である。 4は、 柱状結晶粒である。  In FIG. 1, reference numeral 1 denotes a substrate such as glass. 2 is a columnar polycrystalline film. 3 is a crystal grain boundary indicating a boundary between crystal grains. 4 is columnar crystal grains.
以下に、 柱状多結晶膜 2の形成について説明する。 第 1図に示すガラ スなどの基板 1上に、 例えば材料ガスとして水素ガスにより希釈された 0. 1 %から 3 %のシランガスを用いたプラズマ化学気相成長法 (P C VD法) により、 基板温度 2 0 0"Cから 3 5 0 °C、 成膜圧力 0. 1 P a から 5 P a、 R F p owc r 3 0 0W から 1 kWの条件において結晶 方位および結晶面がそろっている粒径約 1 0◦ nmから 14 0 nmの柱 状の多結晶シリコン膜である柱状多結晶膜 2を形成する。 この条件で成 長した膜は、 主として { 1 1 0 } 面配向を有する柱状多結晶膜 2となる。 また、 第 1図に示すガラスなどの基板 1上に、 例えば、 同じく P CV D法で材料ガスにシランガスと四フッ化珪素ガスの混合ガスを用いて、 基板温度 2 5 0 °Cから 4 5 0 °C、 成膜圧力 l O O P aから 1 70 P a、 R F p owe r 50Wから 5 00 Wの条件において作製すると、 主と して { 1 00} 面配向を有する粒径約 2 5 0 nmの柱状多結晶膜 2が得 られる。 Hereinafter, formation of the columnar polycrystalline film 2 will be described. For example, a plasma chemical vapor deposition (PCVD) method using a 0.1% to 3% silane gas diluted with hydrogen gas as a material gas is formed on a substrate 1 such as a glass shown in FIG. Crystals at temperatures from 200 "C to 350 ° C, deposition pressures from 0.1 Pa to 5 Pa, and RF power from 300 W to 1 kW A columnar polycrystalline film 2 is formed, which is a columnar polycrystalline silicon film having a grain size of about 10 ° nm to about 140 nm having the same orientation and crystal plane. The film grown under these conditions is mainly a columnar polycrystalline film 2 having a {110} plane orientation. On a substrate 1 made of glass or the like shown in FIG. When manufactured under the conditions of 0 ° C, film formation pressure l OOP a to 170 Pa, and RF power 50 W to 500 W, a particle size having a {100} plane orientation is mainly about 250 nm. Thus, the columnar polycrystalline film 2 is obtained.
このように作製された { 1 1 0} 面配向、 或は { 1 00} 面配向した 柱状多結晶膜 2は、 ともに本発明の作用である均一形状のエミ ッ夕を有 する冷電子放出素子を実現できる。  The columnar polycrystalline film 2 having the {110} plane orientation or the {100} plane orientation thus produced is a cold electron emitting element having a uniform-shaped emitter, which is an effect of the present invention. Can be realized.
なお、 柱状多結晶膜 2には非晶質層が含まれるが、 均一形状のェミ ツ 夕を形成するには、 多結晶と非晶質の単位面積に含まれる比率である結 晶化率が 80 %以上であることが望ましい。  Although the columnar polycrystalline film 2 includes an amorphous layer, a crystallization ratio which is a ratio included in a unit area of the polycrystal and the amorphous is required to form a uniform emitter. Is preferably 80% or more.
この結晶化率は、 例えばラマン分光により測定でき、 ラマン分光法に よる結晶相のラマンシフ 卜量約 5 2 0 cm— 1の強度 I ( 52 0 ) と非晶 質相のラマンシフ ト量 4 8 0 cm— ]の強度 I ( 48 0 ) との関係で示さ れる結晶化率 I ( 5 2 0 ) /{ 1 (5 20 )+1(48 0)}で表わされる (第 3図参照)。 This crystallization ratio can be measured by, for example, Raman spectroscopy. The intensity I (520) of the Raman shift amount of the crystalline phase of about 520 cm- 1 by Raman spectroscopy and the Raman shift amount of the amorphous phase of 480 The crystallization ratio I (520) / {1 (520) +1 (480)} is shown in relation to the intensity I (480 ) of cm— ] (see FIG. 3).
なお、 本実施の形態では代表的な成長条件を特定したものであり、 珪 素を含む混合ガスを用いてガス流量、 ガス混合比、 基板温度、 成膜圧力、 R F p o we rなどのある特定の範囲を持った成長条件において柱状 多結晶膜 2を得ることができ、 その粒径やサイズは上記成長条件によつ て変化させることができる。  Note that, in this embodiment, typical growth conditions are specified, and a specific flow rate, a gas mixture ratio, a substrate temperature, a film forming pressure, an RF power, and the like are specified using a mixed gas containing silicon. The columnar polycrystalline film 2 can be obtained under the growth conditions having the range described above, and the grain size and size can be changed according to the growth conditions.
例えば、 第 8図に、 シランと水素の混合ガスを用いたプラズマ化学気 相成長法 (P C VD法) により、 基板温度 300°C、 成膜圧力 2 P a、 R F P owe r 300 Wの条件で成膜した代表的な柱状多結晶シリコ ン膜の X線回折 (XRD) スペク トルを示す。 上記条件により成膜した 膜は、 2 6が約 4 7 . 4 ° に強いビークが得られており、 ( 2 2 0 ) 面に 配向しているのがわかる。 For example, Fig. 8 shows a plasma chemical vapor deposition (PCVD) method using a mixed gas of silane and hydrogen under the conditions of a substrate temperature of 300 ° C, a deposition pressure of 2 Pa, and an RF power of 300 W. The X-ray diffraction (XRD) spectrum of a representative columnar polycrystalline silicon film is shown. Deposited under the above conditions In the film, a strong beak of 26 was obtained at about 47.4 °, and it was found that the film was oriented in the (2 0 0) plane.
また、 { 1 0 0 } 面に配向している柱状多結晶膜 2は、 シランガスと 四フッ化珪素ガスの混合ガスを用いた P C V D法により、 基板温度 3 0 0 nC、 成膜圧力 1 0 0 P a、 ; F P o w e r 3 0 0 Wの条件で成膜し たときに得られ、 XRDスぺク トルの 2 βが約 6 3 . 2 ° に ( 4 0 0 ) の ビーク (図示せず) が現れる。 The columnar polycrystalline film 2 oriented on the {100} plane was formed by a PCVD method using a mixed gas of silane gas and silicon tetrafluoride gas at a substrate temperature of 300 nC and a film forming pressure of 100 nm. FPower: obtained when the film is formed under the condition of FP power 300 W, and a beak of (400) is obtained when the 2β of the XRD spectrum is about 63.2 ° (not shown). ) Appears.
次に、 前述した柱状多結晶膜 2を用いて製造するェミ ツ夕、 及び冷鼋 子放出素子の製造方法について第 2図を用いて説明する。  Next, an emitter manufactured using the above-described columnar polycrystalline film 2 and a method for manufacturing a cold electron emitting device will be described with reference to FIG.
前述したように柱状多結晶膜 2を基板 1 卜.に形成 (第 2 ( a ) 図) し た後、 第 2 ( b ) 図に示すように、 P C V D法やスパッ夕法、 蒸着法等 により S i 0 2などの第 1 の絶縁膜 5を、 柱状多結晶膜上に、 各ドッ ト が円形状または多角形状となるようにパ夕一ニングする。 このパター二 ングは、 例えば、 絶縁膜を 2 0 0 n m程度堆積し、 フォ トリソ工程によ り、 該絶縁膜を直径 1 Ai m程度の円形状あるいは多角形状のドッ トパ夕 ーンに加工する。 After the columnar polycrystalline film 2 is formed on the substrate 1 as described above (FIG. 2 (a)), as shown in FIG. 2 (b), a PCVD method, a sputtering method, an evaporation method, or the like is used. a first insulating film 5, such as S i 0 2, on the columnar polycrystalline film, each dot is Pas evening-learning so that the circular or polygonal shape. In this patterning, for example, an insulating film is deposited to a thickness of about 200 nm, and the insulating film is processed into a circular or polygonal dot pattern having a diameter of about 1 Aim by a photolithography process. .
円形状あるいは多角形状の第 1の絶縁膜 5を形成後、 第 2 ( c ) 図に 示すように、 反応性イオンエッチング (RIE) を施すことにより、 柱状 多結晶膜 2を加工し、 エミ ッ夕 6を得る。 エッチングガスとしては、 例 えば S F sガスなどのハロゲンガスが用いられる。 After forming the first insulating film 5 having a circular or polygonal shape, the columnar polycrystalline film 2 is processed by reactive ion etching (RIE) as shown in FIG. Evening get 6. As an etching gas, a halogen gas, such as SF s gas is used if e example.
梡いて、 第 2 ( d ) 図に示すように、 蒸着法などにより S i 0 2など のゲ一ト絶縁層 7と N bなどの引出しゲ一卜電極 8を形成する。 ゲ一卜 絶縁層 7の膜厚を制御することにより、 エミ ッ夕 6先端部と引出しゲー ト電極 8の間の距離を容易に変化させ、 エミッ夕 6先端部に効率よく電 界を集中させることができ、 電子放出効率の良好な冷電子放出素子が得 られる。 And have梡, as shown in 2 (d) Fig., To form a drawer gate one Bok electrode 8 such as S i 0 gate one gate insulating layer 7, such as 2 and N b by vapor deposition or the like. By controlling the thickness of the gate insulating layer 7, the distance between the tip of the emitter 6 and the extraction gate electrode 8 is easily changed, and the electric field is efficiently concentrated on the tip of the emitter 6. As a result, a cold electron-emitting device having good electron emission efficiency can be obtained.
最後に、 第 2 ( e ) 図に示すように、 リフ トオフ法により上記円形状 あるいは多角形状ドッ トパターンに加工された第 1の絶縁膜 5部分から 上部を除去し、 開口部を形成する。 なお、 本実施形態 1では、 リ フ トォ フ法によりゲ一卜絶縁層 7と引出し電極 8を除去し開 U部を形成してい るが、 エッチバック法により形成することも可能である。 Finally, as shown in FIG. 2 (e), an upper portion is removed from the first insulating film 5 processed into the above-mentioned circular or polygonal dot pattern by a lift-off method, and an opening is formed. In the first embodiment, the default Although the gate insulating layer 7 and the extraction electrode 8 are removed to form the open U portion by the フ method, it can also be formed by the etch back method.
以上のように、 本実施の形態 1によれば、 柱状多結晶膜 2を用いて、 エッチングを施すことによりェミ ツ夕 6を製造したので、 各柱状結晶粒 4内の結晶方位、 結晶面が同じであるため、 結晶粒界 3上を除くすべて の部分において、 湿式や反応性イオンエッチングを施した際の等方性あ るいは異方性エッチング速度を等しくすることができる。 従って、 エミ ッタ 6を再現性よく製造することができ、 広範囲に多数形成したエミ ッ 夕 6において、 形状の均一性を得ることが可能となる。  As described above, according to the first embodiment, since the emitter 6 is manufactured by performing etching using the columnar polycrystalline film 2, the crystal orientation and the crystal plane in each columnar crystal grain 4 are formed. Is the same, the isotropic or anisotropic etching rate when wet or reactive ion etching is performed can be made equal in all parts except on the crystal grain boundary 3. Therefore, the emitter 6 can be manufactured with high reproducibility, and uniformity of the shape can be obtained in the emitter 6 formed in a large number over a wide range.
また、 柱状多結晶膜 2は少なく とも珪素 (シリコン) を含むものであ り、 具体的には、 多結晶珪素膜や多結晶珪素ゲルマニウムであり、 これ ら珪素を含む材料を用いることにより、 大面積基板上に柱状多結晶膜を 5 0 0 °C以下の低温プロセスで形成することが可能となる。したがって、 大面積基板上に柱状多結晶を均一形状にエツチングでき、 大面積基板上 にエミッ夕を多数形成した場合でも、 ェミ ッタの形状の均一性を再現性 よく得るとともに、 エミ ッ夕の形状の変動に起因する電子放出特性のパ ラツキを抑えることができる。  Further, the columnar polycrystalline film 2 contains at least silicon (silicon), specifically, a polycrystalline silicon film or polycrystalline silicon germanium. A columnar polycrystalline film can be formed on an area substrate by a low-temperature process of 500 ° C. or less. Therefore, columnar polycrystals can be etched in a uniform shape on a large-area substrate, and even when a large number of emitters are formed on a large-area substrate, the uniformity of the emitter shape can be obtained with good reproducibility, and Variations in the electron emission characteristics due to variations in the shape of the electron beam can be suppressed.
(実施の形態 2 )  (Embodiment 2)
以下に、 本発明の実施の形態 2について、 第 4図を用いて説明する。 第 4図は、 本発明の実施の形態 2による柱状多結晶基板の断面図であ る。 なお、 本実施の形態 2による冷電了放出素子は、 基板上に絶縁膜を 成膜した後に、 柱状の結晶粒を同じ結晶軸に沿って成長させた柱状多結 晶膜 2を形成し、 エミ ッ夕、 及び冷電了放出素子を製造する点において のみ、 基板を絶縁膜で被膜しないで上記柱状多結晶膜 2を形成する上記 実施の形態 1による冷電子放出素子と異なる。 そのため、 上述の実施の 形態 1 と同じ構成要素については同一の符号を付し説明を省略する。 第 4図において、 ガラス基板 1上に、 第 2の絶縁膜 9を成膜する。 こ のガラス基板 1上に、 第 2の絶縁膜 9を成膜する処理は、 例えば、 材料 ガスとしてシランガスと N 2 0ガス、 あるいは TEOS と酸素の混合ガス を用いて、 P CVD法により、 基板温度 200 °Cから 300て、 成膜圧 力 0. l P aから 1 0 P a、 RF p owe r 300Wから 5 0 0 Wの 条件で、 約 3 00 nmから 1 0 0 0 nmの二酸化珪素膜 S i 02を成膜 する n なお、 第 2の絶縁膜 9形成以降のプロセスは、 上述の実施の形態 1と同様なので省略する。 Hereinafter, Embodiment 2 of the present invention will be described with reference to FIG. FIG. 4 is a sectional view of a columnar polycrystalline substrate according to Embodiment 2 of the present invention. In addition, the cold-emitting device according to the second embodiment forms a columnar polycrystalline film 2 in which columnar crystal grains are grown along the same crystal axis after forming an insulating film on a substrate. It differs from the cold electron-emitting device according to the first embodiment in which the columnar polycrystalline film 2 is formed without coating the substrate with an insulating film only in the production of the emitter and the cold electron-emitting device. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. In FIG. 4, a second insulating film 9 is formed on a glass substrate 1. The process of forming the second insulating film 9 on the glass substrate 1 is performed, for example, by using silane gas and N 20 gas as a material gas, or a mixed gas of TEOS and oxygen. The substrate temperature was from 200 ° C to 300, the deposition pressure was 0.1 Pa to 10 Pa, and the RF power was 300 W to 500 W by PCVD method. n still deposited 1 0 0 0 nm of the silicon dioxide film S i 0 2 from nm, the process of the second insulating film 9 formed later is the same as the above-described first embodiment will be omitted.
このように、 基板 1上に第 2の絶縁膜 9を成膜することにより、 基板 1に含まれる不純物、 例えば硼素 (ポロン) やナト リウムなどの拡散を 抑制でき、 柱状多結晶膜 2の結晶性を向上することができる。  As described above, by forming the second insulating film 9 on the substrate 1, diffusion of impurities contained in the substrate 1, for example, boron (poron) or sodium, can be suppressed, and the crystal of the columnar polycrystalline film 2 can be suppressed. Performance can be improved.
なお、 第 2の絶縁膜 9は、 少なく とも、 酸素かあるいは窒素を含むも のであれぱよく、 二酸化珪素膜 S i 02以外にも例えば、 窒化膜 S i Nx やあるいは、 亜酸化窒化膜あるいは、 これらの複合膜を用いても同様の 効果が得られる n Note that the second insulating film 9 is minimum, oxygen or nitrogen is also to a long path and often contains, for example, in addition to the silicon dioxide film S i 0 2, or or a nitride film S i N x, nitrous oxide nitride film Alternatively, n the same effect by using these composite films are obtained
(実施の形態 3 )  (Embodiment 3)
以下に、 本発明の実施の形態 3について、 第 5図を用いて説明する。 第 5図は、 本允明の実施の形態 3によるある一定方向にそろった柱状 多結晶膜基板の断面図である。 なお、 上述の実施の形態 1と同じ構成要 素については同一の符号を付し説明を省略する。  Hereinafter, Embodiment 3 of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view of a columnar polycrystalline film substrate aligned in a certain direction according to Embodiment 3 of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
第 5図において、 柱状多結晶粒 4は、 某板 1面に対して結晶方位、 及 び結晶面がある一定の方向となるように整列している。 1 0は、 各結晶 粒の方向を示す結晶方位であり、結晶 ώはこの結晶方位 1 0に垂直に { 1 1 0} あるレヽは ί Ι Ο Ο} で配向している。  In FIG. 5, the columnar polycrystalline grains 4 are aligned such that the crystal orientation and the crystal plane are in a certain direction with respect to one surface of a certain plate. Reference numeral 10 denotes a crystal orientation indicating the direction of each crystal grain. The crystal ώ is perpendicular to the crystal orientation 10, and a layer having {110} is oriented as で ί Ο.
の柱状多結晶膜柱の柱状多結晶粒の整列は、 柱状多結晶膜 2に非 質相が含まれていても、その結晶化率が望ましくは 80 %以上であると、 得ることができる。 なお、 この均一形状の柱状多結晶粒 4からなる柱状 多結晶膜基板形成以降のプロセスは、 上述の実施の形態 1と同様なので 省略する。  The alignment of the columnar polycrystalline grains of the columnar polycrystalline film column can be obtained even if the columnar polycrystalline film 2 contains an amorphous phase, if the crystallization ratio is desirably 80% or more. Note that the processes after the formation of the columnar polycrystalline film substrate composed of the columnar polycrystalline grains 4 having the uniform shape are the same as those in Embodiment 1 described above, and a description thereof will be omitted.
以上のように、 本実施の形態 3によれば、 柱状結晶膜 2内の柱状結晶 粒 4が、 基板 1に対してある一定の方向に結晶方位、 及び結晶面がそろ つている構造としたので、 同一結晶粒内のみならず、 結晶粒界以外のす ベての結晶粒領域において、 エッチングの等方性、 あるいは異方性エツ テング速度を等しくすることができる。 従って、 エミッ夕を再現性よく 製造することができ、 広範囲に多数形成したエミッ夕において形状の均 一性を得ることが可能となる。 As described above, according to the third embodiment, the columnar crystal grains 4 in the columnar crystal film 2 have a structure in which the crystal orientation and the crystal plane are aligned in a certain direction with respect to the substrate 1. , Not only within the same crystal grain, but also The etching isotropic or anisotropic etching speed can be made equal in all the crystal grain regions. Therefore, the emitter can be manufactured with good reproducibility, and the uniformity of the shape can be obtained in a large number of emitters.
(実施の形態 4 )  (Embodiment 4)
以下に、 本発明の実施の形態 4について、 第 6図を用いて説明する。 第 6図は、 本発明の実施の形態 4による柱状多結晶膜 2を用いて製造 した冷電子放出素子のエミ ッタ部分の断面図である。 第 6図において、 1 1は、 柱状結晶粒の短い方の粒径を示す。 6は、 エミ ッ夕であり、 1 2は、 ェミッタの先端部である。 なお、 第 6図において、 上述の実施の 形態 1と同じ構成要素については、 同一符号を付し、 説明を省略する。 ェミ ッ夕先端部 1 2の曲率半径は、 一般的に曲率半径が 5 0 nm以上 であると、 引出しゲート電極 8 (上記第 2図 ( e) 参照) によるェミ ツ 夕先端部 1 2への電界集中が効率よく行われず、 シリコンの場合の電子 放出に必要な電界強度 1 06 V/mmを得るためには、 引出しゲ一ト電 極 8に 50 V以上の高い電圧を印加する必要がある。 駆動回路は、 ゲー ト電圧が 5 0 V以下が望ましいので、 エミ ッ夕先端部 1 2の曲率半径を 5 0 nm以下にすることが望ましい。 Hereinafter, Embodiment 4 of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view of an emitter part of a cold electron-emitting device manufactured using columnar polycrystalline film 2 according to Embodiment 4 of the present invention. In FIG. 6, 11 indicates the shorter particle size of the columnar crystal grains. 6 is the emitter, and 12 is the tip of the emitter. In FIG. 6, the same components as those in Embodiment 1 described above are denoted by the same reference numerals, and description thereof will be omitted. Generally, when the radius of curvature of the emitter tip 12 is 50 nm or more, the emitter tip 12 of the emitter gate electrode 8 (see FIG. 2 (e) above) is used. electric field concentration to is not performed efficiently, in order to obtain the electric field intensity 1 0 6 V / mm required for electron emission in the case of silicon, to apply a high voltage of more than 50 V to the extraction gate one preparative electrodes 8 There is a need. Since the drive circuit desirably has a gate voltage of 50 V or less, it is desirable that the radius of curvature of the emitter tip 12 be 50 nm or less.
また、 一般に、 珪素の冷電子放出の電界強度は 1 06V/mm以上必要 とされ、 ェミ ツ夕とェミ ッタに対して正に電圧 V (V) を印加する引出 しゲート電極との距離を d、 ェミ ツ夕の先端曲率十 Sを rとすると、 ェ ミッ夕の先端での電界強度 Fは ( 1 ) 式で表される。 In general, the field strength of the field emission of silicon is needed more than 1 0 6 V / mm, pull-out applies positive voltage V (V) with respect to E Mi Tsu evening and E Mi jitter and the gate electrode Assuming that the distance to is d and the radius of curvature at the tip of the emitter is r, the electric field strength at the tip of the emitter is expressed by equation (1).
F = 2 V/rLn ( 2 d/r) (V/mm) - ( 1 ) 上記 ( 1 ) において、 例えば、 d = 0. 5 X 1 0■ 6 (m) 、 V = 6 0、 80、 1 00 (V) としたときの、 エミヅ夕先端曲率十径 r に対する電 界強度 Fの関係を第 9図に示す。 図において、 Fを 1 0GV/mm以上得 るには、 V> 80 V、 r< 5 0 nmの条件を満たさなければならない。 そ のため、 rが大きくなればなるほど、 エミ ッ夕先端に 1 0 6V / m m以上 の電界をかけるために、 余計に電圧が必要であり、 逆に、 r が小さくな れば、 電圧は低くてすむ。 高電圧が必要になると、 ェミッタを制御する 駆動回路が複雑になり、 また、 引出しゲート電極の下部の絶緣層の耐圧 も問題になるため、 コス トの高い冷電子放出素子デバイスとなる。 した がって、 先端曲率を 5 0 n m以下とすることにより安価な低電圧駆動回 路を提供することができる。 F = 2 V / rLn (2 d / r) (V / mm)-(1) In the above (1), for example, d = 0.5 X 10 0 16 (m), V = 60, 80, FIG. 9 shows the relationship between the field intensity F and the radius of curvature of the radius of curvature Emi at the tip of 100 (V). In the figure, the condition of V> 80 V and r <50 nm must be satisfied to obtain F of 10 G V / mm or more. So For, the larger r is, in order to make a 1 0 6 V / mm or more electric field emitter Tsu evening tip, requires extra voltage, conversely, r is small lever, the voltage is low Help me. When a high voltage is required, the driving circuit for controlling the emitter becomes complicated, and the breakdown voltage of the insulating layer below the extraction gate electrode also becomes a problem, resulting in a high cost cold electron emission device. Therefore, an inexpensive low-voltage drive circuit can be provided by setting the tip curvature to 50 nm or less.
ところで、 このェミッタ先端部 1 2の曲率半径は、 通常のハロゲンガ スを用いた反応性エッチングや、 フッ酸を含む湿式エッチング法によれ ば、 曲率半径を極端に 5 0 n m以下、 例えば数 n m以下程度の鋭い形状 にすることは大変難しく、 通常は 5 0 n m程度になってしまう。 そのた め、 柱状結晶粒の短い方の粒径 1 1を 1 0 0 n m以上に形成することに より、 均一形状のェミ ッタを有する冷電子放出素子を実現できる。  By the way, the radius of curvature of the emitter tip 12 can be extremely reduced to 50 nm or less, for example, several nm or less according to reactive etching using ordinary halogen gas or wet etching including hydrofluoric acid. It is very difficult to make the shape as sharp as this, usually about 50 nm. Therefore, by forming the shorter grain size 11 of the columnar crystal grains to be 100 nm or more, a cold electron emitting device having a uniform-shaped emitter can be realized.
また、 エミ ッ夕先端部 1 2の曲率半径を 5 0 n rn程度の大きさで形成 した場合に、柱状結晶粒の短い方の粒径 1 1が 1 0 0 n mより小さいと、 結晶粒界 3がェミ ッタ先端部に位置する確率 (可能件) が高くなり、 曲 率半径 5 0 n m程度を持つェミ ッ夕先端部 1 2が粒界のために再現性よ く形成されなくなる。  In addition, when the radius of curvature of the emitter tip 12 is about 50 nrn, if the shorter grain size 11 of the columnar crystal grains is smaller than 100 nm, the grain boundary The probability (possible) that 3 is located at the emitter tip becomes higher, and the emitter tip 12 having a radius of curvature of about 50 nm will not be formed with good reproducibility due to grain boundaries. .
さらに、 結晶粒界 3には欠陥が多く、 欠陥がエミッ夕先端部 1 2に位 置すると、 放出電子量が減少してしまう。 以上の理由から、 柱状結晶粒 の短い方の粒径 1 1は、 1 0 0 n m以上で形成するのがよい。  Furthermore, the crystal grain boundary 3 has many defects, and if the defect is located at the tip 12 of the emitter, the amount of emitted electrons decreases. For the above reasons, the shorter grain size 11 of the columnar crystal grains is preferably formed to be 100 nm or more.
以上のように、 本実施の形態 4によれば、 上記柱状結晶粒の短い方の 粒径 1 1が少なく とも 1 0 0 n m以上であることとしたので、 エミ ッ夕 先端部 1 2にェツチング速度の異なる結晶粒界が存在せず、 エミ ッ夕先 端部 1 1を再現性よく形成することが可能となる。  As described above, according to the fourth embodiment, since the shorter particle size 11 of the columnar crystal grains is at least 100 nm or more, the etching is performed at the tip 12 of the emitter. Since there are no crystal grain boundaries having different velocities, it becomes possible to form the emitter end 11 with good reproducibility.
(実施の形態 5 )  (Embodiment 5)
以下に、 本発明の実施の形態 5について、 第 5図および第 2 ( e ) 図 を用いて説明する。 なお、 第 5図において、 上述の実施の形態 3と同じ 構成については、 同じ符号を用いて説明を省略する。 第 5図において、 1 0は、 各結晶粒の方向を表す結晶方位である。 各 結晶粒 4は、基板 1に対して 8 3 ° 以上の角度をもって形成されている。 これは、 ェミッタを形成するには、 最低 0 . 1 Ai mの粒径の柱状多結晶 膜 2の厚みが少なく とも 0 . 8〃m程度必要であり、 この際に、 ェミ ツ 夕先端部付近にできる限りエッチング速度の異なる結晶粒界が存在しな いようにするためには、 t a n ' 1 ( 0 . 8 / 0 . 1 ) = 8 3 ° が必要と なる。 また、 第 2 ( e ) 図に示すように、 ェミ ッ夕先端部 1 2に鼋界を 集中させて、 鼋子を引出すと、 電子はほぼ基板 1に対して垂直方向に流 れるため、 もし、 結晶粒が基板 1に対して 8 3。 以下であると、 電子が 粒界を横切りながら、 ェミッタ先端部まで流れなければならなくなる。 一方、 8 3 ° 以上であると、 電子は同じ結晶粒をエミ ッ夕先端部まで流 れることができ、 欠陥の多い粒界を横切らなくてすみ、 放出電流を減少 させなくてすむ。 Hereinafter, the fifth embodiment of the present invention will be described with reference to FIGS. 5 and 2 (e). In FIG. 5, the same components as those in the above-described third embodiment are denoted by the same reference numerals, and description thereof is omitted. In FIG. 5, 10 is a crystal orientation indicating the direction of each crystal grain. Each crystal grain 4 is formed at an angle of 83 ° or more with respect to substrate 1. In order to form an emitter, the thickness of the columnar polycrystalline film 2 having a grain size of at least 0.1 Aim must be at least about 0.8 μm. In order to prevent the existence of crystal grain boundaries having different etching rates as near as possible, tan ' 1 (0.8 / 0.1) = 83 ° is required. Also, as shown in FIG. 2 (e), when the field is concentrated on the emitter tip 12 and the electrons are extracted, the electrons flow almost perpendicularly to the substrate 1. If the crystal grain is 8 3 against the substrate 1. Below, electrons have to flow to the emitter tip, traversing the grain boundary. On the other hand, when the temperature is 83 ° or more, electrons can flow through the same crystal grain to the tip of the emitter, and do not need to cross a grain boundary with many defects, thereby reducing the emission current.
以上のように、 本実施の形態 5によれば、 各結晶粒 4を、 基板 1に対 して 8 3 ° 以上の角度をもって形成したので、 エミ ッ夕先端部にエッチ ング速度の異なる結晶粒界が存在せず、 ェミ ッタ先端部 1 1を再現性よ く形成することが可能となる。 また、 電子放出特性の優れた冷電子放出 素子を得ることができる。  As described above, according to the fifth embodiment, since each crystal grain 4 is formed at an angle of not less than 83 ° with respect to substrate 1, crystal grains having different etching speeds are formed at the tip of the emitter. There is no field, and the emitter tip 11 can be formed with good reproducibility. Further, a cold electron-emitting device having excellent electron emission characteristics can be obtained.
(実施の形態 6 )  (Embodiment 6)
以下に、 本発明の実施の形態 6について、 第 1図、 第 7図を用いて説 明する。 なお、 第 1図は、 上述した実施の形態 1において説明したため 各構成要素の説明は省略する。  Hereinafter, Embodiment 6 of the present invention will be described with reference to FIGS. 1 and 7. In addition, since FIG. 1 has been described in the first embodiment, the description of each component will be omitted.
柱状結晶粒 4の結晶面は、 { 1 1 0 } あるいは { 1 0 0 } 面配向とし た。 { 1 1 0 } 面配向としたのは、 柱状多結晶膜 2の配向面を { 1 1 0 } とすることにより、 結晶方位と結晶面がそろいやすくなり、 したがって、 均一形状なエッチングを可能とし、 大面積基板上に均一性の優れたエミ ッ夕を有する冷電子放出素子を実現するものである。  The crystal plane of the columnar crystal grain 4 was {110} or {100} plane oriented. The {110} plane orientation is achieved by setting the orientation plane of the columnar polycrystalline film 2 to {110} so that the crystal orientation and the crystal plane can be easily aligned, and therefore, a uniform shape etching can be performed. This realizes a cold electron-emitting device having an emitter with excellent uniformity on a large-area substrate.
さらに、 配向面を { 1 1 0 } あるいは { 1 0 0 } 面配向とすることに より、 柱状多結晶膜 2中の電子が半導体層を走行する際の粒界による電 子運動のエネルギー障壁を下げることができ、 移動度が増大し、 その結 果放出電子量の増大と高速応答を実現できる。 Furthermore, by setting the orientation plane to {110} or {100} plane orientation, the electrons in the columnar polycrystalline film 2 are transported by the grain boundaries when traveling through the semiconductor layer. The energy barrier of the child motion can be reduced, the mobility can be increased, and as a result, the amount of emitted electrons can be increased and a fast response can be realized.
また、 { 1 00} 面配向としたのは、 { 1 1 0} 面配向に比べて結晶 粒界の障壁を下げて、電子を流れやすくさせるためであるとともに、 { 1 00} 面配向にするとゲ一卜絶縁層と半導休結品面の界面におけるキヤ リアのトラップが { 1 1 0} 面配向に比べて少なくなり、 .導体—絶縁 層界面での電子がさらに流れやすくなるからであり、 より移動度が増大 し、 その結果放出電子量の増大と高速応答を実現できる。  Also, the {100} plane orientation is used to lower the crystal grain boundary barrier and facilitate the flow of electrons as compared with the {110} plane orientation. This is because the number of carrier traps at the interface between the gate insulating layer and the surface of the semiconducting insulator is smaller than in the {110} plane orientation, and electrons at the interface between the conductor and the insulating layer are more likely to flow. As a result, the mobility is further increased, and as a result, the amount of emitted electrons can be increased and a fast response can be realized.
本発明において実施した、 結晶構造の違いによる 1 000チップのェ ミ ッ夕からの放出電子量の測定量を第 7図に示す。 但し、 引出しゲ一卜 電極に印加する電圧は同じにしている。 第 7図において、 エミ ッ夕を配 向面 { 1 1 0}柱状多結晶膜 2で形成した場合、 非晶質 (アモルファス) シリコンの場合に比べて、 2倍以上もの放出電子量を示している。 放出 電子量は、 蛍光体からの発光輝度に関係しており、 輝度は放出電子量に 比例している。 すなわち、 同じ放出電子 S (発光輝度) を得るのに、 ェ ミ ッタを配向面 { 1 00} 柱状多結晶膜 2で形成した場合、 ァモルファ スシリコンの場合に比べて、 低い引出しゲート電極ですみ、 低電圧化を 図ることができる。  FIG. 7 shows the measured amount of electrons emitted from an emitter of 1,000 chips due to the difference in crystal structure, which was implemented in the present invention. However, the voltage applied to the extraction gate electrode is the same. In Fig. 7, when the emitter is formed with the {110} columnar polycrystalline film 2, the amount of emitted electrons is more than twice as large as that of amorphous silicon. I have. The amount of emitted electrons is related to the luminance of light emitted from the phosphor, and the luminance is proportional to the amount of emitted electrons. In other words, when the emitter is formed of the {100} columnar polycrystalline film 2 to obtain the same emitted electrons S (emission brightness), the extraction gate electrode is lower than that of amorphous silicon. Therefore, the voltage can be reduced.
さらに、 配向面 { 1 1 0 } 柱状多結晶膜の場合に比べて、 配向面 { 1 0 0} の方が、 冷電子放出素子からの電流量が増加しており、 低電圧化 を図ることができる。  Furthermore, the amount of current from the cold electron-emitting device is higher in the oriented plane {100} than in the case of the oriented plane {110} columnar polycrystalline film, and the voltage must be reduced. Can be.
以上のように、 本実施の形態 6'によれば、 柱状結晶粒の結晶面を { 1 1 0} あるいは { 1 00} 面配向とすれば、 放出電子量を増大させ、 低 電圧駆動で、 効率の良い冷電子放出素子を形成することが可能となる。 産業上利用可能性  As described above, according to Embodiment 6 ′, if the crystal plane of the columnar crystal grains is oriented in {110} or {100} plane, the amount of emitted electrons is increased, An efficient cold electron emitting element can be formed. Industrial applicability
本発明にかかるエミ ッ夕、 及びエミ ッ夕製造方法は、 基板上に柱状の 結晶粒を同じ結晶蚰に沿って成長させた柱状多結晶膜に対してエツチン グを施すことにより、 先端形状の整ったエミ ッ夕を再現性よく形成でき るため、 大面積基板上に多数のエミ ッ夕を形成した場合であっても、 ェ ミ ツ夕形状の均一性が得られる。 これにより、 ェミ ッタの形状の変動に 起因する冷電子放出素子の電子放出特性のバラツキを抑えることができ、 平面型両像表示装置や各種センサ一、 高周波発振器、 超高速デバイス、 電子顕微鏡、 電子ビーム露光装置など種々の電子ビーム利用装置の電子 源として利用することができる。 The emitter and the method of manufacturing an emitter according to the present invention are characterized in that etching is performed on a columnar polycrystalline film formed by growing columnar crystal grains on a substrate along the same crystal rod, whereby the tip shape is obtained. A well-formed emitter can be formed with good reproducibility. Therefore, even when a large number of emitters are formed on a large-area substrate, uniformity of the emitter shape can be obtained. As a result, it is possible to suppress variations in the electron emission characteristics of the cold electron emitter due to variations in the shape of the emitter, such as a flat panel dual image display device, various sensors, a high-frequency oscillator, an ultra-high-speed device, and an electron microscope. It can be used as an electron source for various electron beam utilizing devices such as an electron beam exposure device.

Claims

請求の範囲 The scope of the claims
1 . 基板上に柱状の結晶粒を同じ結晶軸に沿って成長させた柱状多結 晶膜に対してエッチングを施すことにより形成することを特徴とするェ ミッタ。  1. An emitter characterized by forming columnar crystal grains on a substrate by etching a columnar polycrystalline film grown along the same crystallographic axis.
2 . 基板上に柱状の結晶粒を同じ結晶軸に沿って成長させた柱状多結 晶膜を形成した後に、 上記柱状多結晶膜上に第 1の絶縁膜をパターニン グし、  2. After forming a columnar polycrystalline film in which columnar crystal grains are grown along the same crystal axis on the substrate, a first insulating film is patterned on the columnar polycrystalline film,
上記パターニングされた第 1絶縁膜を用いて、 上記柱状多結晶膜にェ ツチングを施すことにより形成することを特徴とするエミ ッ夕。  An emitter formed by performing etching on the columnar polycrystalline film using the patterned first insulating film.
3 . 基板上に第 2の絶縁膜が形成し、 上記第 2の絶縁膜上に柱状の結 晶粒を同じ結晶軸に沿って成長させた柱状多結晶膜を形成した後に、 上 記柱状多結晶膜上に第 1の絶縁膜をパターニングし、  3. A second insulating film is formed on the substrate, and a columnar polycrystalline film is formed on the second insulating film by growing columnar crystal grains along the same crystal axis. Patterning the first insulating film on the crystal film,
上記パターニングされた第 1の絶縁膜を用いて、 上記柱状多結晶膜に ェツチングを施すことにより形成することを特徴とするエミッタ。  An emitter formed by etching the columnar polycrystalline film using the patterned first insulating film.
4 . 請求の範囲第 1項乃至請求の範囲第 3項の何れかに記载のェミ ツ タにおいて、  4. In the emitter described in any one of claims 1 to 3,
上記柱状多結晶膜を構成する柱状結晶粒は、 基板面に対してある一定 の方向に結晶方位、 及び結晶 ώがそろつていることを特徴とするエミ ッ 夕。  An emitter characterized in that the columnar crystal grains constituting the columnar polycrystalline film have crystal orientations and crystal axes aligned in a certain direction with respect to the substrate surface.
5 . 請求の範囲第 1項乃至請求の範囲第 4項の何れかに記載のェミ ツ タにおいて、  5. In the emitter according to any one of claims 1 to 4,
上記柱状多結晶膜は、 少なく とも珪素を含むことを特徴とするエミ ッ 夕。  An emitter, wherein the columnar polycrystalline film contains at least silicon.
6 . 請求の範囲第 1項乃至請求の範囲第 5項に何れかに記載のェミ ッ 夕において、  6. In the emitter set forth in any one of claims 1 to 5,
上記柱状多結晶膜の配向 ώは、 { 1 1 0 } であることを特徴とするェ ミッタ。  An emitter, wherein the orientation の of the columnar polycrystalline film is {110}.
7 . 請求の範囲第 1項乃至請求の範囲第 5項の何れかに記載のェミ ッ 夕において、 上記柱状多結晶膜の配向面は、 { 1 0 0 }であることを特徴とするエミ ッ夕。 7. In the emitter set forth in any one of claims 1 to 5, An emitter characterized in that the orientation plane of the columnar polycrystalline film is {100}.
8 . 請求の範囲第 1項乃至請求の範囲第 7項の何れかに記載のェミ ッ 夕において、  8. In the emitter set forth in any one of claims 1 to 7,
上記柱状多結晶膜にエッチングを施すことにより形成されたェミ ッタ 先端の曲率半径が 5 0 n m以下であることを特徴とするエミ クタ。  An emitter characterized in that the radius of curvature at the tip of the emitter formed by etching the columnar polycrystalline film is 50 nm or less.
9 . 請求の範囲第 1項乃至請求の範囲第 8項の何れかに記載のエミ ッ タにおいて、  9. In the emitter according to any one of claims 1 to 8,
上記柱状結晶膜を構成する柱状結晶粒は、 該柱状結晶粒の短い方の粒 佳が、 少なく とも 1 0 0 n m以上であることを特徴とするエミッ夕。  The columnar crystal grains constituting the columnar crystal film, wherein the shorter one of the columnar crystal grains is at least 100 nm or more.
1 0 . 請求の範囲第 9項に記載のエミッ夕において、  10. In the case of the emissions set forth in claim 9,
上記柱状結晶粒と基板のなす角度は 8 3 。 以上であることを特徴とす るエミ ッ夕。  The angle between the columnar crystal grains and the substrate is 83. Emit evening characterized by the above.
1 1 . 請求の範囲第 3項に記載のェミッタにおいて、  1 1. In the emitter described in claim 3,
上記第 2の絶縁膜は、 少なく とも、 酸素かあるいは窒素を含むことを 特徴とするェミ ッタ。  The emitter, wherein the second insulating film contains at least oxygen or nitrogen.
1 2 . 請求の範囲第 2項または請求の範囲第 3項に記載のェミ ツ夕に おいて、  1 2. In the event set forth in Claim 2 or Claim 3,
上記パ夕一ニングされた第 1の絶縁膜は、 円形状であることを特徴と するエミ ッ夕。  The above-mentioned patterned first insulating film has a circular shape.
1 3 . 請求の範囲第 2項または請求の範囲第 3項に記載のエミ ッタに おいて、  1 3. In the emitter according to claim 2 or claim 3,
上記パターニングされた第 1の絶縁膜は、 多角形状であることを特徴 とするエミ ッ夕。  The above-mentioned patterned first insulating film has a polygonal shape.
1 4 . 基板上に柱状の結晶粒を同じ結晶軸に沿って成長させて柱状多 結晶膜を形成する工程と、  14. a step of growing columnar crystal grains on the substrate along the same crystal axis to form a columnar polycrystalline film;
上記柱状多結晶膜に対してエッチングを施す工程とを有することを特 徴とするエミッタ製造方法。  Performing a step of etching the columnar polycrystalline film.
1 5 . 基板上に柱状の結晶粒を同じ結晶軸に沿って成長させて柱状多 結晶膜を形成する工程と、 1 5. Growing columnar crystal grains along the same crystal axis on the substrate Forming a crystalline film;
上記柱状多結晶膜 に第 1の絶縁膜をパターニングする工程と、 上記パターニングされた第 1絶縁膜を用いて、 上記柱状多結晶膜をェ Patterning a first insulating film on the columnar polycrystalline film; and etching the columnar polycrystalline film using the patterned first insulating film.
'ソチングする工程とを有することを特徴とするエミ ッ夕製造方法。 A process for producing an emitter.
1 6 . 基板上に第 2の絶縁膜を形成する工程と、  16. A step of forming a second insulating film on the substrate;
上記第 2の絶縁膜上に柱状の結晶粒を同じ結晶軸に沿って成長させた 柱状多結晶膜を形成する工程と、  Forming a columnar polycrystalline film in which columnar crystal grains are grown along the same crystal axis on the second insulating film;
上記柱状多結晶膜上に第 1の絶縁膜をパターニングする T.程と、 上記パターニングされた第 1の絶縁膜を用いて、 上記柱状多結晶膜を エッチングする工程とを有することを特徴とするエミ ッ夕製造方法。  Patterning a first insulating film on the columnar polycrystalline film; and etching the columnar polycrystalline film using the patterned first insulating film. Emitter manufacturing method.
1 7 . 請求の範囲第 1 4項乃至請求の範囲第 1 6項の何れかに記載の ェミ ッ夕製造方法において、  17. The method for producing an EMI according to any one of claims 14 to 16,
上記柱状多結晶膜を構成する柱状結晶粒は、 基板面に対してある一定 の Iら Jに結晶方位、 及び結晶面がそろっていることを特徴とするエミ ヅ タ製造方法。  An emitter manufacturing method, characterized in that the columnar crystal grains constituting the columnar polycrystalline film have crystal orientations and crystal planes in a certain range from I to J with respect to the substrate surface.
1 8 . 請求の範囲第 1 4項及至請求の範囲第 1 7項の何れかに記載の ェミ ッタ製造方法において、  18. The method for manufacturing an emitter according to any one of claims 14 to 17
上記柱状多結品膜は、 少なく とも珪素を含むことを特徴とするエミ ッ タ製造方法。  The method for manufacturing an emitter, wherein the columnar multiple product film contains at least silicon.
1 9 . 請求の範囲第 1 4項乃至請求の範囲第 1 8項の何れかに記載の ェミ ッタ製造方法において、  19. The method for manufacturing an emitter according to any one of claims 14 to 18,
上記柱状多結晶膜の配向面は、 { 1 1 0 } であることを特徴とするェ ミ ッタ製造方法。  A method for manufacturing an emitter, wherein the orientation plane of the columnar polycrystalline film is {110}.
2 0 . 請求の範囲第 1 4項乃至請求の範囲第 1 8項の何れかに記載の エミ ヅ夕製造方法において、  20. The method for manufacturing an Emi device according to any one of claims 14 to 18
上記柱状多結晶膜の配向面は、 { 1 0 0 } であることを特徴とするェ ミ ツ夕製造方法。  An emitter manufacturing method, wherein the orientation plane of the columnar polycrystalline film is {100}.
2 1 . 請求の範囲第 1 4項乃至請求の範囲第 2 0項の何れかに記載の エミ ッタ製造方法において、 エミ ッ夕先端の曲率半径が 5 0 n m以下となるように、 上記柱状多結 晶膜にエッチングを施すことを特徴とするエミッ夕製造方法。 21. The method of manufacturing an emitter according to any one of claims 14 to 20. A method for producing an emitter, comprising etching the columnar polycrystalline film so that the radius of curvature at the tip of the emitter is 50 nm or less.
2 2 . 請求の範囲第 1 4項乃至請求の範囲第 2 1項の何れかに記載の エミ ッタ製造方法において、  22. The emitter manufacturing method according to any one of claims 14 to 21.
上記柱状結晶膜中の柱状結晶粒は、 該柱状結晶粒の短い方の粒径が、 少なく とも 1 0 0 n m以上であることを特徴とするエミ ツ夕製造方法。  The columnar crystal grains in the columnar crystal film, wherein the shorter one of the columnar crystal grains has a particle size of at least 100 nm or more.
2 3 . 請求の範囲第 2 2項に記載のエミ ッ夕製造方法において、 上記杵状結晶粒と基板のなす角度は、 8 3 0 以上であることを特徴と するエミッタ製造方法。 2 3. In Emi Tsu evening production method according to the second item 2 claims, the angle of the punch-like grains and the substrate, an emitter fabrication method, characterized in that at 8 3 0 or more.
2 4 . 請求の範開第 1 6項に記載のエミ ッタ製造方法において、 上記第 2の絶縁膜は、 少なく とも、 酸素、 あるいは窒素を含むことを 特徴とするエミ ッタ製造方法。  24. The method for manufacturing an emitter according to claim 16, wherein the second insulating film contains at least oxygen or nitrogen.
2 5 . 請求の範囲第 1 5項または請求の範囲第 1 6項に記載のェミ ッ 夕製造方法において、  25. In the method of manufacturing an EMI lamp according to claim 15 or claim 16,
上記パターニングされた第 1の絶縁膜は、 円形状であることを特徴と するエミ ッタ製造方法。  The method for manufacturing an emitter according to claim 1, wherein the patterned first insulating film has a circular shape.
2 6 . 請求の範囲第 1 5項または請求の範囲第 1 6項に記載のエミ ッ 夕製造方法において、  26. In the method for producing an emitter according to claim 15 or claim 16,
上記パ夕一二ングされた第 1の絶縁膜は、 多角形状であることを特徴 とするェミ ッタ製造方法。  The method for manufacturing an emitter, wherein the first insulating film formed in the above-mentioned manner has a polygonal shape.
2 7 . 請求の範囲第 1 5項または請求の範囲第 1 6項に記載のエミ ッ 夕製造方法によりェミ ツ夕を製造する工程と、  27. A step of producing an emitter by the method for producing an emitter according to claim 15 or claim 16,
上記柱状多結晶膜上にパターニングされた第 1の絶縁膜を残したまま、 第 3の絶縁層と引出しゲー卜電極を形成する工程と、  Forming a third insulating layer and an extraction gate electrode while leaving the first insulating film patterned on the columnar polycrystalline film;
上記柱状多結晶膜上にパターニングされた第 1の絶縁膜の上部のみを 除去して開口部を形成する工程とを有することを特徴とする冷電子放出 素子の製造方法。  Removing only the upper part of the first insulating film patterned on the columnar polycrystalline film to form an opening.
PCT/JP2000/004114 1999-06-24 2000-06-23 Emitter, emitter fabricating method, and cold electron emitting device fabricating method WO2000079556A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020017002346A KR20010072923A (en) 1999-06-24 2000-06-23 Emitter, emitter fabricating method, and cold electron emitting device fabricating method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11/178500 1999-06-24
JP17850099 1999-06-24

Publications (1)

Publication Number Publication Date
WO2000079556A1 true WO2000079556A1 (en) 2000-12-28

Family

ID=16049558

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/004114 WO2000079556A1 (en) 1999-06-24 2000-06-23 Emitter, emitter fabricating method, and cold electron emitting device fabricating method

Country Status (5)

Country Link
KR (1) KR20010072923A (en)
CN (1) CN1318203A (en)
ID (1) ID27523A (en)
TW (1) TW469463B (en)
WO (1) WO2000079556A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1184885A1 (en) * 2000-08-31 2002-03-06 Japan Fine Ceramics Center Method of manufacturing electron-emitting element and electronic device
WO2011121778A1 (en) * 2010-03-31 2011-10-06 日新電機株式会社 Thin film polycrystalline silicon and process for production thereof, and plasma device for production of thin film polycrystalline silicon
US11121100B2 (en) 2015-10-19 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Trap layer substrate stacking technique to improve performance for RF devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100926151B1 (en) * 2007-07-18 2009-11-10 한국원자력연구원 Method for preparing carbon nanotube large area emitter by using carbon nanotube-polymer composite

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04167325A (en) * 1990-10-30 1992-06-15 Sony Corp Field emission type emitter
JPH08306303A (en) * 1995-05-08 1996-11-22 Fuji Electric Co Ltd Microscopic cold electron source and its manufacture
JPH09129123A (en) * 1995-05-11 1997-05-16 Toppan Printing Co Ltd Electron emitting element and manufacture thereof
JP2740444B2 (en) * 1992-05-13 1998-04-15 マイクロン・テクノロジー・インコーポレイテッド Electron emission array and method of manufacturing the same
JPH10312736A (en) * 1997-05-13 1998-11-24 Ricoh Co Ltd Electron emitting element and method for forming cathode thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04167325A (en) * 1990-10-30 1992-06-15 Sony Corp Field emission type emitter
JP2740444B2 (en) * 1992-05-13 1998-04-15 マイクロン・テクノロジー・インコーポレイテッド Electron emission array and method of manufacturing the same
JPH08306303A (en) * 1995-05-08 1996-11-22 Fuji Electric Co Ltd Microscopic cold electron source and its manufacture
JPH09129123A (en) * 1995-05-11 1997-05-16 Toppan Printing Co Ltd Electron emitting element and manufacture thereof
JPH10312736A (en) * 1997-05-13 1998-11-24 Ricoh Co Ltd Electron emitting element and method for forming cathode thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1184885A1 (en) * 2000-08-31 2002-03-06 Japan Fine Ceramics Center Method of manufacturing electron-emitting element and electronic device
US6958571B2 (en) 2000-08-31 2005-10-25 Sumitomo Electric Industries, Ltd. Electron-emitting device
WO2011121778A1 (en) * 2010-03-31 2011-10-06 日新電機株式会社 Thin film polycrystalline silicon and process for production thereof, and plasma device for production of thin film polycrystalline silicon
US11121100B2 (en) 2015-10-19 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Trap layer substrate stacking technique to improve performance for RF devices
US11121098B2 (en) 2015-10-19 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Trap layer substrate stacking technique to improve performance for RF devices

Also Published As

Publication number Publication date
TW469463B (en) 2001-12-21
CN1318203A (en) 2001-10-17
KR20010072923A (en) 2001-07-31
ID27523A (en) 2001-04-12

Similar Documents

Publication Publication Date Title
US7042148B2 (en) Field emission display having reduced power requirements and method
US6062931A (en) Carbon nanotube emitter with triode structure
US6130143A (en) Quantum wires formed on a substrate, manufacturing method thereof, and device having quantum wires on a substrate
US5302238A (en) Plasma dry etch to produce atomically sharp asperities useful as cold cathodes
KR0152251B1 (en) Process for preparation of diamond. like carbon tft-lcd
US9058954B2 (en) Carbon nanotube field emission devices and methods of making same
US5757344A (en) Cold cathode emitter element
US5844252A (en) Field emission devices having diamond field emitter, methods for making same, and methods for fabricating porous diamond
JPH07176745A (en) Semiconductor element
JPH09142821A (en) Accumulation of amorphous silicon-based film
JP2001167721A (en) Electric field discharge display element and manufacturing method of the same
JP2012031000A (en) Grain-arranged diamond film, and method for production thereof
JP2002075171A (en) Manufacturing method of electron emission element and electronic device
KR100449071B1 (en) Cathode for field emission device
WO2000079556A1 (en) Emitter, emitter fabricating method, and cold electron emitting device fabricating method
KR101018448B1 (en) Catalyst structure particularly for the production of field emission flat screens
JPH02142041A (en) Diode, triode or element such as flat integrated cathode ray liminescence display unit and manufacture thereof
JP4312352B2 (en) Electron emission device
JP3908898B2 (en) Etching method of carbon-based material
JP2002352694A (en) Electrode, electron emission element and device using it
US5893787A (en) Application of fast etching glass for FED manufacturing
JP2000188388A (en) Manufacture of semiconductor device and semiconductor device
US6517405B1 (en) Process for forming a film on a substrate having a field emitter
EP1003196A1 (en) Carbon material, method for manufacturing the same material, field-emission type cold cathode using the same material and method for manufacturing the same cathode
JP4350120B2 (en) Diamond etching method

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 00801476.0

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): CN ID JP KR SG US

WWE Wipo information: entry into national phase

Ref document number: 1020017002346

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 09763651

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 1020017002346

Country of ref document: KR

WWR Wipo information: refused in national office

Ref document number: 1020017002346

Country of ref document: KR