JP3826539B2 - Method for manufacturing cold electron-emitting device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a field emission cold electron-emitting device that emits electrons by a strong electric field and a method of manufacturing the same. More specifically, as an electron generation source or electron gun for an optical printer, an electron microscope, an electron beam exposure apparatus, or the like, or as an ultra-compact illumination source for an illumination lamp, in particular, an array of FEA (so-called Field Emitter) constituting a flat display. Array) Cold electron emitters useful as electron generation sourcesOf childIt relates to a manufacturing method.
[0002]
[Prior art]
  Conventionally, a cathode ray tube has been widely used as an electronic display device. However, the cathode ray tube consumes a large amount of energy in order to emit thermal electrons from the cathode of an electron gun, and requires a large volume structurally. There was a problem.
[0003]
  For this reason, there is a demand for a flat display that can use cold electrons instead of thermal electrons to reduce energy consumption as a whole, and further downsize the device itself. Realization of high-speed response and high resolution is strongly demanded for the type display.
[0004]
  As a structure of a flat display using such cold electrons, a structure in which micro cold electron-emitting devices are arranged in an array in a high-vacuum flat plate cell is considered promising. As a cold electron-emitting device used for this purpose, a field emission type cold electron-emitting device using a field emission phenomenon has attracted attention. In this field emission type cold electron emission device, when the strength of the electric field applied to the material is increased, the width of the energy barrier on the surface of the material is gradually reduced according to the strength, and a strong electric field with an electric field strength of 107 V / cm or more is obtained. This makes use of the phenomenon that electrons in a substance can break through its energy barrier by the tunnel effect, and thus electrons are emitted from the substance. In this case, since the electric field follows Poisson's equation, if a portion where the electric field concentrates is formed on the member (emitter) that emits electrons, cold electrons can be efficiently emitted with a relatively low extraction voltage.
[0005]
  As a general example of such a field emission type cold electron emission element, a conical cold electron emission element having a sharp tip can be exemplified as shown in FIG. In this element, a conductive layer 52, an insulating layer 53, and a gate electrode 54 are sequentially stacked on an insulating substrate 51, and an opening A reaching the conductive layer 52 is formed in the insulating layer 53 and the gate electrode 54. Has been. A conical emitter 55 having a dot-like projection Po is formed on the conductive layer 52 in the opening A so as not to contact at least the gate electrode 54.
[0006]
  Among such conical emitters, Spindt-type emitters are widely known.
[0007]
  An example of manufacturing a cold electron-emitting device having a Spindt-type emitter will be described with reference to FIGS.
[0008]
  First, as shown in FIG. 6A, an insulating layer 63 and a gate electrode 64 are sequentially formed on an insulating substrate 61 on which a conductive layer 62 has been previously formed by a sputtering method, a vacuum evaporation method, or the like. Subsequently, a circular hole (gate hole) is opened in part of the insulating layer 63 and the gate electrode 64 by using a photolithography method and a reactive ion etching method (RIE) until the conductive layer 62 is exposed. Etch into.
[0009]
  Next, as shown in FIG. 6B, a lift-off material 65 is formed only on the upper surface and side surfaces of the gate electrode 64 by oblique vapor deposition. As the material of the lift-off material 65, Al, MgO or the like is often used.
[0010]
  Subsequently, as shown in FIG. 6C, a metal material for the emitter 66 is deposited on the conductive layer 62 from the perpendicular direction by ordinary anisotropic deposition. At this time, as the deposition proceeds, the opening diameter of the gate hole is narrowed, and at the same time, the conical emitter 66 is formed on the conductive layer 62 in a self-aligning manner. Deposition is performed until the gate hole is finally closed. As the material of the emitter, Mo, Ni or the like is used.
[0011]
  Finally, as shown in FIG. 6D, the lift-off material 65 is removed by etching, and the gate electrode 64 is patterned as necessary. As a result, a cold electron emission device including a Spindt-type emitter is obtained.
[0012]
  The cold electron emission device having such a Spindt-type emitter has an advantage that a conical emitter can be easily formed in a self-aligning manner by anisotropic vapor deposition, and further, a wide range of emitter materials can be selected. . After emitter wiring
[0013]
  When applying cold electron-emitting devices that use microfabrication technology, represented by Spindt-type emitters, to flat displays, etc., it is indispensable to obtain high-quality image quality because the emission current fluctuation from the emitter is small. It is.
[0014]
  The fluctuation of the emission current can be reduced to some extent by integrating the emitter. This is because the influence of variations in emission characteristics among individual emitters is reduced by integration. However, since this method merely apparently averages the emission current from each emitter, it is impossible to suppress an abnormally large emission current that appears locally.
[0015]
  As a means for reducing such a variation in emission current, US Pat. No. 3,789,471 discloses a technique for providing a resistive layer between a conductive layer and an emitter in a Spindt emitter.
Skill is shown.
[0016]
  A configuration example of a cold electron emission device having such a resistance layer will be described with reference to FIG.
[0017]
  A conductive layer 72, a resistance layer 73, an insulating layer 74, and a gate electrode 75 are sequentially stacked on the insulating substrate 71, and an opening A reaching the resistance layer 73 is formed in the insulating layer 74 and the gate electrode 75. ing. A conical emitter 76 is formed on the resistance layer 73 in the opening A so as not to contact at least the gate electrode 75.
[0018]
  In this case, the resistance layer 73 is electrically inserted between the conductive layer 72 and the emitter 76 in series. The resistance layer 73 has an effect of making the current between the elements uniform, further reduces a large current that leads to element destruction, and also reduces fluctuations in the emission current in proportion to the resistance value of the resistance layer 73. It becomes possible. The specific resistance of the resistance layer 73 is generally about 102 to 10 6 Ω · cm.
[0019]
  On the other hand, silicon emitters using semiconductor integrated circuit manufacturing technology are also widely known.
(Tech. Dig. IVMC., (1991) p26)
[0020]
  An example of manufacturing a cold electron emission device including a silicon emitter will be described with reference to FIGS.
[0021]
  First, as shown in FIG. 8A, a single crystal silicon substrate 81 is thermally oxidized to form a silicon oxide layer on the surface, and the silicon oxide layer is patterned into a circular shape using a photolithography method. A circular silicon oxide layer 82 for etching mask is formed. This silicon oxide layer 82 also functions as a lift-off material as will be described later. The diameter of the silicon oxide layer 82 substantially corresponds to the gate diameter.
[0022]
  Next, as shown in FIG. 8B, the silicon substrate 81 is etched by reactive ion etching (RIE) under a condition with a high side etch rate to form an emitter 83.
[0023]
  Subsequently, as shown in FIG. 8C, an emitter tip sharpening silicon oxide layer 84 is formed on the surfaces of the silicon substrate 81 and the emitter 83 by thermal oxidation. Due to the stress generated when the silicon oxide layer 84 is formed, the tip of the emitter 83 inside the silicon oxide layer 84 is easily sharpened.
[0024]
  Then, as shown in FIG. 8D, an insulating layer 85 and a gate electrode 86 are stacked by anisotropic vapor deposition.
  Finally, as shown in FIG. 8E, the etching mask silicon oxide layer 82 that also functions as a lift-off material is lifted off by etching, and the silicon oxide layer 84 on the surface of the emitter 83 is removed by etching. Then, the gate electrode 86 is patterned as necessary. As a result, a cold electron emission device including a silicon emitter is obtained.
[0025]
  More recently, it has been shown that silicon current can be controlled at a high level by utilizing the properties of silicon as a semiconductor. (Jpn. J. Appl. Phys. Vol. 35 (1996) p6637). A silicon emitter having such a current control function is referred to as a MOSFET structure emitter. The configuration of the cold electron-emitting device provided with this MOSFET structure emitter will be described with reference to FIG.
[0026]
  On the same plane of the p-type silicon substrate 91, an emitter wiring layer 94 is provided via a conical emitter 92 made of n-type silicon and an n-type silicon layer 93, and an insulating layer is provided between the emitter 92 and the emitter wiring layer 94. A gate electrode 96 is provided through 95. That is, this emitter has a structure in which a MOSFET (so-called metal oxide semiconductor-effect effect transistor) structure is built in the cold electron emitter, the emitter wiring layer 94 of the cold electron emitter is the source of the MOSFET, the emitter 92 is the drain, the gate The electrode 96 functions as a gate and the insulating layer 95 functions as a gate insulating film.
[0027]
  An example of manufacturing a cold electron-emitting device having a MOSFET structure emitter will be described with reference to FIGS.
[0028]
  First, as shown in FIG. 10A, a single crystal p-type silicon substrate 101 is thermally oxidized to form a silicon oxide layer 102 on the surface, and the silicon oxide layer 102 is formed into a circular shape by using a photolithography method. By patterning, a circular etching mask silicon oxide layer 102 is formed. This silicon oxide layer 102 also functions as a lift-off material as will be described later. Note that the diameter of the silicon oxide layer 102 substantially corresponds to the gate diameter.
[0029]
  Next, as shown in FIG. 10B, the p-type silicon substrate 101 is etched by a reactive ion etching method (RIE) under a condition with a high side etch rate to form an emitter 103.
[0030]
  Subsequently, as shown in FIG. 10C, a silicon oxide layer 104 for sharpening the emitter tip and for the insulating layer is formed on the surfaces of the p-type silicon substrate 101 and the emitter 103 by thermal oxidation. Due to the stress generated when the silicon oxide layer 104 is formed, the tip of the emitter 103 inside the silicon oxide layer 104 is easily sharpened.
[0031]
  Then, as shown in FIG. 10D, a gate electrode 105 material is formed, and a circular hole pattern for emitter wiring is formed on the gate electrode 106 material using a photolithography method.
[0032]
  Next, as shown in FIG. 10E, the etching mask silicon oxide layer 102 that also functions as a lift-off material is lifted off by etching, and the silicon oxide layer 104 on the surface of the emitter 103 is removed by etching and the emitter wiring is also removed. Form holes.
[0033]
  Subsequently, as shown in FIG. 10F, after phosphorus is ion-implanted, diffusion annealing is performed to make the emitter 103 n-type, and an n-type silicon layer 106 is formed on the surface of the emitter wiring hole.
[0034]
  Finally, as shown in FIG. 10G, after forming a metal thin film 107 such as aluminum as an electrode material for the emitter wiring and the gate wiring, the gate electrode 105 is patterned as necessary. As a result, a cold electron-emitting device having a MOSFET structure emitter is obtained.
[0035]
  In a cold electron emission device composed of a silicon emitter having such a MOSFET structure, although it can be easily manufactured in substantially the same manufacturing process as a conventional silicon emitter, a transistor control is realized by incorporating a MOS transistor in the device. Therefore, it is possible to obtain a very stable emission current and to eliminate the generation of a large local current, so that there is a great feature that element destruction cannot occur in principle.
[0036]
  However, in a cold electron emission device provided with a resistance layer for current stabilization, in order to obtain a sufficient current reduction characteristic for a local large current, it is necessary to provide a larger resistance, There is a problem that fluctuations can only be reduced relative to the characteristics of the individual elements, and that in principle an increase in operating voltage is unavoidable.
[0037]
  On the other hand, a silicon emitter having a MOSFET structure equipped with a current control function can obtain a stable current at a very high level by transistor control. However, an electrode configuration in which the emitter and the emitter wiring are located on the same plane is necessary. Therefore, there is a problem that it is difficult to obtain matrix wiring.
[0038]
[Problems to be solved by the invention]
  The present invention is intended to solve the above-described problems of the prior art, and by incorporating a current control function in the element itself, a local large current can be suppressed without increasing the operating voltage, and the current can be reduced. Field emission type cold electron emission element capable of minimizing fluctuations and easily forming matrix array wiringOf childAn object is to provide a manufacturing method.
[0039]
[0040]
[0041]
[0042]
[0043]
[Means for Solving the Problems]
The present invention is for solving the above-mentioned problems.
  An insulating layer and a gate electrode are sequentially stacked on a conductive substrate, an opening reaching the conductive substrate is provided in the gate electrode and the insulating layer, and an emitter is provided on the conductive substrate in the opening. In the field emission cold electron-emitting device formed so as not to contact
  The conductive substrate is a p-type silicon substrate, and an emitter and an emitter wiring layer are arranged via n-type silicon layers respectively provided on the same plane on the p-type silicon substrate, and the emitter wiring layer A manufacturing method for manufacturing a cold electron-emitting device having an insulating layer and a gate electrode formed thereon,
  (A) A silicon oxide layer is formed on the surface of the p-type silicon substrate by thermal oxidation, and then the silicon oxide layer is patterned to form an emitter hole and an emitter wiring hole. The emitter hole and the emitter wiring Forming an n-type silicon layer in the hole by ion implantation;
  (B) forming an emitter wiring layer material by forming an emitter wiring layer material on the n-type silicon layer generated in the emitter wiring hole and patterning the emitter wiring layer material;
  (C) An insulating material layer and a gate electrode material layer are sequentially formed on the silicon oxide layer and the emitter wiring layer, and a hole pattern having an opening for forming a gate is formed by a photolithography method. And etching the gate electrode material layer and the insulating material layer by reactive ion etching until the n-type silicon layer is exposed, thereby forming the gate hole, and the gate electrode and the insulating layer;
  (D) A lift-off material is deposited only on the top and side surfaces of the gate electrode by oblique deposition, and a lift-off layer is formed. Filming and self-aligning emitter formation;
  (E) peeling off the lift-off layer and peeling off the emitter material on the gate electrode;
A cold electron-emitting device manufacturing method comprising all the steps (a) to (e).
[0044]
  Claim2The invention shown in claim1In particular, the step (b) is characterized in that, after the emitter wiring layer is formed, the silicon oxide layer is removed by etching.
[0045]
  Claim3The invention shown in claim2In particular, in the step (a), in place of the silicon oxide layer provided by thermal oxidation, a metal thin film layer or a ceramic thin film layer provided by a thin film forming method is used, and
  The step (b) is characterized in that after the emitter wiring layer is formed, the metal thin film layer or the ceramic thin film layer is removed by etching.
[0046]
  Claim4The invention shown in claim1Thru3In particular, in the step (c), the insulating layer material is amorphous silicon nitride, and the reaction gas is a PECVD method using a mixed gas composed of either silane or disilane and ammonia. It is formed by.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, the present invention will be described in detail with reference to the drawings.
[0048]
  FIG. 1 is a cross-sectional view of a cold electron emission device of the present invention. As shown in the figure, this cold electron-emitting device has a structure in which a p-type silicon substrate 1, an insulating layer 2, and a gate electrode 3 are sequentially laminated. An opening A reaching the emitter wiring layer 2 is provided in the gate electrode 3 and the insulating layer 2 on the p-type silicon substrate 1, and the surface of the p-type silicon substrate 1 in the opening A is n. A type silicon layer 4 is formed, and a conical or frustoconical emitter 5 is formed on the n type silicon layer 4 so as not to contact the gate electrode 3. Further, an emitter wiring layer 7 is formed on the same surface adjacent to the emitter 5 and on the n-type silicon layer 6 formed on the surface of the p-type silicon substrate 1 below the insulating layer 2 and the gate electrode 3. ing.
[0049]
  In the present invention, the p-type silicon substrate 1 functions as a MOSFET channel in addition to being used as a support substrate for a cold electron-emitting device. Such a p-type silicon substrate preferably has a resistance value of several tens of Ω · cm or less from the viewpoint of the characteristics of the MOSFET.
[0050]
  The insulating layer 2 is a layer for electrically insulating the emitter 5 and the emitter wiring layer 7 from the gate electrode 3. Furthermore, it is used simultaneously for electrically insulating the p-type silicon substrate 1 and the gate electrode 3. That is, it also functions as a gate insulating film of MOSFET. Such an insulating layer 2 can be formed from a known material used as an insulating layer of a cold electron-emitting device, but it has a particularly good insulating property and can provide a pinhole-free film. Examples thereof include a silicon oxide film and a silicon nitride film by a so-called Plasma Enhanced Chemical Vapor Deposition method.
[0051]
  As for the thickness of the insulating layer 2, it is sufficient that sufficient insulation is maintained between the emitter 5, the emitter wiring layer 7 and the p-type silicon substrate 1 and the gate electrode 3, for example, 0.2 to 2 μm, preferably 0.3 to 0.7 μm.
[0052]
  The gate electrode 3 is an electrode for concentrating a strong electric field on the emitter 5. As a material of the gate electrode 3, a material having a high melting point from the viewpoint of current resistance and having resistance to an etching solution used for forming an emitter can be used. Preferably, Cr, W, Ta or Nb is used. Can be mentioned. Among them, it is preferable to use Nb from the viewpoint of adhesion with the base.
[0053]
  The thickness of the gate electrode 3 can be appropriately determined as necessary, but is 0.1 to 0.5 μm.
[0054]
  The n-type silicon layer 4 is a layer that forms a pn junction with the p-type silicon substrate 1 and makes ohmic contact with the emitter 5 and functions as the drain of the MOSFET.
[0055]
  The n-type silicon layer 6 is a layer that forms a pn junction with the p-type silicon substrate 1 and makes ohmic contact with the emitter wiring layer 7 and functions as a drain of the MOSFET.
[0056]
  These n-type silicon layers are required to form a good pn junction with the p-type silicon substrate 1 in order to form a MOSFET, and to obtain good ohmic contact with the emitter 5 and the emitter wiring layer 7. An example of such an n-type silicon layer is a layer formed by a phosphorus ion implantation method.
[0057]
  The emitter 5 is a member that directly emits electrons from the surface thereof. In the present invention, a metal thin film or a non-single-crystal silicon thin film on the n-type silicon layer 4 of the p-type silicon substrate 1 is used. Here, when the emitter is formed of a non-single crystal silicon thin film, for example, a polysilicon thin film or an amorphous silicon thin film, the emitter itself has a certain resistance, so that more stable emission characteristics can be obtained.
[0058]
  The thickness (height) of the entire emitter 5 can be appropriately determined as necessary, but is usually preferably 0.3 to 2 μm.
[0059]
  The shape of the emitter 5 is preferably a conical shape or a cylindrical shape, or a truncated cone shape or a polygonal frustum shape.
[0060]
  The emitter wiring layer 7 is formed from a material having low wiring resistance and high adhesion to the underlying silicon material. Particularly preferable examples of such a material include Cr, Al, and a Cr laminated film.
[0061]
  The thickness of the emitter wiring layer 7 is not particularly limited as long as sufficient wiring resistance and adhesion can be obtained, but is usually 0.05 to 0.5 μm, preferably 0.1 to 0.3 μm.
[0062]
  Next, a method for manufacturing a cold electron-emitting device according to the present invention will be described in detail with reference to FIGS.
[0063]
    Step (a)
  First, the p-type silicon substrate 11 is thermally oxidized to form a thermally oxidized silicon layer 12 on the surface, and then an emitter hole B and an emitter wiring hole C are formed by photolithography. Then, n-type silicon layers 13 and 14 are formed in the region of the emitter hole B and the emitter wiring hole C on the p-type silicon substrate 11 by phosphorus ion implantation using the silicon oxide layer 12 as a mask. (Fig. 2 (a))
[0064]
    Step (b)
  Next, a wiring material made of a metal thin film such as Cr or Al is formed on the surface of the p-type silicon substrate 11 on the thermally oxidized silicon layer 12 side by sputtering or vapor deposition, and then patterned by photolithography. An emitter wiring layer 15 is formed on the n-type silicon layer 14 in the emitter wiring hole C. (Fig. 2 (b))
[0065]
    Step (c)
  Subsequently, after sequentially forming an insulating material and a gate electrode material on the thermally oxidized silicon layer 12 and the emitter wiring layer 15, a circular hole or polygonal hole pattern having a gate opening diameter is formed by photolithography. Then, the gate electrode material and the insulating material are etched by reactive ion etching until the n-type silicon layer 13 is exposed to form the gate hole D, and the insulating layer 16 and the gate electrode 17 are formed. Here, as the film formation method of the gate electrode 17, various methods that can be used to obtain a film having a high electrical insulating property that is usually used can be used. Particularly, the gate electrode 17 has good characteristics as a gate insulating film. It is possible to use amorphous silicon nitride formed by PECVD using silane or a mixed gas composed of disilane and ammonia as a reaction gas.
[0066]
    Step (d)
  Next, the lift-off material 18 is formed only on the upper surface and side surfaces of the gate electrode 17 by oblique vapor deposition. As the material of the lift-off material 18, Al, MgO, or the like that has high peelability at the time of lift-off can be preferably used. Subsequently, a metal material for the emitter 19 is deposited on the n-type silicon layer 13 in the gate hole D by normal anisotropic deposition from the perpendicular direction. At this time, the conical emitter 19 is formed in a self-aligned manner on the n-type silicon layer 13 at the same time as the opening diameter of the gate hole is reduced as the deposition proceeds. Deposition is performed until the gate hole D is finally closed. The emitter material can be selected from a wide range of materials that can be deposited, such as metals, semiconductors, and ceramics. Further, when amorphous silicon or polysilicon by an evaporation method is used as the emitter material, more stable emission characteristics can be obtained.
[0067]
  At this time, for example, when the total thickness of the insulating layer 16 and the gate electrode 17 is 1 μm, when the diameter of the gate hole D is 1 μm or less, the emitter shape is conical and larger than 1 μm, and evaporation of the emitter material is performed. Is finished before the gate hole D is closed, it has a generally truncated cone shape. Further, when the gate hole D has a polygonal shape instead of a circular shape, it can be a polygonal pyramid or a polygonal frustum, respectively. Here, for example, it has been confirmed from the inventor's previous experiments that the frustoconical shape can obtain uniform emission characteristics over a large area rather than the conical shape. Thereby, for example, the emitter 19 having a sharp tip is formed. (Fig. 2 (d))
[0068]
    Step (e)
  Finally, the lift-off material 18 is removed by etching using a buffered hydrofluoric acid solution, and the gate electrode 17 is patterned as necessary. As a result, the cold electron-emitting device shown in FIG.
[0069]
  Further, in step (b), after forming the emitter wiring layer 15, the thermally oxidized silicon layer 12 can be removed by etching using a buffered hydrofluoric acid solution or the like. In this case, the step due to the thermally oxidized silicon film is eliminated in the subsequent process, and the processing accuracy of photolithography or the like can be further improved.
[0070]
  Further, in the step (a), as shown in FIG. 4A ″, a metal or ceramic thin film layer 12 formed by a thin film forming method such as sputtering or vapor deposition is used instead of the thermally oxidized silicon layer functioning as a mask layer for ion implantation. , And after forming the emitter wiring layer, the metal or ceramic thin film layer can be removed by etching as shown in FIG. 4B in step (b). The function of the mask layer can be further improved.
[0071]
  As described above, in the cold electron emission device of the present invention, an emission current highly controlled by a transistor is obtained by forming an emitter of metal or non-single crystal silicon on a silicon substrate having a MOSFET structure. In addition, matrix wiring can be easily realized.
[0072]
【Example】
  A manufacturing example of the cold electron emission device of the present invention will be specifically described in the following examples.
[0073]
    Step (a)
  First, thermal oxidation of a p-type silicon substrate 11 having a specific resistance of several Ω · cm was performed at 1100 ° C. for 30 minutes, thereby forming a thermally oxidized silicon layer 12 having a thickness of 0.3 μm on the surface. Next, the thermal silicon oxide layer 12 was patterned by wet etching using a buffered hydrofluoric acid solution by a photolithography method to form an emitter hole B and an emitter wiring hole C. Subsequently, phosphorus ions were implanted at 60 keV under an irradiation condition of 1015 cm −2, followed by vacuum annealing at 800 ° C. for 30 minutes for activation. (Fig. 2 (a))
[0074]
    Step (b)
  Next, a Cr film having a thickness of 0.2 μm is formed on the thermally oxidized silicon layer 12 by sputtering, followed by patterning using a normal photolithography method, and on the n-type silicon layer 14 in the emitter wiring hole C. An emitter wiring layer 15 was formed on the substrate. (Fig. 2 (b))
[0075]
    Step (c)
  Next, a SiNx film having a thickness of 0.3 μm was formed as a material for the insulating layer by PECVD. A film was formed using a mixed gas of silane and ammonia as a reaction gas and hydrogen as a diluent gas, with a total gas flow rate of 540 sccm, a gas pressure of 1 Torr, a substrate temperature of 350 ° C., and an RF power of 60 W. Subsequently, Nb was formed to a thickness of 0.2 μm as a gate electrode material by a vacuum deposition method. Further, a circular hole pattern having a gate opening diameter of 1 μm was formed using a normal photolithography method, and the gate electrode material Nb and the insulating material SiNx were etched by reactive ion etching until the n-type silicon layer 16 was exposed. The etching conditions at this time were (introduced gas: SF6 of 60 sccm / power of 100 W / gas pressure of 4.5 Pa). Thereby, the gate electrode 17 and the insulating film 16 were formed. (Fig. 2 (c))
[0076]
    Step (d)
  Next, as a lift-off material 18, Al was obliquely deposited with a thickness of 0.3 μm. Subsequently, Mo was vapor-deposited as a material for the emitter 19 until the gate hole was closed by anisotropic vapor deposition from a direction perpendicular to the substrate. (Fig. 2 (d))
[0077]
    Step (e)
  Next, Al of the lift-off material 18 was wet-etched using an acid-based etchant and peeled off together with the upper-layer emitter material to obtain a cold electron emission device as shown in FIG.
[0078]
  An array in which 100 cold electron-emitting devices described above were integrated was prototyped and tested and evaluated as follows. That is, for the device having a structure in which the distance between the emitter and gate electrodes of each device is about 0.6 μm, the height of the emitter is about 0.8 μm, and the channel length L / channel width W is 10/1 as a MOSFET parameter, When a glass plate member with a transparent electrode (anode) coated with is faced at a distance of 30 mm and an extraction voltage is applied between the emitter electrode and the gate electrode with a positive polarity on the gate electrode side, electrons are emitted well and stably. We were able to.
[0079]
  As shown in FIG. 11, the obtained emission characteristic showed the current-voltage characteristic (E) of the emitter itself in the low electric field region, and the current voltage characteristic (M) by the MOSFET in the high electric field region. That is, a transistor control region of current was obtained in a high electric field region where the emission current exceeded the drain current value of the MOSFET, and a stable emission current (ME) was obtained with a gate voltage of 70 V or more in this device.
[0080]
【The invention's effect】
  According to the present invention, by forming an emitter of metal or non-single crystal silicon on a silicon substrate having a MOSFET structure, a highly controlled emission current can be obtained by a transistor, and matrix wiring can be easily realized. can do.
[0081]
  Therefore, it is possible to obtain a cold electron-emitting device having high current stability and easy matrix formation. Furthermore, when applied to a flat panel display, a high-speed, high-definition image can be obtained with low power consumption.
[0082]
  In other words, according to the present invention, by mounting a current control function on the element itself, it is possible to suppress a local large current without increasing the operating voltage, to reduce current fluctuation to a minimum, and Field emission type cold electron emitter capable of easily forming matrix array wiringOf childWe were able to provide a manufacturing method.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a cold electron emission device of the present invention.
FIG. 2 is a manufacturing process diagram of a cold electron emission device of the present invention.
FIG. 3 is another manufacturing process diagram of the cold electron emission device of the present invention.
FIG. 4 is another manufacturing process diagram of the cold electron emission device of the present invention.
FIG. 5 is a cross-sectional view of a conventional cold electron emission device.
FIG. 6 is a manufacturing process diagram of a conventional cold electron-emitting device.
FIG. 7 is a cross-sectional view of another conventional cold electron emission device.
FIG. 8 is a cross-sectional view of a conventional cold electron emission device.
FIG. 9 is a manufacturing process diagram of another conventional cold electron emission device.
FIG. 10 is a manufacturing process diagram of another conventional cold electron-emitting device.
FIG. 11 is an example of electrical characteristics of the cold electron emission device of the present invention.
[Explanation of symbols]
  1 ... p-type silicon substrate
  2 ... Insulating layer
  3 ・ ・ ・ Gate electrode
  4 ... n-type silicon layer
  5 ... Gate electrode
  6 ... n-type silicon layer
  7 ... Emitter wiring layer
  11 ... p-type silicon substrate
  12 ... Thermally oxidized silicon layer
  12 "・ Metal or ceramic thin film layer
  13 ... n-type silicon layer
  14 ... n-type silicon layer
  15 ... Emitter wiring layer
  16 ... Insulating layer
  17 ... Gate electrode
  18 ... Lift-off material
  19 ... Emitter
  51 ... Insulating substrate
  52 ... Conductive layer
  53 ... Insulating layer
  54 ... Gate electrode
  55 ... Emitter
  61 ... Insulating substrate
  62... Conductive layer
  63 ... Insulating layer
  64 ... Gate electrode
  65 ... Lift-off material
  66 ... Emitter
  71 ... Insulating substrate
  72... Conductive layer
  73 ... Resistance layer
  74 ... Insulating layer
  75 ... Gate electrode
  76 ... Emitter
  81 ... Silicon substrate
  82 ... Silicon oxide layer
  83 ... Emitter
  84 ... Silicon oxide layer
  85 ... Insulating layer
  86 ... Gate electrode
  91... P-type silicon substrate
  92 ... Emitter
  93 ... n-type silicon layer
  94: Emitter wiring layer
  95 ... Insulating layer
  96 ... Gate electrode
  101..p-type silicon substrate
  102 .. Silicon oxide layer
  103 .. Emitter
  104 .. Silicon oxide layer
  105 .. Gate electrode
  106 .. n-type silicon layer
  107..Metal thin film
  A: Opening
  B ... Emitter hole
  C: Emitter wiring hole
  D: Gate hole
  E ... Emitter characteristics
  M ... MOSFET characteristics
  ME ・ ・ ・ Emission characteristics

Claims (4)

An insulating layer and a gate electrode are sequentially stacked on a conductive substrate, an opening reaching the conductive substrate is provided in the gate electrode and the insulating layer, and an emitter is provided on the conductive substrate in the opening. In the field emission cold electron-emitting device formed so as not to contact
  The conductive substrate is a p-type silicon substrate, and an emitter and an emitter wiring layer are arranged via n-type silicon layers respectively provided on the same plane on the p-type silicon substrate, and the emitter wiring layer A manufacturing method for manufacturing a cold electron-emitting device having an insulating layer and a gate electrode formed thereon,
  (A) A silicon oxide layer is formed on the surface of the p-type silicon substrate by thermal oxidation, and then the silicon oxide layer is patterned to form an emitter hole and an emitter wiring hole. The emitter hole and the emitter wiring Forming an n-type silicon layer in the hole by ion implantation;
  (B) forming an emitter wiring layer material by forming an emitter wiring layer material on the n-type silicon layer generated in the emitter wiring hole and patterning the emitter wiring layer material;
  (C) An insulating material layer and a gate electrode material layer are sequentially formed on the silicon oxide layer and the emitter wiring layer, and a hole pattern having an opening for forming a gate is formed by a photolithography method. And etching the gate electrode material layer and the insulating material layer by reactive ion etching until the n-type silicon layer is exposed, thereby forming the gate hole, and the gate electrode and the insulating layer;
  (D) A lift-off material is deposited only on the top and side surfaces of the gate electrode by oblique deposition, and a lift-off layer is formed. Filming and self-aligning emitter formation;
  (E) peeling off the lift-off layer and peeling off the emitter material on the gate electrode;
  A manufacturing method characterized by comprising all the steps (a) to (e). In the step (b),
  2. The method of manufacturing a cold electron emission device according to claim 1, wherein the silicon oxide layer is removed by etching after forming the emitter wiring layer. In the step (a), a metal thin film layer or a ceramic thin film layer provided by a thin film forming method was used instead of the silicon oxide layer provided by thermal oxidation, and an emitter wiring layer was formed in the step (b). Removing the metal thin film layer or the ceramic thin film layer later by etching;
  The manufacturing method of the cold electron emission element of Claim 2 characterized by these. In the step (c), the insulating layer material is amorphous silicon nitride, and the reactive gas is formed by PECVD using a mixed gas composed of either silane or disilane and ammonia,
  The method for manufacturing a cold electron-emitting device according to claim 1, wherein:

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