WO2023105899A1 - Field emission element and method for producing same - Google Patents

Field emission element and method for producing same Download PDF

Info

Publication number
WO2023105899A1
WO2023105899A1 PCT/JP2022/037103 JP2022037103W WO2023105899A1 WO 2023105899 A1 WO2023105899 A1 WO 2023105899A1 JP 2022037103 W JP2022037103 W JP 2022037103W WO 2023105899 A1 WO2023105899 A1 WO 2023105899A1
Authority
WO
WIPO (PCT)
Prior art keywords
field emission
multilayer graphene
graphene film
gate electrode
film
Prior art date
Application number
PCT/JP2022/037103
Other languages
French (fr)
Japanese (ja)
Inventor
昌善 長尾
博雅 村田
勝久 村上
Original Assignee
国立研究開発法人産業技術総合研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 国立研究開発法人産業技術総合研究所 filed Critical 国立研究開発法人産業技術総合研究所
Publication of WO2023105899A1 publication Critical patent/WO2023105899A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/304Field-emissive cathodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems

Definitions

  • the present invention relates to a field emission device that emits electrons from the tip of the emitter by applying a high voltage between the emitter and the gate electrode, and a manufacturing method thereof.
  • a field-emission electron source which integrates an emitter with a conical shape perpendicular to the substrate and an extraction gate electrode for applying an electric field to emit electrons from the emitter, is used in display devices such as flat panel displays. , traveling wave tubes (ultra-high frequency tubes), etc.
  • a Spindt-type emitter is known as a field emission device (see, for example, Non-Patent Document 1).
  • the inventor of the present application has disclosed a gate-electrode-integrated field emission device having a volcano-shaped extraction gate electrode (see Patent Document 1).
  • Field emission device arrays emit large currents when applied to traveling wave tubes and X-ray sources. When a large current is emitted, an unexpected discharge occurs between the emitter and gate electrode, and the discharge melts the emitter and gate electrode, causing a short circuit between the emitter and gate electrode, and the entire device stops functioning. A situation occurs.
  • An object of the present invention is to provide a field emission device that avoids discharge between an emitter and a gate electrode, and suppresses adverse effects on other field emission devices even if discharge occurs.
  • an emitter having a sharp tip formed on a substrate, and a gate electrode having an opening exposing the tip of the emitter formed on the substrate with an insulating layer interposed therebetween.
  • the gate electrode is composed of a polycrystalline multilayer graphene film.
  • the gate electrode having the opening exposing the tip of the emitter is made of the multilayer graphene film, even if some of the electrons emitted from the emitter are incident on the gate electrode, abnormal discharge due to gas emission will occur. Even if the electrons enter the gate electrode and reach a high temperature, they do not melt and sublimate, so that defects such as short-circuiting between the emitter and the gate electrode do not occur. It is possible to provide a field emission device that suppresses adverse effects.
  • an emitter having a pointed tip formed on a substrate, and an opening exposing the tip of the emitter formed on the substrate with an insulating layer interposed therebetween
  • a method for manufacturing a field emission device comprising a gate electrode made of a multi-layered polycrystalline graphene film, the method comprising the steps of: forming a metal film at a position to be the gate electrode, and forming an amorphous carbon film thereon; and forming a polycrystalline multilayer graphene film in which the amorphous carbon film is crystallized at the position of the metal film by a layer exchange method in which the film and the amorphous carbon film are heated in a vacuum.
  • the polycrystalline multilayer graphene film is formed as the gate electrode by using a layer exchange method between the metal film and the amorphous carbon film.
  • the metal atoms of the metal film remain between the layers of the multilayer graphene film, and the orientation plane of the graphene in a part of the multilayer graphene film fluctuates from the direction parallel to the film surface of the multilayer graphene film. detachment can be suppressed.
  • FIG. 1 is a cross-sectional view showing the configuration of a field emission device according to a first embodiment of the present invention
  • FIG. FIG. 2 is an explanatory diagram of a polycrystalline multilayer graphene film of a gate electrode
  • FIG. 4 is a process diagram (part 1) of the method for manufacturing the field emission device according to the first embodiment
  • FIG. 2 is a process diagram (part 2) of the method for manufacturing the field emission device according to the first embodiment
  • FIG. 4 is a cross-sectional view showing the configuration of a field emission device according to a second embodiment of the present invention
  • FIG. 11 is a process diagram (part 1) of the method for manufacturing the field emission device according to the second embodiment
  • FIG. 11 is a process diagram (part 2) of the method for manufacturing the field emission device according to the second embodiment;
  • FIG. 10 is a cross-sectional view showing the configuration of a field emission device according to a third embodiment of the present invention;
  • FIG. 5 is a cross-sectional view showing the configuration of a field emission device according to a fourth embodiment of the present invention;
  • FIG. 1 is a cross-sectional view showing the configuration of a field emission device according to the first embodiment of the present invention.
  • a field emission device 10 according to the present embodiment includes a substrate 11, an emitter 12 having a sharp tip 12a formed on the substrate 11, and an emitter 12 formed on the substrate 11 so as to surround the emitter 12. and a gate electrode 15 having an opening 15 a exposing the tip 12 a of the emitter 12 on the second insulating layer 14 .
  • the field emission device 10 applies a high voltage, eg, 50 to 100 V, between the gate electrode 15 and the emitter 12 to extract electrons from the tip 12a of the emitter 12 and emit them to the outside.
  • the substrate 11 is a conductive substrate.
  • the substrate 11 may be a substrate made of an insulating material, such as a glass substrate or a quartz substrate.
  • an emitter electrode layer (not shown) made of a metal material is formed on the substrate 11 .
  • the substrate 11 or emitter electrode layer is electrically connected to the emitter 12 .
  • the first insulating layer 13 is made of an insulating material, such as a silicon oxide film or an aluminum oxide film with a thickness of 500 nm.
  • An opening 13 a communicating with the opening 15 a of the gate electrode 15 is formed in the first insulating layer 13 .
  • the opening 13a is formed to be recessed from the emitter 12 more than the opening 15a.
  • the second insulating layer 14 is formed on the first insulating layer 13 and is made of an insulating material that is difficult for oxygen molecules and water molecules to permeate, such as a silicon nitride film.
  • the second insulating layer 14 has a thickness of 30 nm, for example.
  • the second insulating layer 14 prevents the oxygen molecules and water molecules released from the first insulating layer 13 from adversely affecting the formation of the multilayer graphene film of the gate electrode 15 on the second insulating layer 14 .
  • the second insulating layer 14 may be omitted because it does not adversely affect the formation of the multilayer graphene film.
  • an opening 14a communicating with the opening 13a and the opening 15a is formed.
  • the second insulating layer 14 preferably has a slight conductivity in that it can prevent discharge due to the charge-up of the field emission device 10, and preferably has an electrical resistance value of 1 G ⁇ to 10 G ⁇ .
  • the emitter 12 has a shape with a pointed tip 12a, for example, a conical or pyramidal shape.
  • the emitter 12 is, for example, conical with a height of 800 nm and a diameter of 700 nm.
  • the emitter 12 is made of metal material such as molybdenum, nickel, tungsten.
  • the gate electrode 15 is made of a polycrystalline multilayer graphene film.
  • a multilayer graphene film is formed by stacking a plurality of two-dimensional sheet-like monolayer graphenes composed of a six-membered ring network of carbon atoms.
  • the multilayer graphene film does not cause gas emission even if some of the electrons emitted from the emitter 12 are incident thereon, and can avoid abnormal discharge due to gas emission.
  • the multilayer graphene film has an extremely high heat resistance with a sublimation point of 3500° C. or higher, and extremely high thermal conductivity. A defect such as a short circuit between 12 and gate electrode 15 does not occur.
  • FIG. 2 is an explanatory diagram of a polycrystalline multilayer graphene film of a gate electrode, where (a) is a plan view and (b) is a cross-sectional view.
  • the multilayer graphene film of the gate electrode 15 is made of polycrystal in which a large number of crystal grains 15b having grain boundaries 15c are formed.
  • Each crystal grain 15b is formed by overlapping graphene 15d in multiple layers, and the orientation plane direction of each graphene 15d is substantially parallel to the film surface of the multilayer graphene film in the majority of the region 15e. This is the preferential orientation direction.
  • FIG. 1 is an explanatory diagram of a polycrystalline multilayer graphene film of a gate electrode, where (a) is a plan view and (b) is a cross-sectional view.
  • the multilayer graphene film of the gate electrode 15 is made of polycrystal in which a large number of crystal grains 15b having grain boundaries 15c are formed.
  • Each crystal grain 15b is formed by
  • the multilayer graphene film has a region 15f in which the orientation plane is inclined from the orientation plane of the surrounding region 15e forming the preferred orientation direction inside the crystal grain 15b or near the grain boundary.
  • the orientation plane fluctuates from the direction parallel to the film surface of the multilayer graphene film.
  • the region 15f in which the orientation surface fluctuates is about 1% in area ratio when the multilayer graphene film is viewed from above. In this way, the presence of the region 15f that fluctuates in the direction parallel to the film surface of the multilayer graphene film makes it difficult for the multilayer graphene film to peel off.
  • the multi-layer graphene film of the gate electrode 15 Since the orientation plane of the multilayer graphene film of the gate electrode 15 is partially swayed, the electrical resistivity in the orientation plane direction increases as the grain size of the crystal grains 15b decreases. On the other hand, the multi-layer graphene film is easy to peel when the grain size of the crystal grains 15b is large, and becomes difficult to peel when the grain size is small. Regarding the size of the crystal grains 15b, it is preferable that the average grain size is 300 nm to 3000 nm in terms of a good balance between the electrical resistivity and the difficulty of peeling. Especially preferred.
  • the average grain size is measured using a transmission electron microscope (TEM), for example, on the multilayer graphene film. The exfoliated multilayer graphene film is placed on a TEM mesh, observed from a direction perpendicular to the orientation plane, and the particle diameter of the crystal grains 15b in a certain direction is measured. Find the diameter.
  • TEM transmission electron microscope
  • the multilayer graphene film of the gate electrode 15 contains metal atoms between graphene layers.
  • a metal atom is an atom constituting a metal film used in the layer exchange method, and includes one metal selected from the group of Cr, Mn, Fe, Co, Ni, Ru, Ir, and Pt. This makes it difficult for the multilayer graphene film to peel off.
  • This metal atom is preferably Ni because it has a low melting point and facilitates formation of a multilayer graphene film by a layer exchange method, as will be described later. It is particularly preferable to include 0.1% by weight to 1% by weight of the metal atoms in the multilayer graphene film in order to suppress exfoliation of the multilayer graphene film.
  • the gate electrode 15 having the opening 15a exposing the tip 12a of the emitter 12 is made of a multilayer graphene film, some of the electrons emitted from the emitter 12 are incident on the gate electrode 15. Even if the electrons enter the gate electrode 15 and reach a high temperature, they sublimate without melting, resulting in defects such as short-circuiting between the emitter 12 and the gate electrode 15. It is possible to provide the field emission device 10 that does not occur and that suppresses adverse effects on other field emission devices.
  • a first insulating film such as a silicon oxide film or an aluminum oxide film is formed on a conductive substrate 11 by a known film forming method such as a chemical vapor deposition (CVD) method or a sputtering method.
  • CVD chemical vapor deposition
  • a metal film is formed as an emitter electrode layer on the silicon substrate by sputtering or vacuum deposition, and the first insulating layer 13A is formed thereon.
  • the silicon substrate may be made conductive by ion implantation or the like, and the first insulating layer 13A may be formed on the surface by thermal oxidation.
  • a second insulating layer 14A is formed on the first insulating layer 13A by a known film forming method such as CVD or sputtering.
  • the second insulating layer 14A is made of an insulating material that makes it difficult for oxygen molecules and water molecules from the first insulating layer 13 to permeate so as to eliminate adverse effects on the growth of the multilayer graphene film that serves as the gate electrode.
  • the second insulating layer 14A is preferably a silicon nitride film that is difficult for oxygen molecules and water molecules to permeate. It is preferable that the thickness of the second insulating layer 14A is 20 nm or more because it is difficult for oxygen molecules and water molecules to pass therethrough.
  • the first insulating layer 13A is a silicon thermal oxide film
  • experiments have shown that a multilayer graphene film can be formed on the first insulating layer 13A by the method of the process of FIG. 3B without the second insulating layer 14A. Since it has been completed, the formation of the second insulating layer 14A may be omitted.
  • a metal film 16A is formed on the second insulating layer 14A by a known film forming method such as sputtering or electron beam evaporation.
  • the thickness of the metal film 16A is set to be the same as the thickness of the multilayer graphene film 15A formed by the layer exchange method in the step of FIG. 3B.
  • the thickness of the metal film 16A may be set in consideration of electric field concentration and the like so that the finally formed field emission device 10 can easily emit electrons.
  • the thickness of the metal film 16A is preferably 50 nm to 500 nm, more preferably 100 nm to 100 nm, from the viewpoint of film quality such as crystallinity, electrical resistivity, and thermal conductivity of the multilayer graphene film of the finally formed gate electrode 15. 200 nm is particularly preferred.
  • the metal film 16A is one metal selected from the group of Cr, Mn, Fe, Co, Ni, Ru, Ir and Pt.
  • the layer exchange method and the elements of the metal film are disclosed in document Y. Nakajima et.al, ACS Appl. Mater. Interfaces 2018, 10, 41664-41669.
  • the metal film 16A is preferably a Ni film because the formation temperature of the multilayer graphene film is low.
  • an amorphous carbon film 18 is formed on the metal film 16A by a known film forming method such as CVD or sputtering.
  • the thickness of the amorphous carbon film 18 is set to be the same as the thickness of the metal film 16A.
  • the substrate 11 on which the first insulating layer 13A, the second insulating layer 14A, the metal film 16A and the amorphous carbon film 18 are laminated in the process of FIG. 3A is heat-treated in a vacuum.
  • the multilayer graphene film 15A is formed by crystallizing the amorphous carbon film 18 at the position of the metal film 16A, the metal of the metal film 16A moves to the position of the amorphous carbon film 18, and the metal film 16B is formed.
  • This process is called a layer exchange method.
  • the heating conditions are appropriately selected according to the metal material of the metal film 16A, but are generally 800° C. for about one hour. When the metal of the metal film 16A was Ni, layer exchange occurred even under the heating condition of 500° C. for 1 hour.
  • metal atoms of the metal film 16A remain between the layers of the multilayer graphene film 15A. It is particularly preferable to include 0.1% by weight to 1% by weight of the metal atoms in the multilayer graphene film in order to suppress exfoliation of the multilayer graphene film.
  • the multilayer graphene film 15A since the multilayer graphene film 15A has a region where the orientation surface fluctuates from the direction parallel to the film surface, the multilayer graphene film 15A that is difficult to peel off is formed.
  • the metal film 16B on the outermost surface is removed.
  • the removing process is performed on the metal film 16B using an acidic chemical solution. If the metal film 16B is made of Ni, a nitric acid-based chemical solution may be used, and if the metal film 16B is made of another metal, aqua regia may be used. At this time, the chemical solution does not adversely affect the multilayer graphene film 15A, and the metal film 16B can be removed.
  • a circular pattern with a diameter of about 1 ⁇ m is formed on the multilayer graphene film 15A by photolithography, and the underlying multilayer graphene film 15A, the second insulating layer 14A and the first insulating layer 13A are removed, and the substrate 11 is formed.
  • An etching process is performed to expose the surface of , and a recess 17 consisting of openings 13a to 15a is formed.
  • a reactive etching (RIE) method can be used for the etching process.
  • oxygen gas is used for the multilayer graphene film 15A
  • sulfur hexafluoride (SF 6 ) gas is used when the second insulating layer 14A is a silicon nitride (SiN) film, and the first insulating layer 13A is etched.
  • SF 6 sulfur hexafluoride
  • SiO 2 silicon oxide
  • mixed gas of tetrafluoromethane (CF 4 ) and hydrogen (H 2 ) gas, trifluoromethane (CHF 3 ) gas, or the like is used.
  • a known gas can be used for the RIE method depending on the material to be etched.
  • an etching process is performed using a buffered hydrofluoric acid (BHF) solution to remove the second insulating layer 14A, the first insulating layer 13A, and the second insulating layer 14A in the lateral direction (in-plane direction). . Since the SiN film and the SiO 2 film have different etching rates with respect to the BHF solution, as shown in FIG. structure.
  • BHF buffered hydrofluoric acid
  • a sacrificial layer material is vapor-deposited obliquely with respect to the substrate 11 to cover the surface of the multi-layer graphene film that will become the gate electrode 15 and the side wall of the opening 15a.
  • a sacrificial layer 19 is formed.
  • the angle of the oblique deposition is set so that the side walls of the opening 15a are sufficiently covered with the sacrificial layer material.
  • the material of the sacrificial layer 19 is not particularly limited as long as it can be easily removed with an acid or alkaline chemical solution, and aluminum and magnesium oxide, for example, can be used.
  • emitter material is deposited vertically on the substrate 11 by electron beam evaporation or ionized sputtering to form the conical emitter 12 on the surface of the substrate 11 within the recess 17 .
  • Emitter material 12A is deposited on the surface of sacrificial layer 19 by this vapor deposition.
  • the ionized sputtering method is performed, for example, by the method disclosed in Japanese Patent No. 6093968. In the ionized sputtering method, the choice of emitter materials is wider than in the electron beam evaporation method.
  • Carbide carbide semiconductors such as SiC and GeC (including those doped with impurities), conductive nitrides such as TiN, VN, CrN, ZrN, NbN, MoN, HfN, TaN, and WN, nitrides such as AlN and GaN semiconductors (including those doped with impurities ), Sr2RuO4 , SrRuO3 , RuO2 , IrO2 , Sr4Ru3O10 , CaRuO3 , BaRuO3 , LaNiO3 , La3Ni2O7 , ReO3 , SrFeO 3 , SrCoO 3 , SrIrO 3 , ZnO, InO 2 , InGaZnO, and other conductive oxides can also be used.
  • conductive nitrides such as TiN, VN, CrN, ZrN, NbN, MoN, HfN, TaN, and WN
  • the sacrificial layer 19 is dissolved with an acid or alkaline chemical, the emitter material 12A deposited on the sacrificial layer 19 is removed, and the surface of the gate electrode 15 is exposed.
  • an alkaline chemical solution such as sodium hydroxide can be used.
  • magnesium oxide is used as the material of the sacrificial layer 19, an acid that does not dissolve the material of the emitter 12, such as dilute acetic acid, can be used.
  • the field emission device 10 is formed by the above steps.
  • the polycrystalline multilayer graphene film 15A is formed as the gate electrode 15 by using the layer exchange method of the metal film 16A and the amorphous carbon film 18.
  • the metal atoms of the metal film 16A remain between the layers of the multilayer graphene film, and the orientation plane of each crystal grain of the multilayer graphene film fluctuates from the direction parallel to the film surface of the multilayer graphene film, so that the multilayer graphene film itself is Peeling can be suppressed.
  • FIG. 5 is a cross-sectional view showing the configuration of a field emission device according to the second embodiment of the invention.
  • the field emission device 50 according to the present embodiment includes a substrate 11, an emitter 52 formed on the substrate 11 and having a sharp tip 52a, and an emitter 52 formed on the substrate 11 so as to surround the emitter 52. and a gate electrode 55 having an opening 55 a exposing the tip 52 a of the emitter 52 on the second insulating layer 54 .
  • Each component of the field emission device 50 is made of the same material as that of the field emission device 10 of the first embodiment, and detailed description thereof will be omitted.
  • the field emission device 50 of this embodiment has a so-called volcano shape.
  • the gate electrode 55 has a peripheral portion 55b of the opening 55a that extends along the surface of the tip portion 52a of the emitter 52 while being spaced apart, and has a shape in which the diameter of the opening 55a is smaller than that of the base portion 55c of the peripheral portion 55b. .
  • the gate electrode 55 is composed of a multilayer graphene film similar to that of the field emission device 10 of the first embodiment.
  • the gate electrode 55 has a portion formed parallel to the substrate 11 (hereinafter also referred to as a parallel portion 55d) and a peripheral edge portion 55b extending obliquely upward at a base portion 55c.
  • the parallel portion 55d is parallel to the substrate 11, and the peripheral edge portion 55b is parallel to the surface of the peripheral edge portion 55b and obliquely upward.
  • the multilayer graphene film is formed by bending the orientation direction of the multilayer graphene film along the bent shape of the base portion 55c.
  • the multi-layered graphene film will extend from the peripheral portion 55b of the gate electrode 55 to the peripheral parallel portion. Since the gate electrode 55 is oriented so that current can easily flow toward 55d, the gate electrode 55 is less likely to generate Joule heat and is less likely to reach a high temperature.
  • the height of the peripheral edge portion 55b of the gate electrode 55 is equal to or higher than that of the tip portion 52a of the emitter 52, for example, about 100 nm. Also, the spread of the emitted electron beam can be suppressed to some extent.
  • the second insulating layer 54 is formed to cover the bottom surface of the gate electrode 55 . It is preferable that the second insulating layer 54 is formed so as to cover the entire surface of the peripheral portion 55b of the gate electrode 55 facing the emitter 52 in that creeping discharge is suppressed by increasing the creeping distance of the insulator. .
  • the first insulating layer 53 is formed to cover the base of the emitter 52 and expose the tip 52a. Thereby, unnecessary electron emission caused by triple junction or the like can be suppressed.
  • the same effects as those of the first embodiment are obtained, and furthermore, since it has a volcanic structure, even if discharge occurs between the gate electrode 55 and the emitter 52, the multilayer graphene film is oriented so that current can easily flow from the peripheral edge portion 55b of the gate electrode 55 to the peripheral parallel portion 55d. can.
  • FIGS. 6 and 7 are process diagrams of a method for manufacturing a field emission device according to the second embodiment. A method of manufacturing the field emission device 10 will be described with reference to FIGS.
  • a pointed emitter 52 is formed on the substrate 11 .
  • a method of etching a silicon substrate to form a sharp shape can be used. There is no particular limitation as long as the method can form a conical or pyramidal shape.
  • a first insulating layer 53A covering the surface of the substrate 11 and the emitter 52 is formed by the same method as in the first embodiment.
  • the CVD method is preferably used to cover the entire emitter 52.
  • a silicon oxide film may be formed by the plasma-enhanced CVD method using tetraethoxysilane gas.
  • a second insulating layer 54A eg, a silicon nitride film, is formed to cover the surface of the first insulating layer 53A.
  • a well-known film formation method such as a CVD method, a sputtering method, or the like can be used. It is preferred to use the method.
  • a metal film 56A is formed on the second insulating layer 54A, and an amorphous carbon film 58 is further formed.
  • the metal film 56A and the amorphous carbon film 58 are formed in the same manner as the metal film 16A and the amorphous carbon film 58 of the first embodiment, respectively.
  • the substrate 11 on which the first insulating layer 53A, the second insulating layer 54A, the metal film 56A and the amorphous carbon film 58 are laminated in the process of FIG. 6B is heat-treated in a vacuum. is performed to form a multilayer graphene film 55A in which the amorphous carbon film 58 is crystallized at the position of the metal film 56A, the metal of the metal film 56A moves to the position of the amorphous carbon film 58, and the metal film 56B is formed.
  • the process of FIG. 6(c) is performed in the same manner as the process of FIG. 3(b) of the first embodiment.
  • the multilayer graphene film 55A and the second insulating layer 54A immediately above the tip of the emitter are removed.
  • a so-called etch-back method can be used for this selective removal treatment. Specifically, a photoresist having a film thickness that covers the multilayer graphene film 55A and is flattened over the entire substrate 11 is applied. Next, the photoresist is uniformly etched with oxygen plasma, and the multilayer graphene film 55A is etched until the convex multilayer graphene film 55A directly above the tip 52a of the emitter 52 appears and the second insulating layer 54A is exposed. An opening 55a is formed. The height of the opening 55a of the gate electrode 55 is controlled by the etching time or the like.
  • the second insulating layer 54A exposed in the opening 55a of the gate electrode 55 is etched to expose the first insulating layer 53A and form the opening 54a.
  • sulfur hexafluoride (SF 6 ) gas for example, can be used as the etching gas.
  • the first insulating layer 53A exposed from the openings 54a and 55a is removed, and the tip 52a of the emitter 52 is exposed.
  • a buffered hydrofluoric acid solution can be used in this removal treatment.
  • the gate electrode 55 of the polycrystalline multilayer graphene film is formed by using the layer exchange method.
  • the gate electrode 55 has a parallel portion 55 d parallel to the substrate 11 and a peripheral edge portion 55 b extending obliquely upward following the conical shape of the emitter 52 . Since the orientation direction of graphene in the multilayer graphene film is formed along the shape of the gate electrode 55, the orientation direction is changed at the base portion 55c. Thereby, the effect of the field emission device 50 described above is exhibited.
  • FIG. 8 is a cross-sectional view showing the configuration of a field emission device according to the third embodiment of the invention.
  • the field emission device 80 according to the present embodiment includes a substrate 11, an emitter 52 formed on the substrate 11 and having a sharp tip 52a, and an emitter 52 formed on the substrate 11 so as to surround the emitter 52.
  • the field emission device 80 is a modification of the volcano-type field emission device 50 according to the second embodiment, and has a configuration in which the field emission device 50 is provided with a focusing electrode 83 .
  • the third insulating layer 81 is made of the same material as the first insulating layer 53 .
  • the fourth insulating layer 82 is made of the same material as the second insulating layer 54 and is provided to prevent creeping discharge. This is to prevent the formation of a focal point (triple junction).
  • a triple junction is a point where three things meet: a metal (a conductive substance), an insulator (a substance other than vacuum and air), and a vacuum. Originally unnecessary electron emission occurs due to field emission due to a strong electric field from the triple junction.
  • the fourth insulating layer 82 like the second insulating layer 54, is preferably slightly more conductive than a perfectly insulating material.
  • the focusing electrode 83 is made of a conductive material, for example, a metal material such as niobium, and may use a multilayer graphene film. Since a potential between the potential applied to the gate electrode 55 and the potential applied to the emitter 52 is generally applied to the focusing electrode 83, the probability that electrons emitted from the emitter 52 flow in is low. No need.
  • 6A to 6C and 7A are performed in the same manner as the field emission device 50 according to the second embodiment, and a second 3.
  • An insulating layer 81, a fourth insulating layer and a focusing electrode 83 are formed. 7(b), the opening of the focusing electrode 83 and the opening of the fourth insulating layer 82 are formed using the etch-back method, and the third insulating layer 81 is etched from these openings with a BHF solution. is removed to form an opening. Then, the process of FIG.7(c) is performed.
  • the stress is applied to the multilayer graphene film and the film is easily peeled off.
  • the orientation plane of each crystal grain of the multilayer graphene film 55A fluctuates from the direction parallel to the film surface of the multilayer graphene film, and the metal atoms of the metal film 56A remain between the layers of the multilayer graphene film 55A.
  • exfoliation of the multilayer graphene film can be suppressed.
  • FIG. 9 is a cross-sectional view showing the structure of a field emission device according to the fourth embodiment of the invention.
  • the field emission device 90 according to the present embodiment is similar to the field emission device according to the third embodiment except that a fifth insulating layer 91 is provided between the gate electrode 55 and the third insulating layer 81. It has the same configuration as 80.
  • the fifth insulating layer 91 is an adhesion layer for enhancing adhesion between the multilayer graphene film of the gate electrode 55 and the third insulating layer 81 .
  • the fifth insulating layer 91 is preferably made of a material that does not contain oxygen, such as silicon nitride.
  • the fifth insulating layer 91 is formed, for example, by a reactive sputtering method using nitrogen gas and using pure silicon as a target.
  • Reference Signs List 10 50, 80, 90 field emission device 11 substrate 12, 52 emitter 13, 53 first insulating layer 14, 54 second insulating layer 15, 55 gate electrode 15A, 55A multilayer graphene film 16A, 16B, 56A, 56B metal Films 18, 58 Amorphous carbon film 83 Focusing electrode 91 Fifth insulating layer

Abstract

The present disclosure provides a field emission element 10 which is provided with: an emitter 12 that is formed on a substrate 11 and has an acute tip 12a; and a gate electrode 15 that is formed on the substrate, with insulating layers 13, 14 being interposed therebetween, and has an opening 15a from which the tip of the emitter is exposed. With respect to this field emission element 10, the gate electrode is formed of a polycrystalline multilayer graphene film. A method for producing a field emission element is also disclosed.

Description

電界放出素子およびその製造方法Field emission device and manufacturing method thereof
 本発明は、エミッタとゲート電極との間に高電圧を印加してエミッタの先端部から電子を放出する電界放出素子およびその製造方法に関する。 The present invention relates to a field emission device that emits electrons from the tip of the emitter by applying a high voltage between the emitter and the gate electrode, and a manufacturing method thereof.
 基板に垂直な円錐形状を持つエミッタと、エミッタから電子を放出させるための電界を印加するための、引き出しゲート電極が一体化された電界放出型の電子源は、フラットパネルディスプレイなどの表示装置や、進行波管(超高周波管)などの応用が期待されている。 A field-emission electron source, which integrates an emitter with a conical shape perpendicular to the substrate and an extraction gate electrode for applying an electric field to emit electrons from the emitter, is used in display devices such as flat panel displays. , traveling wave tubes (ultra-high frequency tubes), etc.
 電界放出素子としてスピント型エミッタが知られている(例えば、非特許文献1参照)。本願発明者は、火山型の引き出しゲート電極を有するゲート電極一体型の電界放出素子を開示している(特許文献1参照)。 A Spindt-type emitter is known as a field emission device (see, for example, Non-Patent Document 1). The inventor of the present application has disclosed a gate-electrode-integrated field emission device having a volcano-shaped extraction gate electrode (see Patent Document 1).
 電界放出素子アレイは、進行波管やエックス線源に応用する場合には、大電流を放出する。大電流を放出した際にエミッタとゲート電極の間で予期せぬ放電が起こり、その放電のためにエミッタやゲート電極が溶融し、エミッタとゲート電極間が短絡して、素子全体が機能しなくなるという事態が発生する。 Field emission device arrays emit large currents when applied to traveling wave tubes and X-ray sources. When a large current is emitted, an unexpected discharge occurs between the emitter and gate electrode, and the discharge melts the emitter and gate electrode, causing a short circuit between the emitter and gate electrode, and the entire device stops functioning. A situation occurs.
 電界放出素子は、予期せぬ放電として、エミッタから放出された電子の一部がゲート電極に入射し、それによりゲート電極から局所的にガスが放出され、そのガス放出が発端となって起こることも考えられる。エミッタとゲート電極との間で放電が起った場合、電界放出素子アレイの小ブロック内で給電のためのヒューズとしての電極が溶断する構造が提案されている(例えば、特許文献2、3参照)。 In the field emission device, some of the electrons emitted from the emitter enter the gate electrode as an unexpected discharge, and as a result, gas is locally emitted from the gate electrode, and the gas emission is triggered. is also conceivable. A structure has been proposed in which, when a discharge occurs between an emitter and a gate electrode, an electrode as a fuse for power supply within a small block of a field emission device array is fused (see, for example, Patent Documents 2 and 3). ).
特許第6635510号公報Japanese Patent No. 6635510 特開平4-284324号公報JP-A-4-284324 特開平5-144370号公報JP-A-5-144370
 本願発明者の検討により、特許文献2および3の構造の電界放出素子アレイでは、小ブロック内のエミッタとゲート電極との間で放電が起きた際に溶断した電極が飛び散り、周辺の小ブロックの電界放出素子アレイにおいても短絡が生じるという好ましくない事態が生じることが分かった。 According to studies by the inventors of the present application, in field emission device arrays having the structures of Patent Documents 2 and 3, when discharge occurs between the emitter and the gate electrode in a small block, the fused electrode scatters, causing damage to the surrounding small blocks. It has been found that the field emission device array also causes an undesirable situation in which a short circuit occurs.
 本発明は、エミッタとゲート電極との間で放電を回避するとともに、仮に放電が起きた場合でも他の電界放出素子に悪影響を及ぼすことを抑制した電界放出素子を提供することを目的とする。 An object of the present invention is to provide a field emission device that avoids discharge between an emitter and a gate electrode, and suppresses adverse effects on other field emission devices even if discharge occurs.
 本発明の一態様によれば、基板上に形成された先端部が尖ったエミッタと、上記基板上に絶縁層を介して形成された上記エミッタの先端部を露出する開口部を有するゲート電極と、を備え、上記ゲート電極は、多結晶の多層グラフェン膜からなる、電界放出素子が提供される。 According to one aspect of the present invention, an emitter having a sharp tip formed on a substrate, and a gate electrode having an opening exposing the tip of the emitter formed on the substrate with an insulating layer interposed therebetween. , wherein the gate electrode is composed of a polycrystalline multilayer graphene film.
 上記態様によれば、エミッタの先端部を露出する開口部を有するゲート電極が多層グラフェン膜からなるので、エミッタから放出された電子の一部がゲート電極に入射してもガス放出による異常放電を回避でき、仮に電子がゲート電極に入射して高温になったとしても溶融することなく昇華して、エミッタとゲート電極との間を短絡するような欠陥が生じず、さらに他の電界放出素子に悪影響を及ぼすことを抑制した電界放出素子を提供することができる。 According to the above aspect, since the gate electrode having the opening exposing the tip of the emitter is made of the multilayer graphene film, even if some of the electrons emitted from the emitter are incident on the gate electrode, abnormal discharge due to gas emission will occur. Even if the electrons enter the gate electrode and reach a high temperature, they do not melt and sublimate, so that defects such as short-circuiting between the emitter and the gate electrode do not occur. It is possible to provide a field emission device that suppresses adverse effects.
 本発明の他の態様によれば、基板上に形成された先端部が尖ったエミッタと、上記基板上に絶縁層を介して形成された上記エミッタの先端部を露出する開口部を有し、多結晶の多層グラフェン膜からなるゲート電極と、を備える電界放出素子の製造方法であって、上記ゲート電極となる位置に金属膜と、その上にアモルファスカーボン膜とを形成するステップと、上記金属膜と上記アモルファスカーボン膜とを真空中で加熱する層交換法により上記金属膜の位置に上記アモルファスカーボン膜が結晶化した多結晶の多層グラフェン膜を形成するステップと、を含む、上記製造方法が提供される。 According to another aspect of the present invention, an emitter having a pointed tip formed on a substrate, and an opening exposing the tip of the emitter formed on the substrate with an insulating layer interposed therebetween, A method for manufacturing a field emission device comprising a gate electrode made of a multi-layered polycrystalline graphene film, the method comprising the steps of: forming a metal film at a position to be the gate electrode, and forming an amorphous carbon film thereon; and forming a polycrystalline multilayer graphene film in which the amorphous carbon film is crystallized at the position of the metal film by a layer exchange method in which the film and the amorphous carbon film are heated in a vacuum. provided.
 上記他の態様によれば、ゲート電極として、金属膜とアモルファスカーボン膜との層交換法を用いることで多結晶の多層グラフェン膜を形成する。多層グラフェン膜の層間に金属膜の金属原子が残留するとともに、多層グラフェン膜の一部の領域でグラフェンの配向面が多層グラフェン膜の膜面に平行な方向から揺らいでいることで多層グラフェン膜自体の剥離を抑制できる。 According to the other aspect, the polycrystalline multilayer graphene film is formed as the gate electrode by using a layer exchange method between the metal film and the amorphous carbon film. The metal atoms of the metal film remain between the layers of the multilayer graphene film, and the orientation plane of the graphene in a part of the multilayer graphene film fluctuates from the direction parallel to the film surface of the multilayer graphene film. detachment can be suppressed.
本発明の第1実施形態に係る電界放出素子の構成を示す断面図である。1 is a cross-sectional view showing the configuration of a field emission device according to a first embodiment of the present invention; FIG. ゲート電極の多結晶の多層グラフェン膜の説明図である。FIG. 2 is an explanatory diagram of a polycrystalline multilayer graphene film of a gate electrode; 第1実施形態に係る電界放出素子の製造方法の工程図(その1)である。FIG. 4 is a process diagram (part 1) of the method for manufacturing the field emission device according to the first embodiment; 第1実施形態に係る電界放出素子の製造方法の工程図(その2)である。FIG. 2 is a process diagram (part 2) of the method for manufacturing the field emission device according to the first embodiment; 本発明の第2実施形態に係る電界放出素子の構成を示す断面図である。FIG. 4 is a cross-sectional view showing the configuration of a field emission device according to a second embodiment of the present invention; 第2実施形態に係る電界放出素子の製造方法の工程図(その1)である。FIG. 11 is a process diagram (part 1) of the method for manufacturing the field emission device according to the second embodiment; 第2実施形態に係る電界放出素子の製造方法の工程図(その2)である。FIG. 11 is a process diagram (part 2) of the method for manufacturing the field emission device according to the second embodiment; 本発明の第3実施形態に係る電界放出素子の構成を示す断面図である。FIG. 10 is a cross-sectional view showing the configuration of a field emission device according to a third embodiment of the present invention; 本発明の第4実施形態に係る電界放出素子の構成を示す断面図である。FIG. 5 is a cross-sectional view showing the configuration of a field emission device according to a fourth embodiment of the present invention;
 以下、図面に基づいて本発明の実施形態を説明する。なお、複数の図面間において共通する要素については同じ符号を付し、その要素の詳細な説明の繰り返しを省略する。 Hereinafter, embodiments of the present invention will be described based on the drawings. Elements that are common among a plurality of drawings are denoted by the same reference numerals, and repeated detailed description of the elements is omitted.
[第1実施形態]
 図1は、本発明の第1実施形態に係る電界放出素子の構成を示す断面図である。図1を参照するに、本実施形態に係る電界放出素子10は、基板11と、基板11上に形成された先端部12aが尖ったエミッタ12と、基板11上にエミッタ12を囲むように形成された第1絶縁層13および第2絶縁層14と、第2絶縁層14上にエミッタ12の先端部12aを露出する開口部15aを有するゲート電極15とを備える。電界放出素子10は、ゲート電極15とエミッタ12との間に高電圧、例えば50~100Vを印加することでエミッタ12の先端部12aから電子を引き出して外部に放出する。
[First embodiment]
FIG. 1 is a cross-sectional view showing the configuration of a field emission device according to the first embodiment of the present invention. Referring to FIG. 1, a field emission device 10 according to the present embodiment includes a substrate 11, an emitter 12 having a sharp tip 12a formed on the substrate 11, and an emitter 12 formed on the substrate 11 so as to surround the emitter 12. and a gate electrode 15 having an opening 15 a exposing the tip 12 a of the emitter 12 on the second insulating layer 14 . The field emission device 10 applies a high voltage, eg, 50 to 100 V, between the gate electrode 15 and the emitter 12 to extract electrons from the tip 12a of the emitter 12 and emit them to the outside.
 基板11は、導電性の基板である。基板11は、絶縁性材料からなる基板、例えばガラス基板や石英基板を用いてもよく、この場合は基板11上に金属材料からなるエミッタ電極層(不図示)を形成する。基板11またはエミッタ電極層はエミッタ12に電気的に接続される。 The substrate 11 is a conductive substrate. The substrate 11 may be a substrate made of an insulating material, such as a glass substrate or a quartz substrate. In this case, an emitter electrode layer (not shown) made of a metal material is formed on the substrate 11 . The substrate 11 or emitter electrode layer is electrically connected to the emitter 12 .
 第1絶縁層13は、絶縁材料からなり、例えば厚さ500nmのシリコン酸化膜、酸化アルミニウム膜である。第1絶縁層13には、ゲート電極15の開口部15aと連通する開口部13aが形成される。開口部13aは、開口部15aよりもエミッタ12から後退して形成される。 The first insulating layer 13 is made of an insulating material, such as a silicon oxide film or an aluminum oxide film with a thickness of 500 nm. An opening 13 a communicating with the opening 15 a of the gate electrode 15 is formed in the first insulating layer 13 . The opening 13a is formed to be recessed from the emitter 12 more than the opening 15a.
 第2絶縁層14は、第1絶縁層13上に形成され、酸素分子および水分子を透過し難い絶縁材料からなり、例えばシリコン窒化膜である。第2絶縁層14は、例えば厚さ30nmである。第2絶縁層14は、第1絶縁層13から放出される酸素分子および水分子が、第2絶縁層14上のゲート電極15の多層グラフェン膜の形成に悪影響を及ぼすことを抑制する。また、第2絶縁層14は、沿面放電を抑制する点で設けることが好ましい。なお、第1絶縁層13がシリコンの熱酸化膜の場合は、多層グラフェン膜の形成に悪影響が及ばない点で、第2絶縁層14を省略してもよい。第2絶縁層14には、開口部13aおよび開口部15aに連通する開口部14aが形成される。 The second insulating layer 14 is formed on the first insulating layer 13 and is made of an insulating material that is difficult for oxygen molecules and water molecules to permeate, such as a silicon nitride film. The second insulating layer 14 has a thickness of 30 nm, for example. The second insulating layer 14 prevents the oxygen molecules and water molecules released from the first insulating layer 13 from adversely affecting the formation of the multilayer graphene film of the gate electrode 15 on the second insulating layer 14 . Moreover, it is preferable to provide the second insulating layer 14 in terms of suppressing creeping discharge. When the first insulating layer 13 is a silicon thermally oxidized film, the second insulating layer 14 may be omitted because it does not adversely affect the formation of the multilayer graphene film. In the second insulating layer 14, an opening 14a communicating with the opening 13a and the opening 15a is formed.
 第2絶縁層14は、電界放出素子10のチャージアップの影響で放電が生じるのを防止できる点で、わずかに導電性がある方が好ましく、電気抵抗値が1GΩ~10GΩであることが好ましい。 The second insulating layer 14 preferably has a slight conductivity in that it can prevent discharge due to the charge-up of the field emission device 10, and preferably has an electrical resistance value of 1 GΩ to 10 GΩ.
 エミッタ12は、先端部12aが尖った形状、例えば円錐状または角錐状の形状を有する。エミッタ12は、例えば、高さ800nm、直径700nmの円錐状である。エミッタ12は、モリブデン、ニッケル、タングステン等の金属材料からなる。 The emitter 12 has a shape with a pointed tip 12a, for example, a conical or pyramidal shape. The emitter 12 is, for example, conical with a height of 800 nm and a diameter of 700 nm. The emitter 12 is made of metal material such as molybdenum, nickel, tungsten.
 ゲート電極15は、多結晶の多層グラフェン膜からなる。多層グラフェン膜は炭素原子の六員環ネットワークからなる二次元シート状の単層グラフェンが複数重なって形成されている。多層グラフェン膜は、エミッタ12から放出された電子の一部が入射してもガス放出が発生せず、ガス放出による異常放電を回避できる。多層グラフェン膜は、昇華点が3500℃以上と耐熱性が極めて高く、熱伝導率も極めて高いため、電子が入射して3500℃を超える高温になったとしても溶融することなく昇華して、エミッタ12とゲート電極15との間を短絡するような欠陥は生じない。 The gate electrode 15 is made of a polycrystalline multilayer graphene film. A multilayer graphene film is formed by stacking a plurality of two-dimensional sheet-like monolayer graphenes composed of a six-membered ring network of carbon atoms. The multilayer graphene film does not cause gas emission even if some of the electrons emitted from the emitter 12 are incident thereon, and can avoid abnormal discharge due to gas emission. The multilayer graphene film has an extremely high heat resistance with a sublimation point of 3500° C. or higher, and extremely high thermal conductivity. A defect such as a short circuit between 12 and gate electrode 15 does not occur.
 図2は、ゲート電極の多結晶の多層グラフェン膜の説明図であり、(a)は平面図、(b)は断面図である。図2(a)および(b)を図1と合わせて参照するに、ゲート電極15の多層グラフェン膜は、結晶粒界15cを有する結晶粒15bが多数形成された多結晶からなる。各々の結晶粒15bは、グラフェン15dが多層に重なって形成されており、各々のグラフェン15dは、大部分の領域15eで配向面方向が多層グラフェン膜の膜面にほぼ平行になっており、これが優先配向方向である。図2(b)に示すように、多層グラフェン膜は、結晶粒15bの内部あるいは結晶粒界付近で、配向面が優先配向方向を形成する周囲の領域15eの配向面から傾いている領域15fが一部存在する。すなわち、ゲート電極15の多層グラフェン膜の一部の領域15fで配向面が多層グラフェン膜の膜面に平行な方向から揺らいでいる。配向面が揺らいでいる領域15fは、多層グラフェン膜を平面視した場合、面積比で約1%程度である。このように、多層グラフェン膜の膜面に平行な方向から揺らいでいる領域15fが存在することで、多層グラフェン膜の剥離が生じ難くなっている。 FIG. 2 is an explanatory diagram of a polycrystalline multilayer graphene film of a gate electrode, where (a) is a plan view and (b) is a cross-sectional view. Referring to FIGS. 2A and 2B together with FIG. 1, the multilayer graphene film of the gate electrode 15 is made of polycrystal in which a large number of crystal grains 15b having grain boundaries 15c are formed. Each crystal grain 15b is formed by overlapping graphene 15d in multiple layers, and the orientation plane direction of each graphene 15d is substantially parallel to the film surface of the multilayer graphene film in the majority of the region 15e. This is the preferential orientation direction. As shown in FIG. 2B, the multilayer graphene film has a region 15f in which the orientation plane is inclined from the orientation plane of the surrounding region 15e forming the preferred orientation direction inside the crystal grain 15b or near the grain boundary. Some exist. That is, in the partial region 15f of the multilayer graphene film of the gate electrode 15, the orientation plane fluctuates from the direction parallel to the film surface of the multilayer graphene film. The region 15f in which the orientation surface fluctuates is about 1% in area ratio when the multilayer graphene film is viewed from above. In this way, the presence of the region 15f that fluctuates in the direction parallel to the film surface of the multilayer graphene film makes it difficult for the multilayer graphene film to peel off.
 ゲート電極15の多層グラフェン膜は一部で配向面が揺らいでいるため、結晶粒15bの粒径が小さくなると配向面方向の電気抵抗率が増加する。一方、多層グラフェン膜はは、結晶粒15bの粒径が大きいと剥離し易く、小さいと剥離し難くなる。結晶粒15bの大きさは、平均粒径が300nm~3000nmであることが、電気抵抗率と剥離のし難さとの兼ね合いが良好な点で好ましく、平均粒径が700nm~1500nmであることが、特に好ましい。平均粒径の測定は、多層グラフェン膜を例えば透過型電子顕微鏡(TEM)を用いて行う。TEMのメッシュに剥離した多層グラフェン膜をのせ、配向面に対して垂直方向から観察し、結晶粒15bの一定方向の粒子径を計測して、約20個の粒子径を算術平均して平均粒径を求める。 Since the orientation plane of the multilayer graphene film of the gate electrode 15 is partially swayed, the electrical resistivity in the orientation plane direction increases as the grain size of the crystal grains 15b decreases. On the other hand, the multi-layer graphene film is easy to peel when the grain size of the crystal grains 15b is large, and becomes difficult to peel when the grain size is small. Regarding the size of the crystal grains 15b, it is preferable that the average grain size is 300 nm to 3000 nm in terms of a good balance between the electrical resistivity and the difficulty of peeling. Especially preferred. The average grain size is measured using a transmission electron microscope (TEM), for example, on the multilayer graphene film. The exfoliated multilayer graphene film is placed on a TEM mesh, observed from a direction perpendicular to the orientation plane, and the particle diameter of the crystal grains 15b in a certain direction is measured. Find the diameter.
 ゲート電極15の多層グラフェン膜は、グラフェンの層間に金属原子を含む。金属原子は、層交換法に用いる金属膜を構成する原子であり、Cr,Mn,Fe,Co,Ni,Ru,Ir,Ptの群から選択される一つの金属を含む。これにより、多層グラフェン膜の剥離が生じ難くなっている。この金属原子は、Niであることが後述するように融点が低く層交換法により多層グラフェン膜が形成し易い点で好ましい。金属原子は、特に多層グラフェン膜の0.1重量%~1重量%含むことが、多層グラフェン膜の剥離を抑制できる点で特に好ましい。 The multilayer graphene film of the gate electrode 15 contains metal atoms between graphene layers. A metal atom is an atom constituting a metal film used in the layer exchange method, and includes one metal selected from the group of Cr, Mn, Fe, Co, Ni, Ru, Ir, and Pt. This makes it difficult for the multilayer graphene film to peel off. This metal atom is preferably Ni because it has a low melting point and facilitates formation of a multilayer graphene film by a layer exchange method, as will be described later. It is particularly preferable to include 0.1% by weight to 1% by weight of the metal atoms in the multilayer graphene film in order to suppress exfoliation of the multilayer graphene film.
 本実施形態によれば、エミッタ12の先端部12aを露出する開口部15aを有するゲート電極15が多層グラフェン膜からなるので、エミッタ12から放出された電子の一部がゲート電極15に入射してもガス放出による異常放電を回避でき、仮に電子がゲート電極15に入射して高温になったとしても溶融することなく昇華して、エミッタ12とゲート電極15との間を短絡するような欠陥が生じず、さらに他の電界放出素子に悪影響を及ぼすことを抑制した電界放出素子10を提供できる。 According to the present embodiment, since the gate electrode 15 having the opening 15a exposing the tip 12a of the emitter 12 is made of a multilayer graphene film, some of the electrons emitted from the emitter 12 are incident on the gate electrode 15. Even if the electrons enter the gate electrode 15 and reach a high temperature, they sublimate without melting, resulting in defects such as short-circuiting between the emitter 12 and the gate electrode 15. It is possible to provide the field emission device 10 that does not occur and that suppresses adverse effects on other field emission devices.
[第1実施形態に係る電界放出素子の製造方法]
 図3および図4は、第1実施形態に係る電界放出素子の製造方法の工程図である。図3(a)~(d)および図4(a)~(b)を図1と合わせて参照しつつ、電界放出素子10の製造方法を説明する。
[Manufacturing Method of Field Emission Device According to First Embodiment]
3 and 4 are process diagrams of the method for manufacturing the field emission device according to the first embodiment. A method of manufacturing the field emission device 10 will be described with reference to FIGS. 3(a) to (d) and FIGS.
 図3(a)の工程では、導電性の基板11の上に、化学気相成長(CVD)法、スパッタ法等の公知の成膜手法により、シリコン酸化膜、酸化アルミニウム膜等の第1絶縁層13Aを形成する。基板11に絶縁性材料からなる基板、例えばシリコン基板を用いる場合は、シリコン基板上に金属膜をスパッタ法、真空蒸着法によりエミッタ電極層として形成し、その上に第1絶縁層13Aを形成する。また、シリコン基板にイオン注入等により導電性を付与し、熱酸化により表面に第1絶縁層13Aを形成してもよい。 In the process of FIG. 3A, a first insulating film such as a silicon oxide film or an aluminum oxide film is formed on a conductive substrate 11 by a known film forming method such as a chemical vapor deposition (CVD) method or a sputtering method. Form layer 13A. When a substrate made of an insulating material, such as a silicon substrate, is used as the substrate 11, a metal film is formed as an emitter electrode layer on the silicon substrate by sputtering or vacuum deposition, and the first insulating layer 13A is formed thereon. . Alternatively, the silicon substrate may be made conductive by ion implantation or the like, and the first insulating layer 13A may be formed on the surface by thermal oxidation.
 次いで、第1絶縁層13A上に、CVD法、スパッタ法等の公知の成膜手法により第2絶縁層14Aを形成する。第2絶縁層14Aは、ゲート電極となる多層グラフェン膜の成長への悪影響を排除できるように、第1絶縁層13からの酸素分子および水分子を透過し難い絶縁材料からなる。第2絶縁層14Aは、酸素分子および水分子を透過し難いでシリコン窒化膜であることが好ましい。第2絶縁層14Aは、厚さが20nm以上であることが、酸素分子および水分子を透過し難くできる点で好ましい。なお、第1絶縁層13Aがシリコンの熱酸化膜の場合は、実験により第2絶縁層14Aがなくとも、図3(b)の工程の手法で第1絶縁層13A上に多層グラフェン膜が形成できたので、第2絶縁層14Aの形成を省略してもよい。 Next, a second insulating layer 14A is formed on the first insulating layer 13A by a known film forming method such as CVD or sputtering. The second insulating layer 14A is made of an insulating material that makes it difficult for oxygen molecules and water molecules from the first insulating layer 13 to permeate so as to eliminate adverse effects on the growth of the multilayer graphene film that serves as the gate electrode. The second insulating layer 14A is preferably a silicon nitride film that is difficult for oxygen molecules and water molecules to permeate. It is preferable that the thickness of the second insulating layer 14A is 20 nm or more because it is difficult for oxygen molecules and water molecules to pass therethrough. When the first insulating layer 13A is a silicon thermal oxide film, experiments have shown that a multilayer graphene film can be formed on the first insulating layer 13A by the method of the process of FIG. 3B without the second insulating layer 14A. Since it has been completed, the formation of the second insulating layer 14A may be omitted.
 次いで、第2絶縁層14A上に、スパッタ法、電子ビーム蒸着法等の公知の成膜方法により金属膜16Aを形成する。金属膜16Aの厚さは、図3(b)の工程で層交換法により形成される多層グラフェン膜15Aの厚さと同じに厚さに設定する。金属膜16Aの厚さは、最終的に形成される電界放出素子10が電子放出し易くなるように電界集中等を考慮して設定すればよい。金属膜16Aの厚さは、最終的に形成されるゲート電極15の多層グラフェン膜の結晶性、電気抵抗率、熱伝導率等の膜質の点から、50nm~500nmであることが好ましく、100nm~200nmであることが特に好ましい。 Next, a metal film 16A is formed on the second insulating layer 14A by a known film forming method such as sputtering or electron beam evaporation. The thickness of the metal film 16A is set to be the same as the thickness of the multilayer graphene film 15A formed by the layer exchange method in the step of FIG. 3B. The thickness of the metal film 16A may be set in consideration of electric field concentration and the like so that the finally formed field emission device 10 can easily emit electrons. The thickness of the metal film 16A is preferably 50 nm to 500 nm, more preferably 100 nm to 100 nm, from the viewpoint of film quality such as crystallinity, electrical resistivity, and thermal conductivity of the multilayer graphene film of the finally formed gate electrode 15. 200 nm is particularly preferred.
 金属膜16Aは、Cr,Mn,Fe,Co,Ni,Ru,Ir,Ptの群から選択される一つの金属である。層交換法および金属膜の元素については、文献 Y. Nakajima et.al, ACS Appl. Mater. Interfaces 2018, 10, 41664-41669に開示されている。金属膜16Aは、多層グラフェン膜の形成温度が低い点で、Ni膜であることが好ましい。 The metal film 16A is one metal selected from the group of Cr, Mn, Fe, Co, Ni, Ru, Ir and Pt. The layer exchange method and the elements of the metal film are disclosed in document Y. Nakajima et.al, ACS Appl. Mater. Interfaces 2018, 10, 41664-41669. The metal film 16A is preferably a Ni film because the formation temperature of the multilayer graphene film is low.
 次いで、金属膜16A上に、CVD法、スパッタ法等の公知の成膜手法により、アモルファスカーボン膜18を形成する。アモルファスカーボン膜18の厚さは、金属膜16Aの厚さと同じに厚さに設定する。 Next, an amorphous carbon film 18 is formed on the metal film 16A by a known film forming method such as CVD or sputtering. The thickness of the amorphous carbon film 18 is set to be the same as the thickness of the metal film 16A.
 なお、金属膜16Aとアモルファスカーボン膜18との間に厚さ2nm程度の酸化アルミニウム膜(不図示)を形成することで、最終的に形成される多層グラフェン膜の膜質を向上することができる(H. Murata et al., Scientific reports, (2019) 9, 4068参照)。 By forming an aluminum oxide film (not shown) having a thickness of about 2 nm between the metal film 16A and the amorphous carbon film 18, the film quality of the finally formed multilayer graphene film can be improved ( H. Murata et al., Scientific reports, (2019) 9, 4068).
 次いで、図3(b)の工程では、図3(a)の工程で第1絶縁層13A、第2絶縁層14A、金属膜16Aおよびアモルファスカーボン膜18を積層した基板11を真空中で加熱処理を行って、金属膜16Aの位置にアモルファスカーボン膜18が結晶化した多層グラフェン膜15Aが形成され、アモルファスカーボン膜18の位置に金属膜16Aの金属が移動し、金属膜16Bが形成される。この処理は、層交換法と呼ばれている。加熱条件は、金属膜16Aの金属材料に応じて適宜選択されるが、概ね800℃で1時間程度である。金属膜16Aの金属がNiの場合は、加熱条件は500℃1時間でも層交換が発現した。 Next, in the process of FIG. 3B, the substrate 11 on which the first insulating layer 13A, the second insulating layer 14A, the metal film 16A and the amorphous carbon film 18 are laminated in the process of FIG. 3A is heat-treated in a vacuum. , the multilayer graphene film 15A is formed by crystallizing the amorphous carbon film 18 at the position of the metal film 16A, the metal of the metal film 16A moves to the position of the amorphous carbon film 18, and the metal film 16B is formed. This process is called a layer exchange method. The heating conditions are appropriately selected according to the metal material of the metal film 16A, but are generally 800° C. for about one hour. When the metal of the metal film 16A was Ni, layer exchange occurred even under the heating condition of 500° C. for 1 hour.
 この工程において、多層グラフェン膜15Aの層間に金属膜16Aの金属原子が残留する。金属原子は、特に多層グラフェン膜の0.1重量%~1重量%含むことが、多層グラフェン膜の剥離を抑制できる点で特に好ましい。また、多層グラフェン膜15Aは、その配向面が膜面に平行な方向から揺らいでいる領域が存在することで、剥離し難い多層グラフェン膜15Aが形成される。 In this step, metal atoms of the metal film 16A remain between the layers of the multilayer graphene film 15A. It is particularly preferable to include 0.1% by weight to 1% by weight of the metal atoms in the multilayer graphene film in order to suppress exfoliation of the multilayer graphene film. In addition, since the multilayer graphene film 15A has a region where the orientation surface fluctuates from the direction parallel to the film surface, the multilayer graphene film 15A that is difficult to peel off is formed.
 次いで、図3(c)の工程では、最表面の金属膜16Bの除去処理を行う。除去処理は、金属膜16Bを酸性の薬液を用いて行う。金属膜16BがNiの場合は硝酸系の薬液、金属膜16Bが他の金属の場合は王水を用いればよい。この際、薬液は多層グラフェン膜15Aに悪影響を及ぼすことはなく、金属膜16Bを除去可能である。 Next, in the process of FIG. 3(c), the metal film 16B on the outermost surface is removed. The removing process is performed on the metal film 16B using an acidic chemical solution. If the metal film 16B is made of Ni, a nitric acid-based chemical solution may be used, and if the metal film 16B is made of another metal, aqua regia may be used. At this time, the chemical solution does not adversely affect the multilayer graphene film 15A, and the metal film 16B can be removed.
 次いで、多層グラフェン膜15A上にフォトリソグラフィ法により、直径1μm程度の円形のパターンを形成して、その下の多層グラフェン膜15A、第2絶縁層14Aおよび第1絶縁層13Aを除去して基板11の表面を露出するエッチング処理を行い、開口部13a~15aからなる凹部17を形成する。エッチング処理には、リアクティブエッチング(RIE)法を用いることができる。RIE法によるエッチングでは、多層グラフェン膜15Aには酸素ガスを用い、第2絶縁層14Aがシリコン窒化(SiN)膜の場合は六フッ化硫黄(SF6)ガスを用い、第1絶縁層13Aがシリコン酸化(SiO2)膜の場合は四フッ化メタン(CF4)と水素(H2)ガスとの混合ガス、トリフルオロメタン(CHF3)ガス等を用いる。RIE法に用いるガスはエッチングする材料に応じて公知のガスを用いることができる。 Next, a circular pattern with a diameter of about 1 μm is formed on the multilayer graphene film 15A by photolithography, and the underlying multilayer graphene film 15A, the second insulating layer 14A and the first insulating layer 13A are removed, and the substrate 11 is formed. An etching process is performed to expose the surface of , and a recess 17 consisting of openings 13a to 15a is formed. A reactive etching (RIE) method can be used for the etching process. In the etching by the RIE method, oxygen gas is used for the multilayer graphene film 15A, sulfur hexafluoride (SF 6 ) gas is used when the second insulating layer 14A is a silicon nitride (SiN) film, and the first insulating layer 13A is etched. In the case of a silicon oxide (SiO 2 ) film, mixed gas of tetrafluoromethane (CF 4 ) and hydrogen (H 2 ) gas, trifluoromethane (CHF 3 ) gas, or the like is used. A known gas can be used for the RIE method depending on the material to be etched.
 次いで、緩衝フッ酸(バッファードフッ酸、BHF)液を用いて第2絶縁層14Aおよび第1絶縁層13Aおよび第2絶縁層14Aを横方向(膜面内方向)に除去するエッチング処理を行う。SiN膜とSiO2膜では、BHF液に対するエッチングレートが異なるので、図3(c)に示すように、第1絶縁層13Aが第2絶縁層14Aよりも開口部13a,14aの中心から後退した構造となる。 Next, an etching process is performed using a buffered hydrofluoric acid (BHF) solution to remove the second insulating layer 14A, the first insulating layer 13A, and the second insulating layer 14A in the lateral direction (in-plane direction). . Since the SiN film and the SiO 2 film have different etching rates with respect to the BHF solution, as shown in FIG. structure.
 次いで、図3(d)の工程では、基板11を回転しながら基板11に対して斜め方向から犠牲層材料を蒸着してゲート電極15となる多層グラフェン膜の表面および開口部15aの側壁を覆う犠牲層19を形成する。斜め蒸着の角度は、開口部15aの側壁が犠牲層材料によって十分に覆われるように設定する。犠牲層19の材料は、酸やアルカリの薬液で容易に除去可能でれば特に限定されず、例えばアルミニウム、酸化マグネシウムを用いることができる。 Next, in the step of FIG. 3D, while rotating the substrate 11, a sacrificial layer material is vapor-deposited obliquely with respect to the substrate 11 to cover the surface of the multi-layer graphene film that will become the gate electrode 15 and the side wall of the opening 15a. A sacrificial layer 19 is formed. The angle of the oblique deposition is set so that the side walls of the opening 15a are sufficiently covered with the sacrificial layer material. The material of the sacrificial layer 19 is not particularly limited as long as it can be easily removed with an acid or alkaline chemical solution, and aluminum and magnesium oxide, for example, can be used.
 次いで、図4(a)の工程では、基板11に対して垂直方向からエミッタ材料を電子ビーム蒸着法またはイオン化スパッタリング法により、凹部17内の基板11の表面に円錐状のエミッタ12を形成する。この蒸着により犠牲層19の表面にエミッタ材料12Aが堆積する。イオン化スパッタリング法は、例えば特許文献第6093968号明細書に開示された方法により行う。イオン化スパッタリング法では、電子ビーム蒸着法よりもエミッタ材料の選択の幅が拡がり、例えばLaB6のような硼化物、TiC,ZrC,HfC,NbC,TaC,Mo2C,WC等の導電性を有する炭化物、SiCやGeC等の炭化物半導体(不純物ドープしたものも含む)、TiN,VN,CrN,ZrN,NbN,MoN,HfN,TaN,WN等の導電性を有する窒化物、AlN,GaN等の窒化物半導体(不純物ドープしたものも含む)、Sr2RuO4,SrRuO3,RuO2,IrO2,Sr4Ru310,CaRuO3,BaRuO3,LaNiO3,La3Ni27,ReO3,SrFeO3,SrCoO3,SrIrO3,ZnO,InO2,InGaZnO等の導電性を有する酸化物も用いることができる。 Next, in the process of FIG. 4A, emitter material is deposited vertically on the substrate 11 by electron beam evaporation or ionized sputtering to form the conical emitter 12 on the surface of the substrate 11 within the recess 17 . Emitter material 12A is deposited on the surface of sacrificial layer 19 by this vapor deposition. The ionized sputtering method is performed, for example, by the method disclosed in Japanese Patent No. 6093968. In the ionized sputtering method, the choice of emitter materials is wider than in the electron beam evaporation method. Carbide, carbide semiconductors such as SiC and GeC (including those doped with impurities), conductive nitrides such as TiN, VN, CrN, ZrN, NbN, MoN, HfN, TaN, and WN, nitrides such as AlN and GaN semiconductors ( including those doped with impurities ), Sr2RuO4 , SrRuO3 , RuO2 , IrO2 , Sr4Ru3O10 , CaRuO3 , BaRuO3 , LaNiO3 , La3Ni2O7 , ReO3 , SrFeO 3 , SrCoO 3 , SrIrO 3 , ZnO, InO 2 , InGaZnO, and other conductive oxides can also be used.
 この工程では、エミッタ材料の堆積により犠牲層18を介してゲート電極15の多層グラフェン膜に応力がかかり剥離し易くなる。しかし、本実施形態の多層グラフェン膜15Aは、先の図3(b)の工程において層間に金属原子が残留するとともに、多層グラフェン膜15Aの各々の結晶粒の配向面が多層グラフェン膜の膜面に平行な方向から揺らいでいることで多層グラフェン膜自体の剥離を抑制できる。 In this step, stress is applied to the multi-layer graphene film of the gate electrode 15 via the sacrificial layer 18 due to the deposition of the emitter material, making it easier to peel off. However, in the multilayer graphene film 15A of the present embodiment, metal atoms remain between the layers in the previous step of FIG. Delamination of the multilayer graphene film itself can be suppressed by swaying from the direction parallel to .
 次いで、図4(b)の工程では、酸またはアルカリの薬液により犠牲層19を溶解し、犠牲層19上に堆積したエミッタ材料12Aを剥離してゲート電極15の表面を露出する。犠牲層19の材料にアルミニウムを用いた場合は、水酸化ナトリウム等のアルカリ系の薬液を用いることができる。これによりエミッタ12およびゲート電極15を溶解することなくアルミニウムのみを除去できる。犠牲層19の材料に酸化マグネシウムを用いた場合は、エミッタ12の材料を溶解しない酸、例えば希酢酸等を用いることができる。上の工程により、電界放出素子10が形成される。 Next, in the step of FIG. 4B, the sacrificial layer 19 is dissolved with an acid or alkaline chemical, the emitter material 12A deposited on the sacrificial layer 19 is removed, and the surface of the gate electrode 15 is exposed. When aluminum is used as the material of the sacrificial layer 19, an alkaline chemical solution such as sodium hydroxide can be used. As a result, only aluminum can be removed without dissolving the emitter 12 and the gate electrode 15 . When magnesium oxide is used as the material of the sacrificial layer 19, an acid that does not dissolve the material of the emitter 12, such as dilute acetic acid, can be used. The field emission device 10 is formed by the above steps.
 本実施形態の製造方法によれば、ゲート電極15として、金属膜16Aとアモルファスカーボン膜18との層交換法を用いて多結晶の多層グラフェン膜15Aを形成する。多層グラフェン膜の層間に金属膜16Aの金属原子が残留するとともに、多層グラフェン膜の各々の結晶粒の配向面が多層グラフェン膜の膜面に平行な方向から揺らいでいることで多層グラフェン膜自体の剥離を抑制できる。 According to the manufacturing method of the present embodiment, the polycrystalline multilayer graphene film 15A is formed as the gate electrode 15 by using the layer exchange method of the metal film 16A and the amorphous carbon film 18. The metal atoms of the metal film 16A remain between the layers of the multilayer graphene film, and the orientation plane of each crystal grain of the multilayer graphene film fluctuates from the direction parallel to the film surface of the multilayer graphene film, so that the multilayer graphene film itself is Peeling can be suppressed.
[第2実施形態]
 図5は、本発明の第2実施形態に係る電界放出素子の構成を示す断面図である。図5を参照するに、本実施形態に係る電界放出素子50は、基板11と、基板11上に形成された先端部52aが尖ったエミッタ52と、基板11上にエミッタ52を囲むように形成された第1絶縁層53および第2絶縁層54と、第2絶縁層54上にエミッタ52の先端部52aを露出する開口部55aを有するゲート電極55とを備える。電界放出素子50の各構成要素は、第1実施形態の電界放出素子10と同様の材料から形成され、その詳細な説明を省略する。本実施形態の電界放出素子50は、いわゆる火山型の形状をなしている。ゲート電極55は、開口55a部の周縁部分55bが、エミッタ52の先端部52aの表面に沿うともに離隔して延在し、開口部55aが周縁部分55bの基部55cよりも縮径した形状を有する。
[Second embodiment]
FIG. 5 is a cross-sectional view showing the configuration of a field emission device according to the second embodiment of the invention. Referring to FIG. 5, the field emission device 50 according to the present embodiment includes a substrate 11, an emitter 52 formed on the substrate 11 and having a sharp tip 52a, and an emitter 52 formed on the substrate 11 so as to surround the emitter 52. and a gate electrode 55 having an opening 55 a exposing the tip 52 a of the emitter 52 on the second insulating layer 54 . Each component of the field emission device 50 is made of the same material as that of the field emission device 10 of the first embodiment, and detailed description thereof will be omitted. The field emission device 50 of this embodiment has a so-called volcano shape. The gate electrode 55 has a peripheral portion 55b of the opening 55a that extends along the surface of the tip portion 52a of the emitter 52 while being spaced apart, and has a shape in which the diameter of the opening 55a is smaller than that of the base portion 55c of the peripheral portion 55b. .
 ゲート電極55は、第1実施形態の電界放出素子10と同様の多層グラフェン膜からなる。ゲート電極55は、基板11と平行に形成された部分(以下、平行部分55dとも称する。)と基部55cにおいて斜め上方に屈曲して延在する周縁部分55bを有する。ゲート電極55の多層グラフェン膜の配向方向は、平行部分55dが基板11に平行であり、周縁部分55bが周縁部分55bの表面に平行に斜め上方になる。多層グラフェン膜は、基部55cにおいて屈曲する形状に沿って多層グラフェン膜の配向方向も屈曲して形成される。ゲート電極55の開口部55a付近で、万が一、ゲート電極55とエミッタ52との間で放電が起き、過電流が流れたとしても、多層グラフェン膜がゲート電極55の周縁部分55bから周辺の平行部分55dに向かって電流が流れ易いように配向しているので、ゲート電極55は、ジュール熱も発生し難く高温になり難く、さらに、発生した熱を周辺に逃がし易い構造を有する。 The gate electrode 55 is composed of a multilayer graphene film similar to that of the field emission device 10 of the first embodiment. The gate electrode 55 has a portion formed parallel to the substrate 11 (hereinafter also referred to as a parallel portion 55d) and a peripheral edge portion 55b extending obliquely upward at a base portion 55c. As for the orientation direction of the multilayer graphene film of the gate electrode 55, the parallel portion 55d is parallel to the substrate 11, and the peripheral edge portion 55b is parallel to the surface of the peripheral edge portion 55b and obliquely upward. The multilayer graphene film is formed by bending the orientation direction of the multilayer graphene film along the bent shape of the base portion 55c. In the vicinity of the opening 55a of the gate electrode 55, even if a discharge occurs between the gate electrode 55 and the emitter 52 and an overcurrent flows, the multi-layered graphene film will extend from the peripheral portion 55b of the gate electrode 55 to the peripheral parallel portion. Since the gate electrode 55 is oriented so that current can easily flow toward 55d, the gate electrode 55 is less likely to generate Joule heat and is less likely to reach a high temperature.
 ゲート電極55の周縁部分55bの高さは、エミッタ52の先端部52aと同じか、それよりも高く、例えば100nm程度高くなるように形成するのが、電子放出の際の電界集中がし易い点および放出された電子ビームの拡がりをある程度抑制できる点で好ましい。 The height of the peripheral edge portion 55b of the gate electrode 55 is equal to or higher than that of the tip portion 52a of the emitter 52, for example, about 100 nm. Also, the spread of the emitted electron beam can be suppressed to some extent.
 第2絶縁層54は、ゲート電極55の下面を覆うように形成される。第2絶縁層54は、ゲート電極55の周縁部分55bのエミッタ52と対向する面を全て覆うように形成されることが、絶縁物の沿面距離を長くすることで沿面放電を抑制する点で好ましい。 The second insulating layer 54 is formed to cover the bottom surface of the gate electrode 55 . It is preferable that the second insulating layer 54 is formed so as to cover the entire surface of the peripheral portion 55b of the gate electrode 55 facing the emitter 52 in that creeping discharge is suppressed by increasing the creeping distance of the insulator. .
 第1絶縁層53は、エミッタ52の基部を覆い、先端部52aを露出するように形成される。これにより、トリプルジャンクションなどに起因する不必要な電子放出を抑制することができる。 The first insulating layer 53 is formed to cover the base of the emitter 52 and expose the tip 52a. Thereby, unnecessary electron emission caused by triple junction or the like can be suppressed.
 本実施形態によれば、第1実施形態と同様の効果を有し、さらに、火山型の構造を有するので、万が一、ゲート電極55とエミッタ52との間で放電が起きたとしても多層グラフェン膜がゲート電極55の周縁部分55bから周辺の平行部分55dに向かって電流が流れ易いように配向しているので、ジュール熱が発生し難く高温になり難く、電界放出素子50の放電によるダメージを抑制できる。 According to the present embodiment, the same effects as those of the first embodiment are obtained, and furthermore, since it has a volcanic structure, even if discharge occurs between the gate electrode 55 and the emitter 52, the multilayer graphene film is oriented so that current can easily flow from the peripheral edge portion 55b of the gate electrode 55 to the peripheral parallel portion 55d. can.
[第2実施形態に係る電界放出素子の製造方法]
 図6および図7は、第2実施形態に係る電界放出素子の製造方法の工程図である。図6(a)~(d)および図7(a)~(b)を図5と合わせて参照しつつ、電界放出素子10の製造方法を説明する。
[Manufacturing Method of Field Emission Device According to Second Embodiment]
6 and 7 are process diagrams of a method for manufacturing a field emission device according to the second embodiment. A method of manufacturing the field emission device 10 will be described with reference to FIGS.
 図6(a)の工程では、基板11の上に、先の尖ったエミッタ52を形成する。具体的には、シリコン基板をエッチングして尖った形状を形成する方法を用いることができる。円錐状や角錐状の形状が形成できる方法であれば特に限定されない。 In the process of FIG. 6( a ), a pointed emitter 52 is formed on the substrate 11 . Specifically, a method of etching a silicon substrate to form a sharp shape can be used. There is no particular limitation as long as the method can form a conical or pyramidal shape.
 次いで、図6(b)の工程では、基板11の表面およびエミッタ52を覆う第1絶縁層53Aを第1実施形態と同様の手法により形成する。第1絶縁層53Aは、エミッタ52の全体を覆うためにCVD法を用いることが好ましく、例えば、テトラエトキシシランガスを用いたプラズマ援用CVD法によりシリコン酸化膜を成膜してもよい。 Next, in the process of FIG. 6(b), a first insulating layer 53A covering the surface of the substrate 11 and the emitter 52 is formed by the same method as in the first embodiment. For the first insulating layer 53A, the CVD method is preferably used to cover the entire emitter 52. For example, a silicon oxide film may be formed by the plasma-enhanced CVD method using tetraethoxysilane gas.
 次いで、第1絶縁層53Aの表面を覆う第2絶縁層54A、例えばシリコン窒化膜を形成する。CVD法、スパッタ法等の公知の成膜手法を用いることができるが、第1絶縁層53Aがエミッタ52の錐状の形状を引き継いでいるので、被覆性の高い成膜方法、例えば反応性スパッタ法を用いることが好ましい。 Next, a second insulating layer 54A, eg, a silicon nitride film, is formed to cover the surface of the first insulating layer 53A. A well-known film formation method such as a CVD method, a sputtering method, or the like can be used. It is preferred to use the method.
 次いで、第2絶縁層54Aの上に金属膜56Aを形成し、さらにアモルファスカーボン膜58を形成する。金属膜56Aおよびアモルファスカーボン膜58は、それぞれ、第1実施形態の金属膜16A、アモルファスカーボン膜58と同様に形成する。 Next, a metal film 56A is formed on the second insulating layer 54A, and an amorphous carbon film 58 is further formed. The metal film 56A and the amorphous carbon film 58 are formed in the same manner as the metal film 16A and the amorphous carbon film 58 of the first embodiment, respectively.
 次いで、図6(c)の工程では、図6(b)の工程で第1絶縁層53A、第2絶縁層54A、金属膜56Aおよびアモルファスカーボン膜58を積層した基板11を真空中で加熱処理を行って、金属膜56Aの位置にアモルファスカーボン膜58が結晶化した多層グラフェン膜55Aが形成され、アモルファスカーボン膜58の位置に金属膜56Aの金属が移動し、金属膜56Bが形成される。図6(c)の工程は、第1実施形態の図3(b)の工程と同様に行う。 Next, in the process of FIG. 6C, the substrate 11 on which the first insulating layer 53A, the second insulating layer 54A, the metal film 56A and the amorphous carbon film 58 are laminated in the process of FIG. 6B is heat-treated in a vacuum. is performed to form a multilayer graphene film 55A in which the amorphous carbon film 58 is crystallized at the position of the metal film 56A, the metal of the metal film 56A moves to the position of the amorphous carbon film 58, and the metal film 56B is formed. The process of FIG. 6(c) is performed in the same manner as the process of FIG. 3(b) of the first embodiment.
 次いで、図7(a)の工程では、最表面の金属膜56Bの除去処理を第1実施形態の図3(c)の工程と同様に行う。 Next, in the process of FIG. 7(a), the removal of the outermost metal film 56B is performed in the same manner as in the process of FIG. 3(c) of the first embodiment.
 次いで、図7(b)の工程では、エミッタの先端部の直上にある多層グラフェン膜55Aおよび第2絶縁層54Aの除去処理を行う。この選択的な除去処理は、いわゆるエッチバック法を用いることができる。具体的には、多層グラフェン膜55Aを覆って基板11全体に亘って平らになる膜厚のフォトレジストを塗布する。次いで、酸素プラズマによりフォトレジストを均一にエッチングし、さらにエミッタ52の先端部52aの直上の凸状の多層グラフェン膜55Aが現れ、第2絶縁層54Aが露出するまで多層グラフェン膜55Aをエッチングして開口部55aを形成する。ゲート電極55の開口部55aの高さはエッチング時間等により制御を行う。 Next, in the step of FIG. 7(b), the multilayer graphene film 55A and the second insulating layer 54A immediately above the tip of the emitter are removed. A so-called etch-back method can be used for this selective removal treatment. Specifically, a photoresist having a film thickness that covers the multilayer graphene film 55A and is flattened over the entire substrate 11 is applied. Next, the photoresist is uniformly etched with oxygen plasma, and the multilayer graphene film 55A is etched until the convex multilayer graphene film 55A directly above the tip 52a of the emitter 52 appears and the second insulating layer 54A is exposed. An opening 55a is formed. The height of the opening 55a of the gate electrode 55 is controlled by the etching time or the like.
 次いで、ゲート電極55の開口部55aに露出する第2絶縁層54Aをエッチングして第1絶縁層53Aを露出させ、開口部54aを形成する。第2絶縁層54Aがシリコン窒化膜の場合は、エッチングガスとして、例えば六フッ化硫黄(SF6)ガスを用いることができる。 Next, the second insulating layer 54A exposed in the opening 55a of the gate electrode 55 is etched to expose the first insulating layer 53A and form the opening 54a. When the second insulating layer 54A is a silicon nitride film, sulfur hexafluoride (SF 6 ) gas, for example, can be used as the etching gas.
 次いで、図7(c)の工程では、開口部54a,55aから露出する第1絶縁層53Aの除去処理を行い、エミッタ52の先端部52aを露出させる。この除去処理では、緩衝フッ酸液を用いることができる。以上の工程により、電界放出素子50が形成される。 Next, in the step of FIG. 7(c), the first insulating layer 53A exposed from the openings 54a and 55a is removed, and the tip 52a of the emitter 52 is exposed. A buffered hydrofluoric acid solution can be used in this removal treatment. Through the above steps, the field emission device 50 is formed.
 本実施形態の製造方法によれば、層交換法を用いることで多結晶の多層グラフェン膜のゲート電極55を形成する。ゲート電極55は、基板11に平行な平行部分55dに加え、エミッタ52の錐状の形状を引き継いだ斜め上方に延びる周縁部分55bが形成される。多層グラフェン膜のグラフェンの配向方向はゲート電極55の形状に沿って形成されるので、基部55cにおいて配向方向が変化するように形成される。これにより、上述した電界放出素子50の効果が奏される。 According to the manufacturing method of this embodiment, the gate electrode 55 of the polycrystalline multilayer graphene film is formed by using the layer exchange method. The gate electrode 55 has a parallel portion 55 d parallel to the substrate 11 and a peripheral edge portion 55 b extending obliquely upward following the conical shape of the emitter 52 . Since the orientation direction of graphene in the multilayer graphene film is formed along the shape of the gate electrode 55, the orientation direction is changed at the base portion 55c. Thereby, the effect of the field emission device 50 described above is exhibited.
[第3実施形態]
 図8は、本発明の第3実施形態に係る電界放出素子の構成を示す断面図である。図8を参照するに、本実施形態に係る電界放出素子80は、基板11と、基板11上に形成された先端部52aが尖ったエミッタ52と、基板11上にエミッタ52を囲むように形成された第1絶縁層53および第2絶縁層54と、第2絶縁層54上にエミッタ52の先端部52aを露出する開口部55aを有するゲート電極55と、ゲート電極55上にエミッタ52およびゲート電極55の開口部55aを囲むように形成された第3絶縁層81および第4絶縁層82と、第4絶縁層82上にエミッタ52およびゲート電極55を露出する開口部83aを有する集束電極83とを備える。電界放出素子80は、第2実施形態に係る火山型の電界放出素子50の変形例であり、電界放出素子50に集束電極83を設けた構成を有する。
[Third embodiment]
FIG. 8 is a cross-sectional view showing the configuration of a field emission device according to the third embodiment of the invention. Referring to FIG. 8, the field emission device 80 according to the present embodiment includes a substrate 11, an emitter 52 formed on the substrate 11 and having a sharp tip 52a, and an emitter 52 formed on the substrate 11 so as to surround the emitter 52. a gate electrode 55 having an opening 55a exposing the tip 52a of the emitter 52 on the second insulating layer 54; the emitter 52 and the gate electrode 55 on the gate electrode 55; A third insulating layer 81 and a fourth insulating layer 82 formed to surround an opening 55a of the electrode 55, and a focusing electrode 83 having an opening 83a on the fourth insulating layer 82 to expose the emitter 52 and the gate electrode 55. and The field emission device 80 is a modification of the volcano-type field emission device 50 according to the second embodiment, and has a configuration in which the field emission device 50 is provided with a focusing electrode 83 .
 第3絶縁層81は、第1絶縁層53と同様の材料からなる。第4絶縁層82は、第2絶縁層54と同様の材料からなり、沿面放電を防止するために設けられるものであり、第3絶縁層81と集束電極83と真空との境界において、いわゆる三重点(トリプルジャンクション)が形成されないようにするためである。トリプルジャンクションは、金属(導電性物質)と絶縁体(真空および空気以外の物質)と真空との3つが接する点である。トリプルジャンクションから強電界による電界放出により本来不要な電子放出が起こる。第4絶縁層82は、第2絶縁層54と同様、完全な絶縁性を有する材料よりもわずかに導電性があることが好ましい。 The third insulating layer 81 is made of the same material as the first insulating layer 53 . The fourth insulating layer 82 is made of the same material as the second insulating layer 54 and is provided to prevent creeping discharge. This is to prevent the formation of a focal point (triple junction). A triple junction is a point where three things meet: a metal (a conductive substance), an insulator (a substance other than vacuum and air), and a vacuum. Originally unnecessary electron emission occurs due to field emission due to a strong electric field from the triple junction. The fourth insulating layer 82, like the second insulating layer 54, is preferably slightly more conductive than a perfectly insulating material.
 集束電極83は、導電性材料、例えば、ニオブなどの金属材料からなり、多層グラフェン膜を用いてもよい。集束電極83には、一般にゲート電極55に印加する電位とエミッタ52に印加する電位との間の電位を印加するので、エミッタ52から放出された電子が流入する確率は低いので、多層グラフェン膜でなくともよい。 The focusing electrode 83 is made of a conductive material, for example, a metal material such as niobium, and may use a multilayer graphene film. Since a potential between the potential applied to the gate electrode 55 and the potential applied to the emitter 52 is generally applied to the focusing electrode 83, the probability that electrons emitted from the emitter 52 flow in is low. No need.
[第3実施形態に係る電界放出素子の製造方法]
 電界放出素子80の製造方法は、第2実施形態に係る電界放出素子50と同様に図6(a)~(c)および図7(a)の工程を行い、さらに多層グラフェン膜55A上に第3絶縁層81、第4絶縁層および集束電極83を形成する。次いで、図7(b)と同様にエッチバック法を用いて、集束電極83の開口部および第4絶縁層82の開口部を形成し、さらにそれらの開口部からBHF液により第3絶縁層81を除去して開口部を形成する。次いで、図7(c)の工程を行う。多層グラフェン膜55A上に第3絶縁層81、第4絶縁層および集束電極83を形成する際に応力が多層グラフェン膜に応力がかかり剥離し易くなる。しかし、多層グラフェン膜55Aの各々の結晶粒の配向面が多層グラフェン膜の膜面に平行な方向から揺らいでいること、並びに、多層グラフェン膜55Aの層間に金属膜56Aの金属原子が残留していることで、第1および第2実施形態と同様に多層グラフェン膜の剥離を抑制できる。
[Manufacturing Method of Field Emission Device According to Third Embodiment]
6A to 6C and 7A are performed in the same manner as the field emission device 50 according to the second embodiment, and a second 3. An insulating layer 81, a fourth insulating layer and a focusing electrode 83 are formed. 7(b), the opening of the focusing electrode 83 and the opening of the fourth insulating layer 82 are formed using the etch-back method, and the third insulating layer 81 is etched from these openings with a BHF solution. is removed to form an opening. Then, the process of FIG.7(c) is performed. When the third insulating layer 81, the fourth insulating layer, and the focusing electrode 83 are formed on the multilayer graphene film 55A, the stress is applied to the multilayer graphene film and the film is easily peeled off. However, the orientation plane of each crystal grain of the multilayer graphene film 55A fluctuates from the direction parallel to the film surface of the multilayer graphene film, and the metal atoms of the metal film 56A remain between the layers of the multilayer graphene film 55A. As in the first and second embodiments, exfoliation of the multilayer graphene film can be suppressed.
[第4実施形態]
 図9は、本発明の第4実施形態に係る電界放出素子の構成を示す断面図である。図9を参照するに、本実施形態に係る電界放出素子90は、ゲート電極55と第3絶縁層81との間に第5絶縁層91を備える以外は、第3実施形態に係る電界放出素子80と同様の構成を有する。
[Fourth embodiment]
FIG. 9 is a cross-sectional view showing the structure of a field emission device according to the fourth embodiment of the invention. Referring to FIG. 9, the field emission device 90 according to the present embodiment is similar to the field emission device according to the third embodiment except that a fifth insulating layer 91 is provided between the gate electrode 55 and the third insulating layer 81. It has the same configuration as 80.
 第5絶縁層91は、ゲート電極55の多層グラフェン膜と第3絶縁層81との密着性を高めるための密着層である。第5絶縁層91は、窒化シリコンなどの酸素を含まない材料からなることが好ましい。第5絶縁層91は、例えば窒素ガスを用い純シリコンをターゲットとした反応性スパッタリング法により形成する。 The fifth insulating layer 91 is an adhesion layer for enhancing adhesion between the multilayer graphene film of the gate electrode 55 and the third insulating layer 81 . The fifth insulating layer 91 is preferably made of a material that does not contain oxygen, such as silicon nitride. The fifth insulating layer 91 is formed, for example, by a reactive sputtering method using nitrogen gas and using pure silicon as a target.
 以上、本発明の好ましい実施形態について詳述したが、本発明は係る特定の実施形態に限定されるものではなく、請求の範囲に記載された本発明の範囲内において、種々の変形・変更が可能である。 Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims. It is possible.
 10,50,80,90  電界放出素子
 11  基板
 12,52,  エミッタ
 13,53  第1絶縁層
 14,54  第2絶縁層
 15,55  ゲート電極
 15A,55A  多層グラフェン膜
 16A,16B,56A,56B  金属膜
 18,58  アモルファスカーボン膜
 83  集束電極
 91  第5絶縁層
Reference Signs List 10, 50, 80, 90 field emission device 11 substrate 12, 52 emitter 13, 53 first insulating layer 14, 54 second insulating layer 15, 55 gate electrode 15A, 55A multilayer graphene film 16A, 16B, 56A, 56B metal Films 18, 58 Amorphous carbon film 83 Focusing electrode 91 Fifth insulating layer

Claims (15)

  1.  基板上に形成された先端部が尖ったエミッタと、
     前記基板上に絶縁層を介して形成された前記エミッタの先端部を露出する開口部を有するゲート電極と、を備え、
     前記ゲート電極は、多結晶の多層グラフェン膜からなる、電界放出素子。
    a pointed emitter formed on a substrate;
    a gate electrode having an opening exposing a tip of the emitter formed on the substrate through an insulating layer;
    The field emission device, wherein the gate electrode is composed of a polycrystalline multilayer graphene film.
  2.  前記多層グラフェン膜は、複数の結晶粒を含み、
     前記結晶粒の一部の領域で多層グラフェン膜の配向方向が優先配向方向からずれて形成されてなる、請求項1記載の電界放出素子。
    The multilayer graphene film includes a plurality of crystal grains,
    2. The field emission device according to claim 1, wherein the orientation direction of the multilayer graphene film is deviated from the preferential orientation direction in a partial region of the crystal grains.
  3.  前記結晶粒は、前記多層グラフェン膜を平面視した場合の平均粒径が300nm~3000nmである、請求項2記載の電界放出素子。 The field emission device according to claim 2, wherein the crystal grains have an average grain size of 300 nm to 3000 nm when the multilayer graphene film is viewed from above.
  4.  前記多層グラフェン膜は、金属原子を0.1重量%~1重量%含む、請求項2または3記載の電界放出素子。 The field emission device according to claim 2, wherein the multilayer graphene film contains 0.1% to 1% by weight of metal atoms.
  5.  前記多層グラフェン膜は、金属原子を0.1重量%~1重量%含む、請求項1記載の電界放出素子。 The field emission device according to claim 1, wherein the multilayer graphene film contains 0.1% by weight to 1% by weight of metal atoms.
  6.  前記ゲート電極は、前記開口部の周縁部分が、前記エミッタの先端部の表面に沿うとともに離隔して延在し、該開口部が該周縁部分の基部よりも縮径した形状を有する、請求項1記載の電界放出素子。 3. The gate electrode has a peripheral portion of the opening extending along the surface of the tip portion of the emitter while being spaced apart, and the opening having a shape with a smaller diameter than the base of the peripheral portion. 1. The field emission device according to 1.
  7.  前記多層グラフェン膜は、複数の結晶粒を含み、
     前記結晶粒の一部の領域で多層グラフェン膜の配向方向が優先配向方向からずれて形成されてなる、請求項6記載の電界放出素子。
    The multilayer graphene film includes a plurality of crystal grains,
    7. The field emission device according to claim 6, wherein the orientation direction of the multilayer graphene film is deviated from the preferential orientation direction in some regions of the crystal grains.
  8.  前記多層グラフェン膜は、前記ゲート電極の形状に対応して結晶粒の配向方向が形成されてなる、請求項6または7記載の電界放出素子。 8. The field emission device according to claim 6, wherein said multilayer graphene film is formed so that the orientation direction of crystal grains corresponds to the shape of said gate electrode.
  9.  前記ゲート電極の開口部よりも外側に該ゲート電極上に他の絶縁層と、該他の絶縁層上に前記エミッタの先端部および該ゲート電極の先端部分を露出する他の開口部を有する集束電極をさらに備える、請求項6記載の電界放出素子。 Convergence having another insulating layer on the gate electrode outside the opening of the gate electrode and another opening exposing the tip of the emitter and the tip of the gate electrode on the other insulating layer. 7. The field emission device of Claim 6, further comprising an electrode.
  10.  前記多層グラフェン膜は、複数の結晶粒を含み、
     前記結晶粒の一部の領域で多層グラフェン膜の配向方向が優先配向方向からずれて形成されてなる、請求項9記載の電界放出素子。
    The multilayer graphene film includes a plurality of crystal grains,
    10. The field emission device according to claim 9, wherein the orientation direction of the multilayer graphene film is deviated from the preferential orientation direction in some regions of the crystal grains.
  11.  前記ゲート電極と前記他の絶縁層との間に密着層をさらに備える、請求項10記載の電界放出素子。 11. The field emission device according to claim 10, further comprising an adhesion layer between said gate electrode and said other insulating layer.
  12.  前記ゲート電極と前記他の絶縁層との間に密着層をさらに備える、請求項9記載の電界放出素子。 The field emission device according to claim 9, further comprising an adhesion layer between said gate electrode and said other insulating layer.
  13.  基板上に形成された先端部が尖ったエミッタと、前記基板上に絶縁層を介して形成された前記エミッタの先端部を露出する開口部を有し、多結晶の多層グラフェン膜からなるゲート電極と、を備える電界放出素子の製造方法であって、
     前記ゲート電極となる位置に金属膜と、その上にアモルファスカーボン膜とを形成するステップと、
     前記金属膜と前記アモルファスカーボン膜とを真空中で加熱する層交換法により前記金属膜の位置に前記アモルファスカーボン膜が結晶化した多結晶の多層グラフェン膜を形成するステップと、を含む、前記製造方法。
    A gate electrode made of a multi-layered polycrystalline graphene film, having an emitter formed on a substrate with a pointed tip, and an opening exposing the tip of the emitter formed on the substrate with an insulating layer interposed therebetween. and a method for manufacturing a field emission device,
    forming a metal film at a position to be the gate electrode and an amorphous carbon film thereon;
    and forming a polycrystalline multilayer graphene film in which the amorphous carbon film is crystallized at the position of the metal film by a layer exchange method in which the metal film and the amorphous carbon film are heated in a vacuum. Method.
  14.  前記多層グラフェン膜および前記絶縁層に前記基板を露出する凹部を形成するステップと、
     前記凹部内の前記基板上に前記エミッタを形成するステップと、をさらに含む、請求項13記載の製造方法。
    forming a recess exposing the substrate in the multilayer graphene film and the insulating layer;
    14. The method of claim 13, further comprising forming said emitter on said substrate within said recess.
  15.  前記金属膜を形成する前に、前記基板上に前記エミッタを形成するステップと、
     前記多層グラフェン膜を形成した後に、該多層グラフェン膜に前記開口部を形成して前記エミッタの先端部を露出するステップと、をさらに含む、請求項13記載の製造方法。
    forming the emitter on the substrate before forming the metal film;
    14. The manufacturing method according to claim 13, further comprising, after forming the multilayer graphene film, forming the opening in the multilayer graphene film to expose the tip of the emitter.
PCT/JP2022/037103 2021-12-07 2022-10-04 Field emission element and method for producing same WO2023105899A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-198393 2021-12-07
JP2021198393A JP2023084299A (en) 2021-12-07 2021-12-07 Field emission element and method for manufacturing the same

Publications (1)

Publication Number Publication Date
WO2023105899A1 true WO2023105899A1 (en) 2023-06-15

Family

ID=86730141

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/037103 WO2023105899A1 (en) 2021-12-07 2022-10-04 Field emission element and method for producing same

Country Status (2)

Country Link
JP (1) JP2023084299A (en)
WO (1) WO2023105899A1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010055907A (en) * 2008-08-28 2010-03-11 National Institute Of Advanced Industrial Science & Technology Field emission element of focusing electrode integral type and its preparation method
US20150060757A1 (en) * 2013-09-02 2015-03-05 Kumoh National Institute Of Technology Field emission devices and methods of manufacturing gate electrodes thereof
US20160148774A1 (en) * 2014-11-21 2016-05-26 Electronics And Telecommunications Research Institute Field-emission device with improved beams-convergence
US20170084417A1 (en) * 2014-05-13 2017-03-23 Samsung Electronics Co., Ltd. Electron emitting device using graphene and method for manufacturing same
JP2018035010A (en) * 2016-08-29 2018-03-08 国立大学法人 筑波大学 Production method of multi-layer graphene and multi-layer graphene laminate
US20180158640A1 (en) * 2016-12-07 2018-06-07 Electronics And Telecommunications Research Institute Field emission apparatus
JP6635510B2 (en) * 2016-03-31 2020-01-29 国立研究開発法人産業技術総合研究所 Field emission device and device including field emission device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010055907A (en) * 2008-08-28 2010-03-11 National Institute Of Advanced Industrial Science & Technology Field emission element of focusing electrode integral type and its preparation method
US20150060757A1 (en) * 2013-09-02 2015-03-05 Kumoh National Institute Of Technology Field emission devices and methods of manufacturing gate electrodes thereof
US20170084417A1 (en) * 2014-05-13 2017-03-23 Samsung Electronics Co., Ltd. Electron emitting device using graphene and method for manufacturing same
US20160148774A1 (en) * 2014-11-21 2016-05-26 Electronics And Telecommunications Research Institute Field-emission device with improved beams-convergence
JP6635510B2 (en) * 2016-03-31 2020-01-29 国立研究開発法人産業技術総合研究所 Field emission device and device including field emission device
JP2018035010A (en) * 2016-08-29 2018-03-08 国立大学法人 筑波大学 Production method of multi-layer graphene and multi-layer graphene laminate
US20180158640A1 (en) * 2016-12-07 2018-06-07 Electronics And Telecommunications Research Institute Field emission apparatus

Also Published As

Publication number Publication date
JP2023084299A (en) 2023-06-19

Similar Documents

Publication Publication Date Title
US5151061A (en) Method to form self-aligned tips for flat panel displays
US20080018228A1 (en) Electronic emission device, electron emission display device having the same, and method of manufacturing the electron emission device
US8344607B2 (en) Electron-emitting device and display panel including the same
JP2002150922A (en) Electron emitting device, cold cathode field electron emitting device and manufacturing method therefor, and cold cathode field electron emitting display device and method of its manufacture
JP2006114494A (en) Carbon nanotube emitter and its manufacturing method as well as field emission element adopting the same and its manufacturing method
JPH09219144A (en) Electric field emitting cathode and its manufacture
KR100243990B1 (en) Field emission cathode and method for manufacturing the same
JP2900837B2 (en) Field emission type cold cathode device and manufacturing method thereof
JPH0850850A (en) Field emission type electron emission element and its manufacture
WO2023105899A1 (en) Field emission element and method for producing same
JP2006294387A (en) Nanocarbon emitter and its manufacturing method
JP2000021287A (en) Field emission type electron source and its manufacture
JPH09129123A (en) Electron emitting element and manufacture thereof
JP3622406B2 (en) Cold electron-emitting device and manufacturing method thereof
JP3832070B2 (en) Method for manufacturing cold electron-emitting device
JP3612883B2 (en) Cold electron-emitting device and manufacturing method thereof
JP2743794B2 (en) Field emission cathode and method of manufacturing field emission cathode
JP3502883B2 (en) Cold electron-emitting device and method of manufacturing the same
JP3826539B2 (en) Method for manufacturing cold electron-emitting device
JP4241766B2 (en) Cold electron emitter for lighting lamp
JP2646999B2 (en) Field emission cold cathode
JP3945049B2 (en) Method for manufacturing cold electron-emitting device
JP3595821B2 (en) Cold electron-emitting device and method of manufacturing the same
JPH04284325A (en) Electric field emission type cathode device
KR101945528B1 (en) Method for manufacturing a high-definition field emission device and the field emission device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22903833

Country of ref document: EP

Kind code of ref document: A1