KR100186253B1 - Method of manufacturing silicon fea by locos - Google Patents

Method of manufacturing silicon fea by locos Download PDF

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Publication number
KR100186253B1
KR100186253B1 KR1019950044455A KR19950044455A KR100186253B1 KR 100186253 B1 KR100186253 B1 KR 100186253B1 KR 1019950044455 A KR1019950044455 A KR 1019950044455A KR 19950044455 A KR19950044455 A KR 19950044455A KR 100186253 B1 KR100186253 B1 KR 100186253B1
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oxide film
silicon substrate
locos
silicon
gate
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KR970030055A (en
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정호련
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엄길용
오리온전기주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/14Manufacture of electrodes or electrode systems of non-emitting electrodes
    • H01J9/148Manufacture of electrodes or electrode systems of non-emitting electrodes of electron emission flat panels, e.g. gate electrodes, focusing electrodes or anode electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/022Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2329/00Electron emission display panels, e.g. field emission display panels
    • H01J2329/02Electrodes other than control electrodes
    • H01J2329/04Cathode electrodes
    • H01J2329/0407Field emission cathodes
    • H01J2329/041Field emission cathodes characterised by the emitter shape
    • H01J2329/0413Microengineered point emitters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2329/00Electron emission display panels, e.g. field emission display panels
    • H01J2329/46Arrangements of electrodes and associated parts for generating or controlling the electron beams
    • H01J2329/4604Control electrodes
    • H01J2329/4608Gate electrodes
    • H01J2329/4613Gate electrodes characterised by the form or structure

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)
  • Cold Cathode And The Manufacture (AREA)

Abstract

본 발명은 LOCOS 에 의한 실리콘 FEA 제조방법을 사용하므로서 대면적 기판에 균일한 실리콘 기판을 형성할 수 있고 포토마스크보다 적은 게이트홀을 형성하므로서 구동전압을 감소시킬 수 있는 것을 목적으로 한다.An object of the present invention is to be able to form a uniform silicon substrate in a large area substrate by using a silicon FEA manufacturing method by LOCOS and to reduce the driving voltage by forming a gate hole less than a photomask.

질화막을 실리콘 기판 위에 중착하고 LOCOS 에 의해 국부적으로 실리콘 기판을 열산화하여 열산화막을 형성한 후에, 그 열산화막을 에칭한다. 그후, 실리콘 기판을 열산화하여 게이트 산화막을 형성하고 게이트 산화막 위에 금속을 증착하여 게이트 전극을 형성한다. 원추형 팁 에미터를 노출시키기 위해 리프트 오프(lift-off)공정을 행한다.After nitriding the nitride film on the silicon substrate and locally oxidizing the silicon substrate by LOCOS to form a thermal oxide film, the thermal oxide film is etched. Thereafter, the silicon substrate is thermally oxidized to form a gate oxide film, and a metal is deposited on the gate oxide film to form a gate electrode. A lift-off process is performed to expose the conical tip emitter.

Description

LOCOS 에 의한 실리콘 FEA 제조방법Silicon FEA manufacturing method by LOCOS

제1a도 내지 제1f도는 종래의 방법에 의한 실리콘 FEA 제조공정을 나타내는 단면도,1a to 1f are cross-sectional views showing a silicon FEA manufacturing process by a conventional method,

제2a도 내지 제2f도는 본 발명에 의한 실리콘 FEA 제조공정을 나타내는 단면도.2a to 2f are cross-sectional views showing a silicon FEA manufacturing process according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

21 : 실리콘 기판 22 : 질화막21 silicon substrate 22 nitride film

23 : 열산화막 24 : 게이트 산화막23: thermal oxide film 24: gate oxide film

25 : 게이트 전극 26 : 팁 에미터25 gate electrode 26 tip emitter

본 발명은 평판 디스플레이의 FEA(Field-Emission Array) 제조방법에 관한 것으로, 더욱 상세하게는, 균일한 팁 에미터를 대면적 기판에 형성시킬 수 있을 뿐만 아니라 게이트의 홀을 감소시켜 구동전압을 낮출 수 있는 LOCOS(Local Oxidation of Silicon)에 의한 실리콘 FEA 제조방법에 의한 것이다.The present invention relates to a method for manufacturing a field-emission array (FEA) of a flat panel display, and more particularly, it is possible to form a uniform tip emitter on a large-area substrate as well as to reduce a driving hole by reducing a gate hole. It is by the method of manufacturing silicon FEA by LOCOS (Local Oxidation of Silicon).

최근, 초고집적 반도체 제조기술과 초고진공 기술이 급속히 발달함에 따라 마이크론 크기의 새로운 형태의 삼극 진공관 소자의 연구가 활기를 띠고 있다. 이러한 소자를 디스플레이에 응용하여 CRT 와 LCD의 장점만을 가진 새로운 평판 디스플레이로 개발하는데 주목하고 있다.In recent years, with the rapid development of ultra-high density semiconductor manufacturing technology and ultra-high vacuum technology, research into a new type of three-pole vacuum tube device having a micron size has been vigorous. It is paying attention to the development of a new flat panel display having only the advantages of CRT and LCD by applying such a device to a display.

FED(Field-Emission Display)는 평판 디스플레이의 일종으로서, 마이크로팁형상의 캐소우드와 전계방출을 위한 게이트 전극과 형광체가 도포된 애노우드로 구성되며, 다수의 마이크로팁으로부터 전자방출을 유도하여 발생된 전자를 애노우드의 형광체와 충돌시킴으로써 형광체의 최외각 전자가 여기되고 천이될때 발생되는 빛을 이용하여 원하는 화상 표시를 수행하는 것이다.FED (Field-Emission Display) is a kind of flat panel display, which consists of micro tip-shaped cathode, gate electrode for electric field emission, and anode coated with phosphor, and is generated by inducing electron emission from many micro tips. By colliding the electrons with the phosphor of the anode, a desired image display is performed by using light generated when the outermost electron of the phosphor is excited and transitioned.

종래의 실리콘 FEA 제조방법에 대하여 제1a도 내지 제1f도를 참조하여 설명한다.A conventional silicon FEA manufacturing method will be described with reference to FIGS. 1A to 1F.

먼저, 실리콘 기판(11)을 산화한 후에 사진식각하여 디스크형상으로 산화막(12)을 형성한다(제1a도).First, the silicon substrate 11 is oxidized and then photo-etched to form an oxide film 12 in the shape of a disc (FIG. 1a).

다음으로, 산화막(12)을 마스크로 하여 RIE(reactive ion etching)법에 의해 실리콘 기판(11)을 에칭하고(제1b도), 실리콘 기판(11)을 샤프닝 산화하여 열산화막(13)을 형성한다(제1c도).Next, the silicon substrate 11 is etched by RIE (reactive ion etching) using the oxide film 12 as a mask (FIG. 1B), and the silicon substrate 11 is sharply oxidized to form a thermal oxide film 13. (Figure 1c).

그후, 절연막(14)을 형성하기 위하여 산화막을 증착하고(제1d도), 절연막(14)위에 금속을 증착하여 게이트 전극(15)을 형성한다(제1e도).Thereafter, an oxide film is deposited to form the insulating film 14 (FIG. 1D), and a metal is deposited on the insulating film 14 to form the gate electrode 15 (FIG. 1E).

마지막으로, 게이트 전극을 마스크로 하여 열산화막(13)을 에칭하므로서 팁 에미터(16)를 형성한다(제1f도).Finally, the tip emitter 16 is formed by etching the thermal oxide film 13 using the gate electrode as a mask (FIG. 1f).

그러나, 종래의 FEA 제조방법에 있어서는, 원추형 팁 에미터를 형성하기 위하여 RIE 법을 이용하면, 대면적의 패널을 제조할때 플라즈마 밀도의 불균일로 인하여 균일하고 손상이 없는 원추형 팁 에미터의 형성이 어렵고, 얼라이너(aligner)사용시 장비의 한계로 서브마이크로(submicro) 팁을 제조할 수 없는 문제점이 있었다.However, in the conventional FEA manufacturing method, using the RIE method to form a conical tip emitter, the formation of a uniform and intact conical tip emitter due to the nonuniformity of plasma density when producing a large area panel is avoided. It was difficult and there was a problem in that it was not possible to manufacture a submicro tip due to the limitation of equipment when using an aligner.

상술한 문제점을 감안하여, 본 발명의 목적은 균일한 원추형 팁 에미터를 대면적 기판에 형성시킬 수 있을 뿐만 아니라 LOCOS에 의한 버어드 비이크(Bird's beak)효과에 의하여 포토마스크보다 더 적은 게이트홀을 형성시키므로서 구동접압을 감소시킬 수 있는 실리콘 FEA 제조방법을 제공하는 것이다.In view of the above problems, the object of the present invention is not only to form a uniform conical tip emitter on a large area substrate, but also to produce fewer gate holes than the photomask due to the Bird's beak effect by LOCOS. It is to provide a silicon FEA manufacturing method that can reduce the driving contact pressure by forming a.

본 발명의 목적을 달성하기 위하여 본 발명은 팁 마스크로서 질화막을 디스크형상으로 실리콘 기판위에 형성하는 단계와, 실리콘 기판 LOCOS에 의해 국부적으로 열산화하여 열산화막을 형성하는 단계와, 열산화막을 에칭하는 단계와, 실리콘 기판을 샤프닝(sharpening)산화하여 게이트 산화막을 형성하는 단계와, 게이트 산화막 위에 금속을 증착하여 게이트 전극을 형성하는 단계와, 원추형 팁 에미터 선단을 노출시키기 위하여 리프트 오프(lift-off)공정을 행하는 단계를 구비하는 것을 특징으로 하는 LOCOS에 의한 실리콘 FEA의 제조방법을 제공한다.In order to achieve the object of the present invention, the present invention comprises the steps of forming a nitride film on a silicon substrate as a tip mask on a silicon substrate, locally thermally oxidizing by a silicon substrate LOCOS to form a thermal oxide film, and etching the thermal oxide film. Forming a gate oxide by sharpening and oxidizing a silicon substrate; depositing a metal on the gate oxide to form a gate electrode; and lifting-off to expose the tip of the conical tip emitter. It provides a process for producing a silicon FEA by LOCOS, characterized in that it comprises a step of performing a).

이하, 제2a도 내지 제2f도를 참조하여 본 발명의 LOCOS에 의한 실리콘 FEA제조방법에 대하여 상세히 설명한다.Hereinafter, a method for manufacturing silicon FEA by LOCOS of the present invention will be described in detail with reference to FIGS. 2A to 2F.

먼저, 질화막(22)을 실리콘 기판(21)위에 증착한 후에, LPCVD(low pressure chemical vapor deposition)법에 의해 디스크형상으로 패터닝한다.(제2a도).First, the nitride film 22 is deposited on the silicon substrate 21, and then patterned into a disk by LPCVD (low pressure chemical vapor deposition). (FIG. 2A).

다음으로, LOCOS에 의해 실리콘 기판(21)을 국부적으로 열산화하여 열산화막(23)을 형성하고(제2b도), 열산화막(23)을 7 : 1(BHF)로서 에칭한다(제2c도).Next, the silicon substrate 21 is locally thermally oxidized by LOCOS to form a thermal oxide film 23 (FIG. 2B), and the thermal oxide film 23 is etched as 7: 1 (BHF) (FIG. 2C). ).

그후, 실리콘 기판(21)을 샤프닝 산화하여 게이트 산화막(24)을 형성하고(제2d도), 전자빔 증착법(E-beam evaporation)을 사용하여 게이트 산화막(24)위에 금속을 증착하여 게이트 전극(25)을 형성한다(제2e도).Thereafter, the silicon substrate 21 is sharply oxidized to form a gate oxide film 24 (FIG. 2D), and a metal is deposited on the gate oxide film 24 using an E-beam evaporation to deposit a gate electrode 25. ) (Fig. 2e).

마지막으로, 게이트 전극(25)을 마스크로 하여 게이트 산화막(24)을 7 : 1 (BHF)로서 에칭하므로서 팁 에미터(26)를 노출시킨다(제2f도).Finally, the tip emitter 26 is exposed by etching the gate oxide film 24 as 7: 1 (BHF) using the gate electrode 25 as a mask (FIG. 2f).

이상에서 설명한 바와 같이, 본 발명은 균일한 실리콘 기판을 대면적기판에 형성시킬 수 있으며 수율이 양호한 실리콘 FEA 를 제조할 수 있고, LOCOS에 의한 버어드 비이크(Bird's beak)형상으로 포토마스크의 크기보다 약 70%정도로 축소된 게이트홀을 형성하므로서 구동전압을 낮출 수 있다.As described above, the present invention can form a uniform silicon substrate on a large-area substrate, can produce a silicon FEA having a good yield, and the size of the photomask in the form of a bird's beak by LOCOS. The driving voltage can be reduced by forming the gate hole reduced to about 70%.

또한, 게이트 산화막으로서 열산화막을 사용하므로써 종래의 방법에 의해 제조된 소자의 증착 산화막의 막질 불량을 제거할 수 있다 .In addition, by using the thermal oxide film as the gate oxide film, it is possible to eliminate a film quality defect of the deposited oxide film of the device manufactured by the conventional method.

Claims (1)

팁 마스크로서 질화막을 실리콘 기판 위에 형성하는 단계와, 상기 실리콘 기판을 LOCOS에 의해 국부적으로 열산화하여 열산화막을 형성하는 단계와, 상기 열산화막을 에칭하는 단계와, 상기 실리콘 기판을 샤프닝(sharpening) 산화하여 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막 위에 금속을 증착하여 게이트 전극을 형성하는 단계와, 원추형 팁 에키터 선단을 노출시키기 위하여 리프트 오프(lift-off)공정을 행하는 단계를 구비하는 것을 특징으로 하는 LOCOS에 의한 실리콘 FEA의 제조방법.Forming a nitride film on the silicon substrate as a tip mask, locally thermally oxidizing the silicon substrate by LOCOS, etching the thermal oxide film, and sharpening the silicon substrate. Oxidizing to form a gate oxide film; depositing a metal on the gate oxide film to form a gate electrode; and performing a lift-off process to expose the tip of the conical tip emitter. Method for producing a silicon FEA by LOCOS characterized in that.
KR1019950044455A 1995-11-28 1995-11-28 Method of manufacturing silicon fea by locos KR100186253B1 (en)

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