KR100569264B1 - Method of manufacturing field emission display device - Google Patents

Abstract

The present invention provides a method of manufacturing a field emission display device capable of increasing the path between the gate electrode layer and the cathode line to prevent an electrical short circuit therebetween to stabilize the device and increase the life of the device.

According to the present invention, an insulating film is formed on a substrate on which a cathode line is formed, and a plurality of photoresist film patterns spaced at predetermined intervals are formed on the insulating film on the cathode line. Then, a gate electrode layer is formed on the entire surface of the substrate, and the gate electrode layer is etched to expose a portion of the photoresist film pattern to form a plurality of predetermined holes. Then, the photoresist pattern and the insulating layer exposed through the holes are sequentially etched to expose the cathode lines, thereby forming a plurality of gate holes, and then forming a plurality of emitter tips on the cathode lines in the gate holes, The resist film pattern is removed.

Description

Method of manufacturing field emission display device

1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional field emission display device.

2A to 2F are cross-sectional views illustrating a method of manufacturing a field emission display device according to a first embodiment of the present invention.

3A and 3B are cross-sectional views illustrating a method of manufacturing a field emission display device according to a second embodiment of the present invention.

4A and 4B are cross-sectional views illustrating a method of manufacturing a field emission display device according to a third embodiment of the present invention.

5A and 5B are cross-sectional views illustrating a method of manufacturing a field emission display device according to a fourth embodiment of the present invention.

6A and 6B are cross-sectional views illustrating a method of manufacturing a field emission display device according to a fifth embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

20: substrate 21: cathode line

22, 22A, 22B: insulating film

23, 23A, 23B, 23C: photoresist film pattern

24: gate electrode layer

26A, 26B, 26C: Emitter Tip

H1, H2, H3: Gate Hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field emission display device, and more particularly, to a method of manufacturing a field emission display device capable of preventing an electrical short between a cathode line and a gate electrode layer.

In general, a field emission display (FED) is a display using a principle of matrix-accessing a field emission array (FEA) and generating cathode ray emission by stimulating a phosphor with an electron beam like a CRT.

This FED has a cathode plate and an anode plate, and a spacer is interposed therebetween. In addition, the cathode plate is provided with a gate electrode and several emitter tips for emitting electrons to form FEA, and the anode plate is provided with an indium tin oxide (ITO) electrode and a phosphor to realize colorization of the field emission display device.

On the other hand, the emitter tip for determining the brightness of the field emission display device is formed by forming a predetermined hole in the gate electrode layer, and then depositing a metal in the shape of a cone in the hole.

1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional FED device.

As shown in FIG. 1A, a cathode line 11 is formed on a substrate 10 such as glass or a wafer, and an insulating film 12 and a gate electrode layer 13 are sequentially formed on the entire surface of the substrate. Next, as shown in FIG. 1B, the gate electrode layer 13 is etched to expose a portion of the insulating layer 12 to form a hole having a diameter of 0.3 to 1.5 μm.

Referring to FIG. 1C, the insulating layer 12 exposed using the gate electrode layer 13 as a mask is etched by BOE (Buffer Oxide Etcher) or Reactive Ion Etching (RIE) to expose the cathode line 11. Gate holes H1, H2, and H3 are formed. Then, the substrate 11 is mounted on the vacuum deposition equipment, and the aluminum film 14 is deposited on the surface of the gate electrode layer 13 as a sacrificial layer while rotating about a rotation axis perpendicular to the surface of the substrate 11. At this time, the aluminum particles are incident at an angle of 15 to 30 degrees with respect to the substrate surface, and the aluminum film 14 is also deposited on the edges of the gate electrode layer 13 and the gate holes H1, H2, and H3.

Referring to FIG. 1D, a tip forming material film 15 such as a Mo film, a MoW film, and a Cr film is deposited on the structure of FIG. 1C by using an E-beam evaporation apparatus, and the cathode line 11 is deposited. After the conical emitter tips 15A, 15B, and 15C are formed, the tip forming material film 15 and the aluminum film 14 deposited on the aluminum film 14, as shown in FIG. ) Is removed in a lift off manner.

On the other hand, although only three tips are shown in this figure, in the actual process, 10 to 10,000 tips are formed in one cathode line.

However, in the manufacture of the FED element as described above, the conductivity of the surface of the insulating film 12 after etching is increased by the surface dangling bonds caused by foreign matters generated on the etching surface during the etching of the insulating film 12. Accordingly, as described above, when the path between the cathode line 11 and the gate electrode layer 13 is short, the gate electrode layer 13 and the cathode line 11 are electrically shorted and a leakage current is generated. . As a result, not only the device becomes unstable, but also the life of the device is shortened.

Accordingly, the present invention is to solve the above-mentioned conventional problems, and to increase the path between the gate electrode layer and the cathode line to prevent the electrical short between them to stabilize the device as well as to increase the life of the device electric field It is an object of the present invention to provide a method of manufacturing a light emitting display device.

In order to achieve the above object, according to the first embodiment of the present invention, an insulating film is formed on a substrate on which a cathode line is formed, and a plurality of photoresist film patterns spaced at predetermined intervals are formed on the insulating film on the cathode line. do. Then, a gate electrode layer is formed on the entire surface of the substrate, and the gate electrode layer is etched to expose a portion of the photoresist film pattern to form a plurality of predetermined holes. Then, the photoresist pattern and the insulating layer exposed through the holes are sequentially etched to expose the cathode lines to form a plurality of gate holes, and then a plurality of emitter tips are formed on the cathode lines in the gate holes. The photoresist film pattern is removed.

In addition, according to the second embodiment of the present invention, an insulating film is formed on a substrate on which a cathode line is formed, and a photoresist film pattern is formed on the insulating film on the cathode line in the form of a cathode line. Next, a gate electrode layer is formed on the entire surface of the substrate, and the gate electrode layer, the photoresist layer pattern, and the insulating layer are sequentially etched to expose the cathode line, thereby forming a plurality of gate holes. Then, a plurality of emitter tips are formed on the cathode line in the gate hole, and the photoresist film pattern is removed.

In addition, according to the third embodiment of the present invention, an insulating film is formed on a substrate on which a cathode line is formed, and a plurality of photoresist film patterns spaced at predetermined intervals are formed on the cathode line. Then, an insulating film and a gate electrode layer are sequentially formed on the entire surface of the substrate, and the gate electrode layer, the insulating film and the photoresist film pattern are sequentially etched to expose the cathode line, thereby forming a plurality of gate holes. Then, a plurality of emitter tips are formed on the cathode line in the gate hole, and the plurality of photoresist film patterns are removed.

In addition, according to the fourth embodiment of the present invention, a first insulating film is formed on a substrate having a cathode line formed thereon, and a plurality of photoresist film patterns spaced at predetermined intervals are formed on the first insulating film on the cathode line. . Then, the second insulating film and the gate electrode layer are sequentially formed on the entire surface of the substrate, and the gate electrode layer, the second insulating film, the photoresist film pattern, and the second insulating film are sequentially etched to expose the cathode line, thereby forming a plurality of gate holes. . Then, a plurality of emitter tips are formed on the cathode line in the gate hole, and the plurality of photoresist film patterns are removed.

In addition, according to the fifth exemplary embodiment of the present invention, a photoresist film pattern is formed on the substrate on which the cathode line is formed, so as to completely cover the cathode line, and a gate electrode layer is formed on the entire surface of the substrate. Then, the gate electrode layer and the photoresist film pattern are sequentially etched to expose the cathode line, thereby forming a plurality of gate holes, and forming a plurality of emitter tips on the cathode line in the gate hole, and then removing the photoresist film pattern. do.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a method of manufacturing a field emission display device according to a first embodiment of the present invention.

Referring to FIG. 2A, a cathode line 21 is formed on a substrate 20 such as glass or a wafer, and an insulating film 22 is formed on the entire surface of the substrate to a thickness of 0.2 to 1 μm. Here, the insulating film 22 is formed of a SiO ₂ film, a SiON film, or a SiNx film. Then, a plurality of photoresist film patterns 23A and 23B spaced at predetermined intervals on the insulating film 22 on the cathode line 21 are deposited and patterned on the insulating film 22 to a thickness of 0.13 to 1 탆. , 23C). Then, the gate electrode layer 24 is formed on the entire surface of the substrate with one material selected from the group consisting of Cr film, Mo film, MoW film, and W film.

Referring to FIG. 2B, the gate electrode layer 24 is etched to expose a portion of the photoresist film patterns 23A, 23B, and 23C to form predetermined holes. 2C, the exposed photoresist film patterns 23A, 23B, and 23C are etched using the gate electrode layer 24 as a mask to expose the insulating film 22. Then, the exposed insulating film 22 using the gate electrode layer 24 and the photoresist film patterns 23A, 23B, and 23C as an etch mask is etched by BOE or RIE to expose the cathode line 21, and as shown in FIG. 2D. As shown, the gate holes H1, H2, and H3 are formed.

Referring to FIG. 2E, an aluminum film (not shown) is mounted on the surface of the gate electrode layer 24 while the substrate 21 is mounted on the vacuum deposition apparatus and rotated about a rotation axis perpendicular to the surface of the substrate 21. To deposit. At this time, the aluminum particles are incident at an angle of 30 degrees with respect to the substrate surface, and the aluminum film is also deposited on the edges of the gate electrode layer 24 and the gate holes H1, H2, and H3. Then, a tip forming material film such as a Mo film, a MoW film, and a Cr film is deposited on the entire surface of the substrate by using an E-beam evaporation apparatus, and an emitter tip in the form of a cone is formed on the cathode line 21. (26A, 26B, 26C). Then, the tip forming material film and the aluminum film deposited on the aluminum film is removed by a lift-off method.

Then, as shown in FIG. 2F, the photoresist film patterns 23A, 23B, and 23C are removed by an ashing process or by wet or dry etching.

According to the first embodiment described above, the path between the cathode line 21 and the gate electrode layer 24 is increased by the photoresist film patterns 23A, 23B, and 23C, thereby preventing an electrical short between them.

3A and 3B are cross-sectional views illustrating a method of manufacturing a field emission display device according to a second exemplary embodiment of the present invention. Unlike the above-described exemplary embodiment, the gate is shown in FIG. Before the formation of the electrode layer 24, a photoresist film pattern 23 having a thickness of 0.13 to 1 탆 is formed on the insulating film 22 in the form of a cathode line 21, and then the subsequent steps as in the first embodiment are performed. Proceed.

Accordingly, as shown in FIG. 3B, after removal of the photoresist film pattern 23, a path between the cathode line 21 and the gate electrode layer 24 is increased, thereby preventing an electrical short between them.

4A and 4B are cross-sectional views illustrating a method of manufacturing a field emission display device according to a third embodiment of the present invention. Unlike this embodiment, as shown in FIG. Before forming the insulating film 22, a plurality of photoresist film patterns 23A, 23B, and 23C having a thickness of 0.13 to 1 μm and spaced at predetermined intervals are formed on the cathode line 21 in the same manner as in the first embodiment. Subsequently, the same process as in the first embodiment is performed.

Accordingly, as shown in FIG. 4B, after the removal of the photoresist film patterns 23A, 23B, and 23C, the path between the cathode line 21 and the gate electrode layer 24 is increased, so that an electrical short circuit therebetween occurs. Is prevented.

5A and 5B are cross-sectional views illustrating a method of manufacturing a field emission display device according to a fourth embodiment of the present invention. In the present embodiment, as shown in FIG. 5A, unlike FIG. The insulating film 22 is formed of a double film of the first and second insulating films 22A and 22B, and has a thickness of 0.13 to 1 µm therebetween and is spaced at predetermined intervals in the same manner as in the first embodiment. After the photoresist film patterns 23A, 23B, and 23C are formed, the subsequent steps as in the first embodiment are performed.

Accordingly, as shown in FIG. 5B, after the removal of the photoresist film patterns 23A, 23B, and 23C, the path between the cathode line 21 and the gate electrode layer 24 is increased, so that an electrical short circuit therebetween occurs. Is prevented.

6A and 6B are cross-sectional views illustrating a method of manufacturing a field emission display device according to an embodiment of the present invention. In this embodiment, unlike the above-described embodiment, as shown in FIG. 6A, a cathode line (instead of an insulating film) is used. The photoresist film pattern 23 is formed so as to completely cover 21), and the subsequent steps as in the first embodiment are performed.

Thus, as shown in FIG. 6B, since no insulating film is present, a short circuit between the cathode line 21 and the gate electrode layer 24 due to the increase in the surface conductivity of the insulating film is prevented.

According to the present invention described above, after the photoresist film pattern is formed between the cathode line and the gate electrode layer, the photoresist film pattern is removed or the use of the insulating film is eliminated, thereby increasing the path therebetween, resulting from the surface conductivity of the insulating film. The problem of electrical short between them is avoided. This not only stabilizes the device but also increases the life of the device.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (9)

Forming an insulating film on a substrate having a cathode line formed thereon; Forming a plurality of photoresist film patterns spaced at predetermined intervals on the insulating film on the cathode line; Forming a gate electrode layer on the entire surface of the substrate; Etching the gate electrode layer to expose a portion of the photoresist layer pattern to form a plurality of predetermined holes; Sequentially etching the photoresist pattern and the insulating layer exposed through the holes to expose the cathode line to form a plurality of gate holes; Forming a plurality of emitter tips on the cathode line in the gate hole; And And removing the plurality of photoresist film patterns. The method of claim 1, wherein the thickness of the photoresist film pattern is 0.13 to 1 μm. Forming an insulating film on a substrate having a cathode line formed thereon; Forming a photoresist film pattern on the cathode line in the form of the cathode line; Forming a gate electrode layer on the entire surface of the substrate; Sequentially etching the gate electrode layer, the photoresist layer pattern, and the insulating layer to expose the cathode line to form a plurality of gate holes; Forming a plurality of emitter tips on the cathode line in the gate hole; And And removing the photoresist film pattern. The method of claim 3, wherein the thickness of the photoresist film pattern is 0.13 to 1 μm. Forming an insulating film on a substrate having a cathode line formed thereon; Forming a plurality of photoresist film patterns spaced at predetermined intervals on the cathode line; Sequentially forming an insulating film and a gate electrode layer over the substrate; Sequentially etching the gate electrode layer, the insulating layer, and the photoresist layer pattern to expose the cathode line to form a plurality of gate holes; Forming a plurality of emitter tips on the cathode line in the gate hole; And And removing the plurality of photoresist film patterns. The method of claim 5, wherein the photoresist film pattern has a thickness of 0.13 to 1 μm. Forming a first insulating film on a substrate having a cathode line formed thereon; Forming a plurality of photoresist film patterns spaced at predetermined intervals on the first insulating film on the cathode line; Sequentially forming a second insulating film and a gate electrode layer on the entire surface of the substrate; Sequentially etching the gate electrode layer, the second insulating layer, the photoresist layer pattern, and the second insulating layer to expose the cathode line to form a plurality of gate holes; Forming a plurality of emitter tips on the cathode line in the gate hole; And And removing the plurality of photoresist film patterns. The method of claim 7, wherein the photoresist film pattern has a thickness of 0.13 to 1 μm. Forming a photoresist film pattern on the substrate having the cathode line formed thereon to completely cover the cathode line; Forming a gate electrode layer on the entire surface of the substrate; Sequentially etching the gate electrode layer and the photoresist layer pattern to expose the cathode line to form a plurality of gate holes; Forming a plurality of emitter tips on the cathode line in the gate hole; And And removing the photoresist film pattern.

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