JP3239285B2 - Method of manufacturing field emission cathode - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission cathode known as a cold cathode, and more particularly to a method for manufacturing a field emission cathode capable of improving a manufacturing yield.

[0002]

2. Description of the Related Art An electric field applied to a metal or semiconductor surface is 10
^{When the} voltage is set to about ⁹ [V / m], electrons pass through the barrier due to the tunnel effect and emit electrons in a vacuum even at room temperature. This is called field emission,
A cathode that emits electrons according to such a principle is called a field emission cathode (Field Emission Cathode). In recent years, it has become possible to create surface emission field emission cathodes composed of micron-sized field emission cathodes by making full use of semiconductor processing technology. Field emission cathodes are used in fluorescent displays, electronic devices, electron microscopes, and the like. It has been developed as an element constituting an electron beam device.

FIG. 5 is a perspective view of an example of a device using a field emission cathode (hereinafter referred to as FEC) called a Spindt type having a resistance between an emitter and a cathode. In this figure, a cathode electrode layer (line) 101 is formed on a substrate 100,
On this cathode electrode layer 101, a cone-shaped emitter 115 formed by a manufacturing method described later is formed via a resistance layer 102. Further, a gate electrode layer (line) 104 is provided on the resistance layer 102 via an insulating layer 103, and the above-mentioned cone-shaped emitter 115 is inserted into a round opening provided in the gate electrode layer 104. The tip of the emitter 115 is disposed on the gate electrode layer 10.
4 from the opening opened in.

The pitch between the emitters 115 can be 10 μm or less. Tens of thousands or hundreds of thousands of such emitters are provided on one substrate 100, and x, y as shown in the figure. By applying a scan voltage from the cathode drive circuit and the gate drive circuit to the cathode electrode layer 101 and the gate electrode layer 104 extending in the directions,
Electrons are emitted from the field emission element block located in the area of the intersection, and the anode electrode 1 disposed opposite to the anode electrode 1
The fluorescent substance applied to the light emitting layer 20 emits light.

The emitter 115 and the cathode electrode layer 1
When a resistive layer is provided between the emitters 01, a large current flows through the emitters even when a short circuit occurs between some of the emitters and the gate which are arranged very close due to dust or impact during the manufacturing process or operation, and the emitters are blown. An accident that the emitter scatters around and loses the function of all the field emission cathodes near the emitter can be prevented.

Furthermore, since electrons are apt to be emitted from one of the many emitters which emits electrons easily, current is concentrated on the emitter and an abnormally bright spot may be generated on the screen. However, it is extremely effective to provide a resistance region between the cathode and the emitter in order to prevent these operational disadvantages.

Next, an example of a manufacturing process of the Spindt-type FEC as described above will be described with reference to FIG. First, FIG.
As shown in (a), a cathode electrode layer 101 is formed on a substrate 100 made of glass or the like by vapor deposition, and further, a metal material is sputter-deposited thereon to form a resistive layer 102, and then oxidized. Silicon insulation layer 10
3 are formed. Further, the gate electrode layer 1
Niobium (Nb) to be deposited on the gate electrode layer 1
After applying a photoresist on the substrate 04, patterning and etching are performed as shown in FIG. 6B to form an opening 113 in the gate electrode layer 104.

Such a laminated substrate is wet-etched with buffered hydrofluoric acid (BHF) or the like, or
_{4 The} insulating layer 103 is etched by reactive ion etching (RIE) to form a hole 114 for forming the emitter 115 in the insulating layer 103 (FIG. 6C). Next, as shown in FIG. 6C, while the substrate 100 is being rotated, evaporation of aluminum to be the release layer 105 is performed in an oblique direction. When the oblique deposition is performed in this manner, the release layer 105 is selectively deposited only on the surface of the gate electrode layer 104 without being deposited in the opened hole.

Further, as shown in FIG.
Material layer 10 made of a mixture of molybdenum and the like from above
6 is deposited from the vertical direction by electron beam evaporation (EB). Then, the material layer 106 is also deposited in the hole 114 formed in the insulating layer 103, and is deposited as a conical cone on the resistance layer 102, and this is formed as the emitter 115. Thereafter, when the peeling layer 105 and the material layer 106 on the gate electrode layer 104 are both removed by etching, a single FEC having a shape as shown in FIG. 6E can be obtained.

In the FEC shown in FIG. 6E, the distance between the cone-shaped emitter 115 and the gate electrode layer 104 can be made submicron, so that a voltage of only several tens of volts is applied between the emitter 115 and the gate electrode layer 104. Is applied, electrons can be emitted from the emitter 115.

[0011] As shown in FIG. 6F, a second insulating layer 107 and a second gate electrode layer 108 are stacked on the upper surface of the gate electrode layer 104, and the above-described F
When the EC manufacturing process is performed, an FEC having a triode structure in which the second gate 108 is used as a focusing electrode can be formed.

[0012]

By the way, when a large number of field emission cathodes as described above are formed on a substrate and are adapted to, for example, a display device, they face the field emission element as shown in FIG. Anode electrode 120 that emits light by collision of electrons at a distance of about 200 μm in a vacuum
It is known that an emitter that emits electrons is divided into blocks in units of an appropriate number, and a scanning voltage is applied to each of the divided blocks to form an image display device.

In the case of such a display device, the cathode electrode is divided into blocks corresponding to the pixels in order to scan each of the field emission elements which are blocked according to the image signal. Cathode electrode layer is approximately 0.2 μm
When divided into blocks according to this thickness, uneven portions are formed in the portions of the insulating layer and the gate electrode layer laminated between the blocks, and the film quality of the step portion is a portion having no step. Therefore, there is a problem that a crack is formed in this portion depending on conditions.

That is, as shown in an enlarged view in FIG. 7, a cathode electrode layer 101 blocked in a predetermined region is deposited on a substrate 100, and an amorphous silicon layer 102 serving as a resistance layer is deposited thereon. And an insulating layer 103 are formed, and niobium to be a gate electrode layer 104 is further deposited on the upper surface thereof to form a laminated substrate. Then, the method for producing the Spindt described above, but the predetermined number of the field emission cathodes on the cathode electrode emitter is formed is constructed, cathode - the cathode electrode layer and the region L _C, adjacent between cathode L As shown in the drawing, a step of uneven shape is generated depending on the thickness of the cathode electrode layer 101, and a concave sink is generated particularly in a portion of the gate electrode layer 104 deposited on the uppermost layer.

Then, when niobium of a thin film serving as a gate electrode is vapor-deposited on the submerged region, Q
When a crack is formed at the position indicated by the dot and patterning or etching for forming the field emission element is performed in this state, disconnection due to etching of the crack lower part and distortion due to internal stress of the element are generated, and each of the blocked There is a problem that the yield is extremely low as a manufacturing method in which the characteristics of the field emission device become non-uniform and a number of rejected products having unevenness on the display surface occur frequently.

[0016]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a field emission cathode in which the above-mentioned problems in manufacturing can be solved. A n-type or p-type amorphous silicon layer is formed, and a predetermined position of the n-type or p-type amorphous silicon layer is polycrystallized by annealing with a laser beam to form a cathode electrode. A field emission cathode is formed by forming an emitter and a gate electrode on the upper surface of the silicon layer by the Spindt method.

[0017]

The n or p-type amorphous silicon layer deposited on the substrate by the plasma CVD method or the like has a resistivity of 1 by being doped with, for example, phosphorus or boron.
0 ² to 10 ⁶ Ω / cm, and operates as a resistance layer for suppressing the current of the emitter. When a predetermined region of the n-type or p-type amorphous silicon layer is annealed by a laser, the annealed portion is heated by thermal energy. Polycrystalline from the amorphous state, with a resistivity of 10 ^-1
To 10 ⁻³ Ω / cm. Therefore, when an insulating layer and a gate electrode layer are deposited by using the annealed region as a cathode electrode, the laminated substrate has a flat shape and the uneven portion is eliminated, so that a field emission device having uniform characteristics can be constructed. .

[0018]

1 and 2 show the steps of manufacturing a field emission cathode according to the present invention.
An n or p-type amorphous silicon layer 122 doped with phosphorus is formed on one surface of the substrate 1 by a plasma CVD method.

[0019] The n-type Amorufu Ass silicon layer by plasma decomposition by mixing several tens of% of PH ₃ from a few percent to S _i H ₄ or Si ₂ H ₆ as the gas species, resistivity of 10 ²
It is formed as an n-type amorphous silicon layer having a thickness of 10 ⁶ Ω / cm and serves as a FEC resistance layer as shown in FIG. As the doping material, arsenic (As) or the like can be mixed in addition to phosphorus. Also,
As the p-type dopant, gallium (Ga), indium (In), or the like can be mixed in addition to boron (B ₂ H ₆ ) .

Then, as shown in FIG. 1 (b), for example, an annealing process for irradiating an excimer laser Lp (wavelength 308 nm) to instantaneously heat a predetermined region is performed.
Alternatively, when the laser-irradiated portion of the p-type amorphous silicon layer 122 is polycrystallized from an amorphous state, the doped phosphorus is activated, and the annealed region 123 has a resistivity of 10 ^-1 to 10 ^-3. It changes to a conductor of Ω / Cm.

[0021] Thus after annealed to n or p-type amorphous silicon layer 122 is disposed on a glass substrate, FIG. 1 (c) as shown in example SiO ₂
Thereafter, an insulating layer 124 and a gate electrode layer 125 made of niobium or the like are formed, and the FEC is formed as shown in FIG. 126 is formed, a hole is formed in the gate electrode layer 125 by etching (FIG. 1D), and then, as shown in FIG. A hole is formed in the insulating layer 124 by isotropic etching. Then, when an emitter material layer made of molybdenum or the like is deposited from these holes by an electron beam evaporation method or the like, FIG.
As shown in (f), a cone-shaped emitter 115 having a conical tip is formed on the n-type or p-type amorphous silicon layer 122. Then, the FEC of the present invention is formed by removing the resist layer 126 and the release layer 127 in the same manner as in the conventional manufacturing method. (Figure 2
G)

In the field emission cathode of the present invention, as described above, a resistance layer is formed by the n or p type amorphous silicon layer 122, and laser annealing is performed on a predetermined position of the n or p type amorphous silicon layer 122. Since the doping material is activated when the n- or p-type amorphous silicon layer is polycrystallized from amorphous silicon to change into a good conductor, this conductor portion can be used as the cathode electrode region 123.
Therefore, each emitter is connected to the cathode electrode region 123 via the n or p-type amorphous silicon layer forming the resistance layer.

In the FEC structure of the present invention, all the layers become flat in the state of the laminated substrate, and the laminated state in which the upper surface of the portion corresponding to the cathode electrode rises as in the conventional FEC does not occur. , FEC are manufactured on a flat surface, and the thickness of the gate electrode and the height of the emitter can be made uniform.

The shape of the cathode electrode region 123 formed by laser annealing the resistance layer formed by the n or p type amorphous silicon layer is, for example, as shown in FIG. Block 1 divided into emission cathode elements 128 as a group
29 can be formed. In the case of a display device, the shape of the cathode electrode 123 is changed as shown in FIG.
As shown in (1), the cathode electrode layer 101 may be configured in a strip shape.

By the way, when a cathode electrode is arranged on a substrate as shown in FIG. 2 (g), each emitter in the block is connected to the cathode electrode via a resistance layer made of an n or p type amorphous silicon layer. The problem that the path lengths to be connected are different remains. Therefore, when a laminated substrate is formed as shown in FIG. 4 below, an FEC having a uniform resistance layer on a strip-shaped cathode electrode layer can be formed.

That is, as shown in FIG. 4, a substrate 131 made of glass or the like is coated with an insulating amorphous silicon or polysilicon mixed with impurities by a sputter deposition method or a plasma CVD method to form a first film. An insulating layer 132 is formed. When a predetermined range B of the first insulating layer 132 is annealed by an excimer laser or the like, a part of the layer made of amorphous silicon is crystallized, and the resistivity is about 10 ^-1 to 10 ^-3 Ω / cm. Is crystallized. Then, as shown in FIG.
The n or p-type amorphous silicon layer 134 is deposited on the upper surface of the substrate 3 by a low pressure CVD method, and an insulating layer 135 and a gate electrode layer 136 are formed thereon as shown in FIGS.

In the method described with reference to FIGS. 1 and 2, a hole is formed in the insulating layer 135, and an emitter is formed from the hole by depositing molybdenum or the like. In the case of this embodiment, the emitter is formed. As shown in FIG. 1C, before the insulating layer 135 is formed, a hole is formed in the insulating layer 135 and then a laser LP is applied to the insulating layer 135 so as to locally cover the portion formed by the n or p type amorphous silicon layer 134. Resistance region 1
Laser annealing for forming 37 is performed. Then, as shown by the cross-hatched lines, a part of the n-type or p-type amorphous silicon layer 134 that has been annealed is locally formed in the resistance region 1.
37, which indicates a resistance such that the resistivity is in the range of about 10 ² to 10 ⁶ Ω / cm.

In order to accurately realize this resistivity, the n-type or p-type amorphous silicon layer 1 on the laminated substrate is required.
34, a test area is provided in a partial area, and the laser annealing time,
It is preferable to carry out while adjusting the strength and the like. Then, after the resistance region 137 is formed by the above-described laser annealing, the molybdenum material is vertically deposited by electron beam evaporation as described above, and the emitter 115 is deposited in the hole of the insulating layer.

Therefore, in the case of this embodiment, FIG.
As shown in (d), a resistance region 137 also formed by annealing is provided above the cathode electrode region 133 formed by annealing, and the cone-shaped emitter 115 is provided on the resistance region 137. F
Can be EC.

In this embodiment, all the emitters 115 mounted above the cathode electrode region 133 are connected to the cathode electrode region 133 via the same resistance region 137. When 133 is controlled as a scanning electrode, the potential of each emitter can be kept completely the same.

In the above embodiment, the laser is irradiated from above the laminated substrate when performing the laser annealing, but the portion to be the cathode electrode layer is annealed from the back side of the substrate by utilizing the transparency of the glass substrate. Can also be formed. Therefore, in the manufacturing method shown in FIGS. 1, 2 and 4, it is also possible to form the cathode electrode region 123 or 133 after finally completing the FEC.

[0032]

As described above, according to the present invention, since the cathode electrode formed on the glass substrate is formed by laser annealing the n-type or p-type amorphous silicon layer, various constituent materials constituting the FEC are provided. When laminating, these layers can be processed in a flat state. Therefore, various problems caused by the swelling of the cathode electrode when forming the laminated substrate as in the related art can be eliminated, and the production of defect-free and homogeneous field emission cathodes can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first half showing a manufacturing process of a field emission cathode of the present invention.

FIG. 2 is an explanatory diagram of a latter half showing a manufacturing process of the field emission cathode of the present invention.

FIG. 3 is an explanatory diagram of a cathode electrode formed by laser annealing.

FIG. 4 is an explanatory view showing a manufacturing process of a field emission cathode showing another embodiment of the present invention.

FIG. 5 is a perspective view showing an example of an apparatus using a field emission cathode.

FIG. 6 is an explanatory view showing a conventional method for manufacturing a field emission cathode.

FIG. 7 is an enlarged cross-sectional view of unevenness of a laminated substrate generated by a conventional manufacturing method.

[Explanation of symbols]

 121, 131 substrate 122 n or p-type amorphous silicon layer 123 cathode electrode region 123 insulating layer 125 gate electrode layer 115 emitter

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Waka Otsu 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Corporation (56) References JP-A-4-229922 (JP, A) JP-A-7- 14500 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01J 9/02

Claims (3)

(57) [Claims] 1. A plasma CVD method or a reduced pressure C
An n or p-type amorphous silicon layer is formed by a VD method or the like, and a predetermined position of the n or p-type amorphous silicon layer is polycrystallized by laser annealing to form a cathode electrode region. Field emission cathode, wherein at least an insulating layer and a gate electrode layer are formed on an upper surface of a type amorphous silicon layer, and a large number of emitters and gate electrodes are formed by an FEC manufacturing process of etching and depositing predetermined positions. Manufacturing method. 2. The method according to claim 1, wherein the cathode electrode is formed to surround a plurality of the emitters. 3. The S _i H _4, or PH ₃ to Si ₂ H ₆ the n-type amorphous silicon layer as the gas species, and p-type
Amorphous silicon layer S _i H ₄ as a gas species, or
By plasma decomposition on Si ₂ H ₆ as a mixture of B ₂ H _6,
The method for producing a field emission cathode according to claim 1, wherein the resistivity is 10 ² Ω / cm to 10 ⁶ Ω / cm.