JPH07141984A - Manufacture of field emission cathode - Google Patents

Abstract

PURPOSE:To improve a yield when a field emission cathode element is manufactured. CONSTITUTION:An (n) or (p) type amorphous silicon layer 122 having a resistivity of 10<2>OMEGA/cm-10<4>OMEGA/cm degree is vapor-deposited on the upper surface of a substrate 121 of glass, etc., to irradiate a laser beam to the given region of this layer to perform annealing treatment. An annealed region can by polycrystallized from an amorphous condition to be changed into a cathode region 123 having resistivity near to that of a conductor. When an insulating layer 124 and a gate electrode layer 125 are formed into films on the upper surface of this (n) or (p) type amorphous silicon layer 122, the respective layers of a laminated substrate for manufacturing an FEC can be flattened to eliminate the crack of a gate electrode apt to be generated an FEC manufacturing process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission cathode known as a cold cathode, and more particularly to a method for manufacturing a field emission cathode capable of improving a manufacturing yield.

[0002]

2. Description of the Related Art The applied electric field on the surface of a metal or semiconductor is reduced to 10
^At about ⁹ [V / m], the electrons pass through the barrier due to the tunnel effect, and the electrons are emitted in vacuum even at room temperature. This is called field emission,
A cathode that emits electrons based on this principle is called a field emission cathode. In recent years, it has become possible to create a surface emission type field emission cathode consisting of a micron size field emission cathode by making full use of semiconductor processing technology.The field emission cathode is used for a fluorescent display device, an electronic device, an electron microscope, It has been developed as an element that constitutes an electron beam device.

FIG. 5 is a perspective view of an example of a device using a field emission cathode (hereinafter referred to as FEC) called a Spindt type having resistance between an emitter and a cathode. In this figure, a cathode electrode layer (line) 101 is formed on a substrate 100,
On this cathode electrode layer 101, a cone-shaped emitter 115 formed by a manufacturing method described later is formed via a resistance layer 102. Further, a gate electrode layer (line) 104 is provided on the resistance layer 102 via an insulating layer 103, and the cone-shaped emitter 115 described above is provided in a round opening provided in the gate electrode layer 104. The emitter 115 is arranged so that the tip portion of the emitter 115 is the gate electrode layer 10.
It faces from the opening opened in 4.

The pitch between the emitters 115 can be 10 microns or less. Tens of thousands to hundreds of thousands of such emitters are provided on one substrate 100, and as shown in the drawing, x, y. By applying a scanning voltage from the cathode drive circuit and the gate drive circuit to the cathode electrode layer 101 and the gate electrode layer 104 extending in the direction,
Electrons are emitted from the field emission device block located in the region of the intersection, and the anode electrodes 1 are arranged facing each other.
The fluorescent substance coated on 20 is made to emit light.

The emitter 115 and the cathode electrode layer 1
If a resistance layer is provided between the electrodes 01 and 01, even if a short circuit occurs between a part of the emitter and the gate, which are arranged in close proximity to each other due to dust or shock during the manufacturing process or operation, a large current flows to the emitter and blows off. It is possible to prevent the accident that the emitter scatters to the periphery and loses the function of all the field emission cathodes near the emitter.

Further, among many emitters, electrons are likely to be concentrated and emitted from the one where electrons are likely to be emitted, so that the current is concentrated on the emitter, which may cause an abnormally bright spot on the screen. However, it is extremely effective to provide a resistance region between the cathode and the emitter in order to prevent these operation defects.

Next, an example of the manufacturing process of the Spindt-type FEC as described above will be described with reference to FIG. First, FIG.
As shown in (a), a cathode electrode layer 101 is formed on a substrate 100 such as glass by vapor deposition, and a metal material is sputter-deposited thereon to form a resistance layer 102, and further oxidation is performed. Insulating layer 10 made of silicon
3 is formed. Furthermore, the gate electrode layer 1 is formed on top of it.
Niobium (Nb) to be 04 is vapor-deposited to form the gate electrode layer 1
After the photoresist is coated on 04, patterning and etching are performed as shown in FIG. 6B to form an opening 113 in the gate electrode layer 104.

Such a laminated substrate is wet-etched with buffered hydrofluoric acid (BHF) or the like, or CF is used.
_{4. The} insulating layer 103 is etched by reactive ion etching (RIE) to form a hole 114 for forming an emitter 115 in the insulating layer 103 portion (C in FIG. 6). Next, as illustrated in FIG. 6C, evaporation of aluminum to be the separation layer 105 is performed in an oblique direction while rotating the substrate 100. When the oblique deposition is performed in this manner, the peeling layer 105 is not deposited in the opened hole but is selectively deposited only on the surface of the gate electrode layer 104.

Further, as shown in FIG. 6 (d), the release layer 1
Material layer 10 composed of a mixture of molybdenum and the like from above 05
6 is vertically deposited by electron beam evaporation (EB). Then, the material layer 106 is also deposited in the holes 114 formed in the insulating layer 103, and is deposited as a conical cone on the resistance layer 102 to form the emitter 115. After that, when the separation layer 105 and the material layer 106 on the gate electrode layer 104 are both removed by etching, a single FEC having a shape as shown in FIG. 6E can be obtained.

Since the distance between the cone-shaped emitter 115 and the gate electrode layer 104 can be made submicron in the FEC shown in FIG. 6E, a voltage of only several tens of volts is applied between the emitter 115 and the gate electrode layer 104. By applying, it becomes possible to emit electrons from the emitter 115.

As shown in FIG. 6F, the second insulating layer 107 and the second gate electrode layer 108 are laminated on the upper surface of the gate electrode layer 104, and the above-mentioned F is formed.
When the EC manufacturing process is performed, an FEC having a triode structure in which the second gate 108 is used as a focusing electrode can be configured.

[0012]

By the way, when a large number of field emission cathodes as described above are formed on a substrate and applied to a display device, for example, they face the field emission device as shown in FIG. Anode electrode 120 that emits light by collision of electrons at a distance of approximately 200 μm in vacuum
It is known that an image display device is provided by dividing an emitter that emits electrons into blocks with an appropriate number of units, and applying a scanning voltage to each of the divided blocks.

In the case of such a display device, the cathode electrode is divided into blocks corresponding to the pixels in order to scan the field emission devices which are blocked corresponding to the image signal. The cathode electrode layer is approximately 0.2 μm
There is a certain thickness, and when divided into blocks due to this thickness, uneven steps are generated in the insulating layer and the gate electrode layer that are stacked between each block. Therefore, there is a problem that cracks may occur in this part depending on the conditions.

That is, as shown enlarged in FIG. 7, a cathode electrode layer 101 which is blocked in a predetermined region is vapor-deposited on a substrate 100, and an amorphous silicon layer 102 which becomes a resistance layer is formed thereon. The insulating layer 103 is formed, and niobium to be the gate electrode layer 104 is vapor-deposited on the upper surface of the insulating layer 103 to form a laminated substrate. Then, according to the Spindt manufacturing method described above, an emitter is formed and a predetermined number of field emission cathodes are constructed on the cathode electrode. However, the area L _C of the cathode electrode layer and the space L between the adjacent cathode electrodes are formed. As shown in the drawing, an uneven step is formed depending on the thickness of the cathode electrode layer 101 as shown in the drawing, and in particular, a concave depression is formed in the portion of the gate electrode layer 104 deposited on the uppermost layer.

Then, when a thin film of niobium to be a gate electrode is vapor-deposited in the depressed region, Q
When a crack occurs at the position indicated by the dot and patterning or etching to form a field emission device is performed in this state, a strain occurs due to disconnection due to etching under the crack or internal stress of the device, and each of the blocks is blocked. There is a problem that the yield becomes extremely poor as a manufacturing method in which the characteristics of the field emission device become non-uniform and uneven products frequently appear on the display surface.

[0016]

SUMMARY OF THE INVENTION The present invention has been made for the purpose of providing a field emission cathode in which the above-mentioned problems in manufacturing are solved, and for example, a plasma CVD method is provided on a substrate. To form a cathode electrode by polycrystallizing an n or p type amorphous silicon layer by annealing with a laser beam at a predetermined position of the n or p type amorphous silicon layer. A field emission cathode is formed by forming an emitter and a gate electrode on the upper surface of the silicon layer by the Spindt method.

[0017]

The n or p type amorphous silicon layer deposited on the substrate by the plasma CVD method or the like has a resistivity of 1 by being doped with phosphorus or boron, for example.
It is 0 ² to 10 ⁶ Ω / cm, and operates as a resistance layer that suppresses the current of the emitter, but when a predetermined region of this n-type or p-type amorphous silicon layer is annealed by a laser, the annealed portion is heated by thermal energy. Polycrystalline from amorphous state, its resistivity is 10 ^-1
To 10 ⁻³ Ω / cm conductor. Therefore, when the insulating layer and the gate electrode layer are vapor-deposited by using the annealed region as a cathode electrode, the laminated substrate has a flat shape and the uneven portion is eliminated, so that a field emission device having uniform characteristics can be constructed. .

[0018]

1 and 2 show a process of manufacturing a field emission cathode according to the present invention. First, a glass substrate 12 is used.
An n- or p-type amorphous silicon layer 122 doped with phosphorus is formed on one surface of No. 1 by a plasma CVD method.

[0019] The n-type Amorufu Ass silicon layer by plasma decomposition by mixing several tens of% of PH ₃ from a few percent to S _i H ₄ or Si ₂ H ₆ as the gas species, resistivity of 10 ²
The film is formed as an n-type amorphous silicon layer of 10 ⁶ Ω / cm, and serves as a resistance layer of the FEC as shown in FIG. In addition to phosphorus, arsenic (As) or the like can be mixed as the doping material. Also,
In addition to boron, gallium (G
a), indium (In), etc. can be mixed.

Then, as shown in FIG. 1B, for example, an annealing process is performed in which an excimer laser Lp (wavelength 308 nm) is irradiated to instantaneously heat a predetermined region.
Alternatively, when the laser-irradiated portion of the p-type amorphous silicon layer 122 is polycrystallized from the amorphous state, the doped phosphorus is activated and the annealed region 123 has a resistivity of 10 ⁻¹ to 10 ^−3. The conductor changes to Ω / Cm.

After the n or p type amorphous silicon layer 122 arranged on the glass substrate is annealed in this way, as shown in FIG. 1C, for example, SiO _{2 is used.}
From the above, a step of forming an insulating layer 124 and a gate electrode layer 125 made of niobium or the like and molding the FEC as shown in FIG. 6, that is, a photoresist layer by masking a predetermined position of the gate electrode layer 125. After forming 126, a hole is formed in the gate electrode layer 125 by etching (d in FIG. 1), and then Al to be the peeling layer 207 is vapor-deposited by oblique vapor deposition as shown in FIG. The insulating layer 124 is perforated by isotropic etching. Then, when an emitter material layer made of molybdenum or the like is deposited from this hole by an electron beam vapor deposition method or the like, as shown in FIG.
As shown in (f), a cone-shaped emitter 115 having a conical tip is formed on the n-type or p-type amorphous silicon layer 122. Then, thereafter, the FEC of the present invention is formed by removing the resist layer 126 and the peeling layer 127 as in the conventional manufacturing method. (Fig. 2
G)

In the field emission cathode of the present invention, a resistance layer is formed by the n or p type amorphous silicon layer 122 as described above, and laser annealing is applied to a predetermined position of the n or p type amorphous silicon layer 122. Since the doping material is activated to change into a good conductor when the n- or p-type amorphous silicon layer is polycrystallized from amorphous silicon, this conductor portion can be used as the cathode electrode region 123.
Therefore, each emitter is connected to the cathode electrode region 123 via the n-type or p-type amorphous silicon layer forming the resistance layer.

In the FEC structure of the present invention, all the layers are flat in the state of the laminated substrate, and the upper surface of the portion corresponding to the cathode electrode does not become a raised laminated state as seen in the conventional FEC. , FEC can be performed on a flat surface, and the thickness of the gate electrode and the height of the emitter can be made uniform.

The shape of the cathode electrode region 123 formed by laser annealing the resistance layer formed by the n-type or p-type amorphous silicon layer is, for example, as shown in FIG. Block 1 divided into groups of emission cathode devices 128
The pattern can be such that it surrounds 29. In the case of a display device, the shape of the cathode electrode 123 is shown in FIG.
Alternatively, the cathode electrode layer 101 may have a strip shape as shown in FIG.

By the way, when the cathode electrode is arranged on the substrate as shown in FIG. 2 (g), each emitter in the block is connected to the cathode electrode through the resistance layer made of the n-type or p-type amorphous silicon layer. The problem remains that the connected path lengths are different. Therefore, by constructing a laminated substrate as shown in FIG. 4 below, an FEC having a homogeneous resistance layer on a strip-shaped cathode electrode layer can be constructed.

That is, as shown in FIG. 4, a substrate 131 such as glass is coated with insulating amorphous silicon or polysilicon having impurities mixed therein by a sputter deposition method or a plasma CVD method to form a first film. The insulating layer 132 is formed. Then, when a predetermined range B of the first insulating layer 132 is annealed by an excimer laser or the like, a part of the layer made of amorphous silicon is crystallized and the resistivity is about 10 ⁻¹ to 10 ⁻³ Ω / cm. Conductive region 133 is crystallized. Then, as shown in FIG.
The n- or p-type amorphous silicon layer 134 is vapor-deposited on the upper surface of 3 by the low pressure CVD method, and the insulating layer 135 and the gate electrode layer 136 are formed thereon as shown in FIGS. 1 and 2.

Then, a hole is formed in the insulating layer 135 by the method described with reference to FIGS. 1 and 2, and an emitter is formed by depositing molybdenum or the like through the hole. In the case of this embodiment, this emitter is formed. 1C, a laser LP is irradiated after the insulating layer 135 is pierced, and the portion formed by the n-type or p-type amorphous silicon layer 134 is locally irradiated. Resistance region 1
Laser annealing for forming 37 is performed. Then, a part of the annealed n- or p-type amorphous silicon layer 134 is locally formed in the resistance region 1 as shown by the cross-hatched lines.
It changes to 37 and shows a resistance such that the resistivity is in the range of 10 ² to 10 ⁶ Ω / cm.

In order to realize this resistivity accurately, the n-type or p-type amorphous silicon layer 1 on the laminated substrate is formed.
A test region is provided in a partial region of 34, and while monitoring the resistance change of this test region, the time of laser annealing,
It is preferable to adjust the strength and the like. Then, after the resistance region 137 is formed by the above laser annealing, the molybdenum material is vertically deposited by electron beam evaporation as described above, and the emitter 115 is deposited in the hole of the insulating layer.

Therefore, in the case of this embodiment, FIG.
As shown in (d), a resistance region 137, which is also formed by annealing, is provided above the cathode electrode region 133 formed by annealing, and the cone-shaped emitter 115 is formed on the resistance region 137. F
It can be EC.

In this embodiment, all the emitters 115 mounted above the cathode electrode region 133 are connected to the cathode electrode region 133 through the same resistance region 137, and this cathode electrode region 133 is connected. When controlling 133 as a scanning electrode, the potential of each emitter can be kept completely the same.

In the above embodiment, the laser is irradiated from above the laminated substrate when performing the laser annealing. However, the portion which becomes the cathode electrode layer is annealed from the back side of the substrate by utilizing the transparency of the glass substrate. It can also be formed by. Therefore, in the manufacturing method shown in FIGS. 1, 2, and 4, the cathode electrode region 123 or 133 can be formed after the FEC is finally completed.

[0032]

As described above, according to the present invention, the cathode electrode formed on the glass substrate is formed by laser annealing the n-type or p-type amorphous silicon layer. When laminating, each of these layers can be processed in a flat state. Therefore, various problems caused by the swelling of the cathode electrode when forming a laminated substrate as in the related art are eliminated, and the production of a defect-free and homogeneous field emission cathode can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a first half showing a manufacturing process of a field emission cathode of the present invention.

FIG. 2 is an explanatory diagram of the latter half showing the manufacturing process of the field emission cathode of the present invention.

FIG. 3 is an explanatory diagram of a cathode electrode formed by laser annealing.

FIG. 4 is an explanatory view showing a manufacturing process of a field emission cathode showing another embodiment of the present invention.

FIG. 5 is a perspective view showing an example of an apparatus using a field emission cathode.

FIG. 6 is an explanatory view showing a conventional method for manufacturing a field emission cathode.

FIG. 7 is an enlarged cross-sectional view of the unevenness of the laminated substrate produced by the conventional manufacturing method.

[Explanation of symbols]

 121, 131 substrate 122 n-type or p-type amorphous silicon layer 123 cathode electrode region 123 insulating layer 125 gate electrode layer 115 emitter

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kazuka Otsu 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd.

Claims (3)

[Claims] 1. A plasma CVD method or a reduced pressure C on a substrate.
An n or p type amorphous silicon layer is formed by a VD method or the like, and a predetermined position of the n or p type amorphous silicon layer is polycrystallized by laser annealing to form a cathode electrode region, and the n or p type is also formed. Field emission cathode characterized in that a large number of emitters and gate electrodes are formed by an FEC manufacturing process in which at least an insulating layer and a gate electrode layer are formed on the upper surface of a type amorphous silicon layer, and predetermined positions are etched and deposited. Manufacturing method. 2. The method of manufacturing a field emission cathode according to claim 1, wherein the cathode electrode is formed so as to surround a plurality of the emitters. Wherein said n-type amorphous silicon layer is an S _i H _4, or PH ₃ to Si ₂ H ₆ as the gas species, a mixture of B ₂ H ₆ as a p-type, resistivity of 10 ² Ω / cm~ 10
^{6. The} method for producing a field emission cathode according to claim 1, wherein the field emission cathode is ⁶ Ω / cm.