JP2002093308A - Electron emission device, electron source, image forming apparatus, and manufacturing method of electron emission element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electron emission device and an electron source forming an electric field by which, a good electron emission is performed, to provide an image forming apparatus with highly defined and uniform displaying property, and to provide a manufacturing method of the electron emission device which makes the production easy. SOLUTION: As an emitted electron travels perpendicular to an equipotential surface 6, the electron emitted from an electron emission file 5 travels perpendicular to the surface of the electron emission film 5, and the proportion of collision of emitted electron at a side wall of a minute hole is reduced, and the diameter of electron beam becomes small when the emitted electron reaches an anode electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron-emitting device, an electron source using the same, an image forming apparatus, and a method for manufacturing an electron-emitting device.

[0002]

2. Description of the Related Art Conventionally, two types of electron-emitting devices, a thermionic electron-emitting device and a cold cathode electron-emitting device, are known. The cold cathode electron emitting device includes a field emission type (hereinafter, referred to as “FE type”), a metal / insulating layer / metal type (hereinafter, referred to as “MIM type”), a surface conduction type electron emitting device, and the like.

Some FE type electron-emitting devices are disclosed in
Japanese Patent Application Laid-Open Nos. -96703, 8-96704, 8-115654 and the like are known.

[0004] Examples of a configuration in which the insulating layer is composed of a plurality of layers are disclosed in JP-A-6-162919 and JP-A-6-162919.
The one disclosed in JP-A-333496 is known.

[0005]

In order to apply the above-mentioned electron-emitting device to an image forming apparatus such as a display device, it is necessary to provide an emission current for causing the phosphor to emit light with sufficient luminance.
Further, in order to increase the definition of the display device, it is necessary that the diameter of the electron beam irradiated on the phosphor is small and the electron emission characteristics are uniform. It is important that the device can be driven at a low voltage and is easy to manufacture.

However, in the above-mentioned electron-emitting device,
There were the following problems.

FIG. 17 shows an example of a hole type FE-type electron-emitting device disclosed in Japanese Patent Application Laid-Open No. Hei 8-96704.

In this example, a cathode electrode 1 is provided on a substrate 171.
The gate electrode 174 and the gate electrode 174 are stacked with an insulating layer 173 interposed therebetween, and minute holes penetrating the gate electrode 174 and the insulating layer 173 are formed, and the electron emission film 175 is provided on the bottom surface in the minute holes. An electron-emitting device.

This electron emission element emits electrons from the electron emission film 175 by applying a higher voltage to the gate electrode 174 than to the cathode electrode 172.

However, at this time, the equipotential surface formed in the minute hole has a convex shape whose central portion protrudes upward depending on the thickness of the electron emission film 175, and the inside of the surface of the electron emission film 175 The strongest electric field is applied near the side walls of the micro holes.

For this reason, electrons are mainly emitted from the vicinity of the side wall of the microhole in the surface of the electron emission film 175. Further, since the equipotential surface in the micropore has a convex shape in which the central portion protrudes, many electrons collide with the side wall of the micropore. As a result, electrons may enter the insulating layer 173, causing a problem such as discharge due to charge-up.

In addition, the emitted electrons also spread while spreading outward under the influence of such an electric field, so that the diameter of the electron beam applied to the phosphor increases.

On the other hand, Japanese Patent Application Laid-Open No.
FIG. 18 shows an example disclosed in Japanese Patent No. 162919.

This example has an emitter 185 rising in a conical shape on a conductive substrate 181, and insulating layers 182 and 183 formed in multiple layers having different dielectric constants are formed so as to surround the periphery of the emitter 185. The gate electrode 184 is stacked over the insulating layer 183, and the dielectric constant of the insulating layer 182 close to the conductive substrate 181 is set to be smaller than that of another insulating layer (such as the insulating layer 183). ing.

In this example, a plurality of insulating layers 182 and 183 having different dielectric constants are stacked, and the dielectric constant of the insulating layer 182 close to the conductive substrate 181 is smaller than that of the other insulating layers 183. The electric field intensity applied to the vicinity of the tip is larger than that of an electron-emitting device composed of only one kind of insulating layer, and the gate voltage required to obtain the same emission current can be reduced.

FIG. 19 shows another example of the FE-type electron-emitting device in which the insulating layer is composed of a plurality of layers as disclosed in Japanese Patent Application Laid-Open No. 6-333496.

In this example, the insulating substrate 1 is placed on the insulating substrate 191.
An Al ₂ O ₃ layer 196 for protecting 91 and a lower Cr layer 192 as a base electrode are laminated, and a Mo layer 195 as a long cathode layer having an edge portion is formed on a part of the layer. The upper Cr layer 194 which is a control electrode laminated on the lower Cr layer 192 via the insulating layers 193a, 193b and 193c is spaced apart from the Mo layer 195 by a sub-micron order. The structure is such that it is formed at the same height as the edge of the layer 195.

In this example, the thermal stress during heating causes Cr
In order to suppress the occurrence of cracks in the layers 192 and 194, an Al ₂ O ₃ layer is employed as the insulating layers 193a and 193c, and the insulating layer portion is formed of an Al ₂ O ₃ layer, a SiO ₂ layer, and an Al ₂ O ₃ layer. It has a three-layer structure in which layers are sequentially stacked.

These electron-emitting devices include a gate electrode 18
By applying a voltage higher than that of the conductive substrate 181 or the lower Cr layer 192 to the upper layer 4 or the upper Cr layer 194, electrons are emitted from the tip of the emitter 185 or the edge of the Mo layer 195.

However, at this time, the tip of the emitter 185 and the M
The strongest electric field is applied between the edge of the o-layer 195 and the gate electrodes 184, 194.

Therefore, a large number of electrons are transferred to the gate electrode 184.
Or the side wall of the upper Cr layer 194. As a result, a problem such as a decrease in the number of emitted electrons may occur.

In addition, the emitted electrons also propagate while spreading outward under the influence of such an electric field, so that the diameter of the electron beam applied to the phosphor increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a high-performance electron-emitting device and an electron source for forming an electric field for satisfactorily emitting electrons, and a further object. An object of the present invention is to provide an image forming apparatus having high definition and uniform display characteristics, and a method of manufacturing an electron-emitting device which can be easily manufactured.

[0024]

According to the present invention, there is provided an electron-emitting device comprising: a first electrode and a second electrode laminated on the first electrode with an insulating layer interposed therebetween; An electron emission portion provided on a bottom surface of a hole penetrating the second electrode and the insulation layer, wherein the insulation layer is composed of a plurality of layers. Preferably, the dielectric constant of the layer on the first electrode side is higher than the dielectric constant of the layer on the second electrode side.

It is preferable that the surface of the electron emitting portion is provided on the first electrode side with respect to an interface between a layer having a large dielectric constant disposed on the first electrode side and a layer laminated thereon. It is.

It is preferable that the plurality of layers constituting the insulating layer have a multilayer structure in which the dielectric constant changes continuously.

A cathode electrode on the insulating substrate and a gate electrode on the cathode electrode with an insulating layer interposed therebetween; and an electron emission film provided on the bottom surface of a hole formed through the gate electrode and the insulating layer. Wherein the insulating layer is provided in a multilayer structure in which multiple layers having different dielectric constants are stacked on the cathode electrode side.

It is preferable that the surface of the electron emission film is provided on the cathode electrode side with respect to an interface between a layer having a large dielectric constant on the cathode electrode side of the insulating layer and a layer stacked thereon. .

It is preferable that the insulating layer has a laminated structure of three or more layers, and that the dielectric constant of each layer decreases from the cathode electrode side toward the gate electrode side.

Preferably, the insulating layer has a laminated structure of three or more layers, and the dielectric constant of the layer closest to the cathode electrode and the dielectric layer of the layer closest to the gate electrode are preferably higher than the dielectric constant of a layer between them. is there.

It is preferable that the insulating layer has a multilayer structure in which the dielectric constant changes continuously.

Preferably, the insulating layer is formed by mixing two or more insulating materials having different dielectric constants.

When the dielectric constant of the insulating layer decreases from the cathode electrode side toward the gate electrode side,
It is preferable that the surface of the electron emission film is provided on the cathode side which is a region that is equal to or more than the average value of all the dielectric constants of the insulating layer.

The hole has a polygonal shape, a slit shape, a circular shape,
It is preferable to form any one of a part of a circle, an ellipse, and a part of an ellipse.

It is preferable that the electron emission film contains diamond-like carbon or diamond.

It is preferable that the hole is formed by dug a part of the cathode electrode.

The electron source according to the present invention is characterized in that a plurality of the above-mentioned electron-emitting devices are arranged in parallel and at least one row of the electron-emitting devices is connected. .

At least one or more rows of the above-mentioned electron-emitting devices each including a plurality of the above-mentioned electron-emitting devices are arranged, and a low-potential supply line and a high-potential supply line for driving the electron-emitting devices are arranged in a matrix. It is characterized by being arranged.

An image forming apparatus according to the present invention includes the above-mentioned electron source and an image forming member for forming an image by the electrons emitted from the electron source, and each electron of the electron source is transmitted by an information signal. The amount of electrons of the emission element is controlled.

Preferably, the image forming member is a phosphor.

In the method of manufacturing an electron-emitting device according to the present invention, a multi-layer structure in which a cathode electrode and a layer having a large dielectric constant are provided on the side of the cathode electrode and having different dielectric constants is stacked on an insulating substrate. A step of sequentially stacking and forming an insulating layer and a gate electrode provided in the structure, a step of forming a hole through the gate electrode and the insulating layer, and forming an electron emission film on the bottom surface of the hole And a step.

[0042]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the dimensions of the components described in this embodiment,
The materials, shapes, relative arrangements, and the like are not intended to limit the scope of the present invention only to them unless otherwise specified.

First, the main structure and effects of the electron-emitting device of the present invention will be described.

In the electron-emitting device of the present invention, a cathode electrode as a first electrode and a gate electrode as a second electrode are laminated on a substrate via an insulating layer, and minute holes penetrating the gate electrode and the insulating layer are formed. An electron-emitting device in which an electron-emitting film as an electron-emitting portion is provided on the bottom surface in the minute hole, wherein the insulating layer between the cathode electrode and the gate electrode has at least a different dielectric constant. It is composed of two or more insulating layers, and among the two or more insulating layers, the dielectric constant of the layer closest to the cathode electrode is larger than the dielectric constant of the layer laminated thereon. The configuration is as follows.

In the above-described structure of the electron-emitting device of the present invention, the equipotential surface near the surface of the electron-emitting film is formed as described in JP-A-8-9 / 1996.
As recessed below the conventional example such as 6704,
Since the electron emission film is formed in a concave shape in which the parallel or central part is depressed, the emitted electrons travel almost perpendicular to the surface of the electron emission film. The rate of collision can be reduced, and the diameter of the electron beam when the electron beam reaches the anode (phosphor) can be reduced. High definition becomes possible.

Further, since the electron-emitting device of the present invention is formed in a simple laminated structure, it is easy to manufacture, and since the structure is easy to control, the electron-emitting characteristics of each electron-emitting device should be uniform. Can be.

Since the electron-emitting device of the present invention uses the gate electrode as a modulation electrode and can apply a high voltage to the anode, the emitted electrons have sufficient energy to cause the phosphor to emit light. Because of the collision, sufficient luminance can be obtained with the phosphor.

In the electron-emitting device according to the present invention, the voltage applied between the gate electrode and the cathode electrode is reduced by reducing the thickness of the insulating layer or selecting a material having a small work function for the electron-emitting film. However, electrons can be emitted, and the element can be driven at a low voltage.

Next, specific embodiments of the electron-emitting device of the present invention will be described.

FIG. 2 is a schematic plan view showing the electron-emitting device according to the present embodiment, and FIG. 1 is a schematic cross-sectional view taken along line AA 'in FIG. 2 showing the electron-emitting device according to the present embodiment. It is.

1 is a substrate, 2 is a cathode electrode laminated on the substrate 1, 3a and 3b are insulating layers laminated on the cathode electrode 2, 4 is a gate electrode laminated on the insulating layer 3b,
Reference numeral 5 denotes an electron emission film provided on the bottom surface of the microhole penetrating the gate electrode 4 and the insulating layers 3a and 3b, respectively, and W1 denotes an opening diameter of the microhole. The dielectric constant of the insulating layer 3a on the cathode electrode 2 side is higher than the dielectric constant of the insulating layer 3b laminated thereon.

The thickness of the insulating layers 3a and 3b is appropriately set according to the material, the dielectric constant, the driving voltage, the required shape of the electron beam of the emitted electrons, and the like, and the interface between the insulating layers 3a and 3b is determined. Is smaller than the surface of the electron emission film 5 by the gate electrode 4.
Set to be on the side. That is, the insulating layer 3a and the electron emission film 5 are both formed on the substrate 1, and the thickness of the insulation layer 3a is set to be larger than the thickness of the electron emission film 5.

The thickness of the insulating layer 3a is
Although the optimum thickness differs depending on the ratio of the dielectric constant of the cathode 3b, the thickness between the cathode electrode 2 and the gate electrode 4 (the cathode electrode 2 and the gate electrode 4 including the insulating layers 3a and 3b together).
About 20 to 80% of the total thickness between them).

The opening diameter W1 of the microhole is determined by the material and dielectric constant of the electron-emitting device, the work function of the material of the electron-emitting film 5, the driving voltage between the cathode electrode 2 and the gate electrode 4, and the required emission electrons. It is set appropriately according to the shape of the electron beam.
Usually, it is set in the range of several tens nm to several tens of μm, and preferably selected in the range of several hundred nm to several μm.

FIG. 3 is a schematic sectional view showing an electric field in a minute hole formed during operation of the electron-emitting device according to the present embodiment.

Reference numeral 6 denotes an equipotential surface formed near the electron emission film 5. At this time, the cathode electrode 2 is
In this state, a higher voltage is applied.

The shape of the general equipotential surface is determined by the magnitude of the applied voltage and the thickness and width of each material forming the element. In the electron-emitting device of the present embodiment, a plurality of insulating layers 3a and 3b having different dielectric constants are laminated, and the dielectric constant of the insulating layer 3a closest to the cathode electrode 2 is set to the dielectric constant of the insulating layer 3b laminated thereon. Designed larger than.

Therefore, the equipotential surface 6 inside the insulating layer 3a is
Is wider than the interval between the equipotential surfaces inside the insulating layer 3b.

Then, in the laminated thickness region of these insulating layers 3a and 3b in the micropore, the equipotential surface passing through the inside of the insulating layer 3b is connected to the electron emitting film by the equipotential surface passing through the inside of the insulating layer 3a. As a result, when the insulating layer is a single layer, the convex equipotential surface 6 which bulges upward in the micropore is pushed down in the micropore to emit electrons. A concave shape in which a portion parallel or central to the surface of the film 5 is recessed.

FIG. 4 is a diagram showing a configuration example when operating the electron-emitting device according to the present embodiment.

Reference numeral 8 denotes an anode electrode serving as an anode for allowing emitted electrons to reach. Va is a potential difference between the cathode electrode 2 and the anode electrode 8, Vb is a potential difference between the cathode electrode 2 and the gate electrode 4, and D1 is a distance between the gate electrode 4 and the anode electrode 8.

The electrons emitted from the electron emission film 5 by the electric field formed by the potential difference Vb are attracted to the anode electrode 8 by the potential difference Va.

At this time, the electric field formed in the minute hole due to the potential difference Vb is, as shown in FIG.
In the laminated thickness region, the equipotential surface is pushed down in the micropores, so that the equipotential surface is parallel to the surface of the electron emission film 5 or has a concave shape in which the central portion is depressed.

Therefore, the electrons are transferred to the equipotential surface 6 shown in FIG.
The electrons emitted from the electron-emitting film 5 travel substantially perpendicularly to the surface of the electron-emitting film 5, and the ratio of the emitted electrons colliding with the side wall of the microhole is reduced. Further, the electron beam diameter of the electrons when the emitted electrons reach the anode electrode 8 is reduced.

Here, the thickness, width, and dielectric constant of the insulating layer of each material forming the element can be arbitrarily selected to be suitable values according to the intended use of the element.

Since the surface of the electron emitting film 5 is closer to the cathode electrode 2 than the interface between the insulating layers 3a and 3b as in the present embodiment, the equipotential surface 6 of the electric field of the above-described device emits electrons. It is possible to sufficiently obtain the effect of forming a concave shape in which the central portion is concave or parallel to the surface of the film 5.

This is because, as shown in FIG. 3, in an intermediate region of the laminated thickness of the insulating layer 3b, the equipotential surface 6 is substantially parallel to the equipotential surface in the insulating layer 3b, and This is because the equipotential surface 6 has a convex shape in which the central portion slightly protrudes in the gate electrode 4 side region having a laminated thickness.

That is, it is preferable that the surface of the electron emission film 5 be provided further on the cathode electrode 2 side.

A preferred manufacturing method of the above-described electron-emitting device of the present embodiment will be described in detail. FIG. 5 is a diagram illustrating an example of a method for manufacturing the electron-emitting device according to the present embodiment.

First, as shown in FIG. 5A, a cathode electrode 2, insulating layers 3a and 3b, and a gate electrode 4 are sequentially stacked on a substrate 1.

A quartz glass whose surface has been sufficiently cleaned in advance, a glass having a reduced content of impurities such as Na, a soda lime glass, a laminate obtained by laminating SiO ₂ on a silicon substrate or the like by sputtering or the like, a ceramic such as alumina One of the insulating substrates is used as the substrate 1 and the cathode electrode 2 is laminated on the substrate 1.

The cathode electrode 2 generally has conductivity, and is formed by a general vacuum film forming technique such as an evaporation method or a sputtering method, or a photolithography technique.

The material of the cathode electrode 2 is, for example, Be,
Mg, Ti, Zr, Hf, V, Nb, Ta, Mo, W,
Metal or alloy material such as Al, Cu, Ni, Cr, Au, Pt, Pd, TiC, ZrC, HfC, TaC, Si
Carbides such as C and WC, HfB ₂ , ZrB ₂ , LaB ₆ , C
borides such as eB ₆ , YB ₄ , GdB ₄ , TiN, ZrN,
The material is appropriately selected from nitrides such as HfN, semiconductors such as Si and Ge, and organic polymer materials.

The thickness of the cathode electrode 2 is several tens of nm.
To a few mm, preferably in the range of several hundred nm to several μm.

Next, following the cathode electrode 2, the insulating layer 3
a and 3b are deposited.

The insulating layers 3a and 3b are formed by sputtering or CVD.
(Chemical Vapor Deposition
n) It is formed by a general vacuum film forming technique such as a method and a vapor deposition method, and its thickness is set in a range of several nm to several μm, and is preferably selected from a range of several tens nm to several hundred nm. You.

Desirable materials used for the insulating layers 3a and 3b include SiO ₂ , SiN, Al ₂ O ₃ , Ta ₂ O ₅ ,
A material having a high withstand voltage that can withstand a high electric field such as CaF is desirable, and the material is selected such that the dielectric constant of the insulating layer 3a is higher than the dielectric constant of the insulating layer 3b. Further, it is preferable that the ratio difference between the dielectric constant of the insulating layer 3a and the dielectric constant of the insulating layer 3b is larger.

Further, a gate electrode 4 is deposited following the insulating layers 3a and 3b.

The gate electrode 4 has conductivity similarly to the cathode electrode 2, and is formed by a general vacuum film forming technique such as an evaporation method or a sputtering method, or a photolithography technique.

The material of the gate electrode 4 is, for example, Be, M
g, Ti, Zr, Hf, V, Nb, Ta, Mo, W, A
l, metal or alloy material such as Cu, Ni, Cr, Au, Pt, Pd, TiC, ZrC, HfC, TaC, SiC,
Carbide such as WC, HfB ₂ , ZrB ₂ , LaB ₆ , Ce
Borides such as B ₆ , YB ₄ and GdB ₄ , TiN, ZrN, H
It is appropriately selected from nitrides such as fN, semiconductors such as Si and Ge, and organic polymer materials.

The thickness of the gate electrode 4 is set in the range of several nm to several tens of μm, and is preferably selected in the range of several tens of nm to several μm.

The cathode electrode 2 and the gate electrode 4
May be the same material or different materials, and may be the same forming method or different methods.

Next, as shown in FIG. 5B, a mask pattern 7 is formed on the gate electrode 4 by a photolithography technique. The mask pattern 7 is formed except for a portion to be etched in order to form a fine hole in the next step.

Then, as shown in FIG. 5C, a minute hole penetrating the insulating layers 3a and 3b and the gate electrode 4 is formed.

However, the formation of the fine holes is performed by etching, but this etching step may be stopped on the cathode electrode 2 or a part of the cathode electrode 2 may be etched. In the etching step, an etching method may be selected according to the materials of the insulating layers 3a and 3b and the gate electrode 4 to be etched.

Subsequently, as shown in FIG. 5D, an electron emission film 5 is deposited.

The electron emission film 5 is formed by a general vacuum film forming technique such as an evaporation method and a sputtering method, and a photolithography technique.

The material of the electron emission film 5 is appropriately selected from, for example, graphite, fullerene, carbon nanotube, diamond-like carbon, carbon in which diamond is dispersed, and a carbon compound. Preferably, a diamond thin film, diamond-like carbon, or the like having a low work function is used.

The thickness of the electron emission film 5 is set in the range of several nm to several μm, preferably several nm to several hundred n.
m, and the surface of the electron emission film 5 is
It is set to be closer to the cathode electrode 2 than the interface between the a and the insulating layer 3b.

Finally, as shown in FIG. 5E, the mask pattern 7 is peeled off to complete the electron-emitting device.

FIG. 1 described so far as an example
The electron-emitting device according to the present embodiment shown in FIG. 1 has a configuration in which two insulating layers 3a and 3b having different dielectric constants are stacked as an insulating layer interposed between the cathode electrode 2 and the gate electrode 4.

However, the insulating layer interposed between the cathode electrode 2 and the gate electrode 4 may have a laminated structure composed of a plurality of three or more insulating layers having different dielectric constants. It is also possible to use a material that changes dynamically.

Further, as shown in FIG. 2, the aperture shape of the fine hole of the electron-emitting device according to the present embodiment is circular, but it is polygonal, slit-shaped, circular, part of circular, elliptical, and elliptical. It is only necessary to form any one of the shapes.

An application example using the electron-emitting device according to this embodiment will be described below. By arranging a plurality of the electron-emitting devices according to the present embodiment on a substrate, for example, an electron source or an image forming apparatus can be configured.

An electron source obtained by arranging a plurality of electron-emitting devices according to the present embodiment will be described with reference to FIG.

Reference numeral 61 denotes an electron source base; 62, an X-direction wiring;
Reference numeral 3 denotes a Y-direction wiring, 64 denotes an electron-emitting device of the present invention, and 65 denotes a connection.

The X-direction wiring 62 includes Dx1, Dx2,.
It is composed of xm wirings, and can be formed of a conductive metal or the like formed by a vacuum evaporation method, a printing method, a sputtering method, or the like. The Y-direction wiring 63 includes Dy1, Dy2,.
It is composed of n wirings yn and is formed in the same manner as the X-directional wiring 62.

An interlayer insulating layer (not shown) is provided between the m X-directional wirings 62 and the n Y-directional wirings 63 to electrically separate them. The material, thickness and width of the wiring are appropriately designed. Here, m and n are both positive integers.

The interlayer insulating layer (not shown) is made of SiO ₂ or the like formed by a vacuum deposition method, a printing method, a sputtering method, or the like. The interlayer insulating layer (not shown) includes, for example, an X-direction wiring 6.
2 is formed in a desired shape on the entire surface or a part of the substrate 61 on which the substrate 2 is formed. Is set. X direction wiring 62 and Y direction wiring 63
Are drawn out as external terminals.

A pair of electrode layers (not shown (the cathode electrode 2 and the gate electrode 4)) constituting the above-described electron-emitting device 64 according to the present embodiment are composed of m X-directional wirings 62 and n wirings. The Y-direction wiring 63 is electrically connected to a connection 65 made of a conductive metal or the like.

X direction wiring 62, Y direction wiring 63, connection 6
5 and a material constituting the pair of device electrodes may have some or all of the constituent elements which are the same or different.

These materials are appropriately selected from, for example, the materials of the cathode electrode 2 and the gate electrode 4 which are the device electrodes of the electron-emitting device 64 described above. When the material forming the element electrode is the same as the wiring material, the wiring connected to the element electrode can also be called an element electrode. Further, the device electrode can be used as a wiring electrode.

The X-direction wiring 62 is connected to a scanning signal applying means (not shown) for applying a scanning signal for selecting a row of the electron-emitting devices 64 arranged in the X-direction. On the other hand, Y
The direction wiring 63 has electron emitting elements 64 arranged in the Y direction.
(Not shown) for modulating each of the columns according to the input signal. The drive voltage applied to each electron-emitting device 64 is supplied as a difference voltage between a scanning signal and a modulation signal applied to the electron-emitting device 64.

In the electron source having the above configuration, individual electron-emitting devices 64 can be selected and driven independently by using a simple matrix wiring.

An image forming apparatus configured using such an electron source having a simple matrix arrangement will be described with reference to FIG. FIG. 7 is a schematic diagram illustrating an example of a display panel of the image forming apparatus.

Reference numeral 61 denotes an electron source substrate on which a plurality of electron-emitting devices are arranged; 71, a rear plate on which the electron source substrate 61 is fixed;
Reference numeral 6 denotes a face plate in which a fluorescent film 74 as a fluorescent material serving as an image forming member, a metal back 75, and the like are formed on the inner surface of a glass substrate 73.

A support frame 72 connects the rear plate 71 and the face plate 76 using frit glass or the like.

Reference numeral 77 denotes an envelope, for example, which is fired in air or nitrogen at a temperature in the range of 400 to 500 ° C. for 10 minutes or more to be sealed. Envelope 77
As described above, the face plate 76 and the support frame 7
2. It is composed of a rear plate 71.

Since the rear plate 71 is provided mainly for the purpose of reinforcing the strength of the base 61, if the base 61 itself has sufficient strength, the separate rear plate 71 can be omitted. That is, the support frame 7 is directly attached to the base 61.
2, the envelope 77 may be constituted by the face plate 76, the support frame 72, and the base 61.

On the other hand, by providing a support (not shown) called a spacer between the face plate 76 and the rear plate 71, the envelope 77 having sufficient strength against atmospheric pressure can be formed. .

In the image forming apparatus using the electron-emitting device according to the present embodiment, a phosphor (fluorescent film 74) is aligned above the electron-emitting device 64 in consideration of the emitted electron trajectory. .

FIG. 8 shows the fluorescent film 7 used in this display panel.
FIG. In the case of a color fluorescent film, the fluorescent film 74 is composed of a black conductive material 81 called a black stripe shown in FIG. 8A or a black matrix shown in FIG. did.

The image forming apparatus as described above can be used as a display device for a television broadcast, a display device such as a video conference system or a computer, or an image forming device as an optical printer using a photosensitive drum or the like. Can also be used.

[0114]

EXAMPLES Examples of the present embodiment will be described below in detail.

(Embodiment 1) An electron-emitting device according to this embodiment will be described with reference to FIGS. 1, 2, 4, 5, 9, and 10. FIG.

Hereinafter, the manufacturing process of the electron-emitting device of this embodiment will be described in detail with reference to FIG.

(Step 1) First, as shown in FIG. 5 (a), the substrate 1 is made of quartz and sufficiently washed, and then the cathode electrode 2 having a thickness of 5 is formed on the substrate 1 by sputtering.
00 nm of Ta was laminated.

Next, Ta (OC ₂ H ₅ ) ₅ and O ₂
Was supplied, the substrate temperature was set to 550 ° C., and Ta ₂ O ₅ having a thickness of 0 to 450 nm was laminated as the insulating layer 3a.

Thereafter, UV / O ₃ (Ultra-Vio)
(let / Ozone) annealing treatment.

Subsequently, the insulating layer 3b is formed by sputtering.
SiO with a thickness of 50 to 500 nm _Two, Gate electrode 4 and
Then, Ta having a thickness of 100 nm was deposited in this order.

(Step 2) Next, as shown in FIG. 5B, spin coating of a positive type photoresist (AZ1500 / manufactured by Clariant) and exposure of a photomask pattern on the gate electrode 4 by photolithography. Then, development was performed to form a mask pattern 7.

The mask pattern 7 is formed except for a portion to be dry-etched in order to form a fine hole in the next step.

(Step 3) Then, as shown in FIG. 5C, the insulating layers 3a and 3b and the gate electrode 4 are dry-etched using the mask pattern 7 as a mask and CF ₄ gas to form a cathode electrode 2 Then, the etching was stopped, and fine holes penetrating the insulating layers 3a and 3b and the gate electrode 4 were formed.

In the present embodiment, the opening shape of the fine hole was circular, and the opening diameter W1 shown in FIG. 2 was 0.5 μm.

(Step 4) Subsequently, FIG.
As shown in (d), a diamond-like carbon film as the electron emission film 5 was deposited to a thickness of 100 nm on the bottom surface of the fine hole. As a reaction gas, a mixed gas of CH ₄ and H ₂ was used.

(Step 5) Finally, the mask pattern 7 used as a mask was completely removed to complete the electron-emitting device of this embodiment as shown in FIG. 5 (e).

The electron-emitting device manufactured as described above was arranged as shown in FIG. 4 to emit electrons.

Here, 8 is an anode electrode, Va is a potential difference between the cathode electrode 2 and the anode electrode 8, Vb is a potential difference between the cathode electrode 2 and the gate electrode 4, and D1 is a potential difference between the gate electrode 4 and the anode electrode 8. Distance.

Electrons emitted from the electron emission film 5 by the electric field formed by the potential difference Vb are attracted to the anode electrode 8 by the potential difference Va.

In this embodiment, Va = 5 kV, D1 = 1 m
m. Using an electrode coated with a phosphor as the anode electrode 8, the electron beam diameter was observed. Here, the electron beam diameter is a size up to a region of 10% of the peak luminance of the emitted phosphor.

The relative permittivity of Ta ₂ O ₅ is about 25, and the relative permittivity of SiO ₂ is about 3.9.

FIG. 9 is a graph showing the electron beam diameter during operation with respect to the stack thickness of Ta ₂ O ₅ as the insulating layer 3a.

[0133] In this embodiment, a laminate thickness of Ta ₂ O _5, 50 nm intervals and a 0~450nm, in FIG. 9, to the thickness of the entire insulating layer, the horizontal axis laminate rate of Ta ₂ O ₅ I have to. For example, when the stack thickness of Ta ₂ O ₅ is 0,
For nm 0% of Ta ₂ O ₅ stacked rate, if the laminated thickness of the Ta ₂ O ₅ is 450nm is set to 90% of Ta ₂ O ₅ stacked rate.

In FIG. 9, the thickness of the Ta ₂ O ₅ layer is 0 nm, that is, the electron beam diameter is 100 when the SiO ₂ single layer is used as the insulating layer 3b as the insulating layer.
The electron beam diameter is plotted with respect to each layer thickness of Ta ₂ O ₅ .

From the results shown in FIG. 9, the opening diameter of the fine holes, the hole depth of the fine holes,
With structural parameters such as the film thickness of the electron emission film 5, Ta ₂ O ₅ as the insulating layer 3a is used to reduce the electron beam diameter.
It is desirable to design the lamination rate to be about 40 to 70%.

FIG. 10 is a graph showing the gate current ratio during operation with respect to the stack thickness of Ta ₂ O ₅ as the insulating layer 3a.

The gate current here is a current flowing between the gate electrode 4 and the cathode electrode 2 at the time of electron emission.
The gate current ratio is a gate current when the laminated thickness of Ta ₂ O ₅ is 0 nm, that is, when the gate current when the insulating layer is a single layer of SiO ₂ is 100. The Ta ₂ O ₅ stacking ratio on the horizontal axis is the same as in the case of FIG. 9 described above.

It is considered that the larger the gate current is, the more electrons emitted from the electron emission film 5 collide with the gate electrode 4. Therefore, the insulating layers 3 a and 3 b between the cathode electrode 2 and the gate electrode 4 are considered. It is considered that the emitted electrons are also colliding.

When the gate current flows, power consumption is increased, and the emitted electrons are generated by the insulating layers 3a, 3a.
If it collides with 3b, problems such as discharge due to charge-up of the insulating layers 3a and 3b may occur.

From the results shown in FIG. 10, the structural parameters such as the opening diameter of the fine hole, the hole depth of the fine hole, and the film thickness of the electron emitting film 5 of the electron-emitting device shown in this embodiment indicate that In order to reduce the collision of the emitted electrons to the substrate, it is desirable to design the Ta ₂ O ₅ lamination ratio as the insulating layer 3a to about 30 to 70%.

Therefore, in order to reduce the diameter of the electron beam and to reduce the collision of the electrons with the side walls of the fine holes, the T
It is desirable to design the a ₂ O ₅ stacked rate of about 40% to 70%.

(Second Embodiment) FIGS. 1, 2, 4, and 1
An electron-emitting device according to the present embodiment will be described with reference to FIGS.

In this embodiment, an example in which SiN is used for the insulating layer 3a and SiO ₂ is used for the insulating layer 3b indicates that it is preferable that the difference between the dielectric constants of the insulating layer 3a and the insulating layer 3b is large. Here, only the characteristic portions of the present embodiment will be described, and redundant description will be omitted.

After laminating the cathode electrode 2 on the substrate 1 in the same manner as in the first embodiment, SiN having a thickness of 0 to 450 nm is formed as the insulating layer 3a and SiO having a thickness of 50 to 500 nm as the insulating layer 3b by sputtering. _{2. As} the gate electrode 4, Ta having a thickness of 100 nm was deposited in this order.

Subsequently, a mask pattern 7 is formed in the same manner as in the first embodiment, the gate electrode 4 and the insulating layers 3b and 3a are dry-etched using CF ₄ gas, respectively, and the etching is stopped at the cathode electrode 2. , Opening diameter W1 = 0.
An opening of 5 μm was formed.

The following manufacturing steps are the same as in the first embodiment, and will not be described.

The electron-emitting device manufactured as described above has the same structure as that shown in FIG.
The device was driven at Vb = 10 V and D1 = 1 mm to emit electrons.

Here, the relative permittivity of SiN is about 7, and the relative permittivity of SiO ₂ is about 3.9.

FIG. 11 is a graph showing the electron beam diameter during operation with respect to the thickness of SiN as the insulating layer 3a.

In the present embodiment, the stack thickness of SiN is
It is 0 to 450 nm every 50 nm. In FIG. 11, the abscissa represents the stacking ratio of SiN with respect to the entire thickness of the insulating layer.

The lamination ratio here is the same as that described in the first embodiment.

In FIG. 11, the electron beam diameter when the laminated thickness of SiN is 0 nm, that is, when the insulating layer 3b is a single SiO ₂ layer as the insulating layer, is 100, and
The electron beam diameter is plotted for each layer thickness of SiN.

From the results shown in FIG. 11, the electron beam diameter is determined by the structural parameters such as the opening diameter of the fine holes, the hole depth of the fine holes, and the film thickness of the electron emitting film 5 of the electron-emitting device shown in this embodiment. In order to reduce the size, S as the insulating layer 3a
It is desirable to design the iN lamination ratio to about 30 to 60%.

FIG. 12 is a graph showing the gate current rate during operation with respect to the thickness of SiN as the insulating layer 3a.

The gate current ratio here is the same as that described in the first embodiment.

From the results shown in FIG. 12, the structural parameters such as the opening diameter of the micro holes, the hole depth of the micro holes, and the film thickness of the electron emitting film 5 of the electron-emitting device shown in this embodiment indicate that In order to reduce the collision of emitted electrons, it is desirable to design the SiN stacking ratio as the insulating layer 3a to be about 21 to 60%.

Therefore, in order to reduce the diameter of the electron beam and to reduce the collision of the electrons with the side walls of the fine holes, it is necessary to use S
It is desirable to design the iN lamination ratio to about 30 to 60%.

In the electron-emitting device of this embodiment, the electron beam diameter and the gate current ratio are not so much improved as compared with the first embodiment. Therefore, it is more effective that the difference in the relative permittivity between the insulating layer 3a and the insulating layer 3b is large. That is,
The larger the difference between the dielectric constants of the insulating layers 3a and 3b, the more preferable.

(Embodiment 3) An electron-emitting device according to this embodiment will be described with reference to FIGS.

In this embodiment, the insulating layer interposed between the cathode electrode 2 and the gate electrode 4 has a three-layer structure, and an insulator having a higher permittivity is sandwiched between insulators having a lower permittivity. In this case, as in the first embodiment, an example in which the effect of reducing the electron beam diameter and the effect of reducing the collision of electrons with the side wall of the microhole is obtained. Here, only the characteristic portions of the present embodiment will be described, and redundant description will be omitted.

After laminating the cathode electrode 2 on the substrate 1 in the same manner as in the first embodiment, a 250 nm thick insulating layer 3a is formed.
Ta ₂ O ₅ , 150 nm thick SiO ₂ as the insulating layer 3b
_{2. As} the insulating layer 3c, Ta ₂ O ₅ having a thickness of 100 nm was laminated in this order, and the gate electrode 4 was laminated thereon.

Subsequently, a mask pattern 7 is formed in the same manner as in the first embodiment, and the gate electrode 4 and the insulating layers 3c, 3b,
3a is dry-etched using CF ₄ gas, the etching is stopped at the cathode electrode 2, and the opening diameter W
Micropores of 1 = 0.5 μm were formed.

The following manufacturing steps are the same as in the first embodiment, and will not be described.

The electron-emitting device manufactured as described above has a structure similar to that shown in FIG.
The device was driven at Vb = 10 V and D1 = 1 mm to emit electrons.

As a result, the electron beam diameter was about 25% and the gate current ratio was about 10%, as compared with the case where a single layer of SiO ₂ was laminated as the insulating layer.

(Embodiment 4) An electron-emitting device according to this embodiment will be described with reference to FIGS.

In this embodiment, the insulating layer interposed between the cathode electrode 2 and the gate electrode 4 has a three-layer structure. In this insulating layer, the insulating layer 3a closest to the cathode electrode 2 has the highest dielectric constant, 4, the insulating layers 3b,
An example in which the effect of reducing the diameter of the electron beam and reducing the collision of electrons with the side walls of the micropores, as in the first embodiment, is obtained when the dielectric constant of 3c is gradually reduced. Here, only the characteristic portions of the present embodiment will be described, and redundant description will be omitted.

After laminating the cathode electrode 2 on the substrate 1 in the same manner as in the first embodiment, a 250 nm thick insulating layer 3a is formed.
Ta ₂ O ₅ , 150 nm thick Si as the insulating layer 3b
N, SiO ₂ having a thickness of 100 nm was laminated in this order as the insulating layer 3c, and the gate electrode 4 was laminated thereon.

Subsequently, a mask pattern 7 is formed in the same manner as in the first embodiment, and the gate electrode 4 and the insulating layers 3c, 3b,
3a is dry-etched using CF ₄ gas, the etching is stopped at the cathode electrode 2, and the opening diameter W
Micropores of 1 = 0.5 μm were formed.

The following manufacturing steps are the same as in the first embodiment, and will not be described.

The electron-emitting device manufactured as described above has a structure similar to that shown in FIG.
The device was driven at Vb = 10 V and D1 = 1 mm to emit electrons.

As a result, the electron beam diameter was about 17% and the gate current ratio was about 10%, as compared with the case where a single layer of SiO ₂ was laminated as the insulating layer.

(Fifth Embodiment) An electron-emitting device according to this embodiment will be described with reference to FIGS.

In this embodiment, when the dielectric constant of the insulating layer 3 interposed between the cathode electrode 2 and the gate electrode 4 is continuously changed so that the dielectric constant on the cathode electrode 2 side is the highest, As in the first embodiment, an example in which the effects of reducing the electron beam diameter and reducing the collision of electrons with the side walls of the micropores will be described. Here, only the characteristic portions of the present embodiment will be described, and redundant description will be omitted.

After laminating the cathode electrode 2 on the substrate 1 in the same manner as in the first embodiment, a 500 nm thick mixture of SiO ₂ and SiN was laminated as the insulating layer 3 by the dual simultaneous sputtering method. First, 200 W for SiN and 40 W for SiO ₂
The stacking was started by applying W power, the power applied to SiN was gradually reduced, the power applied to SiO ₂ was increased, and finally the power applied to SiN was cut off.

Subsequently, a mask pattern 7 is formed in the same manner as in the first embodiment, and the gate electrode 4 and the insulating layer 3 are dry-etched using CF ₄ gas, respectively. Micropores having a diameter W1 of 0.5 μm were formed.

The following manufacturing steps are the same as in the first embodiment, and will not be described.

The electron-emitting device manufactured as described above has a configuration similar to that shown in FIG.
The device was driven at Vb = 10 V and D1 = 1 mm to emit electrons.

As a result, the beam diameter was about 90% and the gate current ratio was about 80% as compared with the case where a single layer of SiO ₂ was laminated as the insulating layer.

In this embodiment, the dielectric constant of the insulating layer 3 is continuously changed so as to decrease toward the gate electrode 4, and the surface of the electron emission film 5 has a dielectric constant of the entire insulating layer 3. Is provided on the side of the cathode electrode 2 which is a region of not less than the average value of.

(Sixth Embodiment) FIGS. 4, 15, and 1
6, the electron-emitting device according to this embodiment will be described. FIG. 16 is a plan view showing an electron-emitting device according to this embodiment, and FIG.
FIG. 5 is a schematic cross-sectional view taken along line AA ′ in FIG. 16 showing the electron-emitting device according to this example.

In the present embodiment, an example is shown in which, when forming micropores by dry etching, the etching is not stopped on the cathode electrode 2 but a part of the cathode electrode 2 is etched to dig the cathode electrode 2. In addition, the opening shape of the minute holes was made into a stripe shape, and a diamond film was used as the electron emission film 5. Here, only the characteristic portions of the present embodiment will be described, and redundant description will be omitted.

After laminating the cathode electrode 2 on the substrate 1 in the same manner as in the first embodiment, a 250 nm thick insulating layer 3a is formed.
Ta ₂ O ₅ , 250 nm thick SiO ₂ as the insulating layer 3b
₂ were laminated in this order, and a gate electrode 4 was laminated thereon.

Subsequently, a mask pattern 7 is formed in the same manner as in the first embodiment, and a part of the gate electrode 4, the insulating layers 3b and 3a, and a part of the cathode electrode 2 are dry-etched using CF ₄ gas, respectively. Microscopic holes having a stripe-shaped opening shape having an opening diameter W1 = 0.5 μm and an opening width L1 = 100 μm were formed. At this time, the etching was stopped when the cathode electrode 2 was dug down by 50 nm.

Subsequently, a 100 nm diamond film was deposited as the electron emission film 5 by the CVD method.

The following manufacturing steps are the same as in the first embodiment, and will not be described.

The electron-emitting device manufactured as described above has a structure similar to that shown in FIG.
The device was driven at Vb = 10 V and D1 = 1 mm to emit electrons.

Then, as compared with the case where a single layer of SiO ₂ is laminated as an insulating layer in the electron-emitting device shown in the first embodiment,
The beam diameter was about 18%, and the gate current ratio was about 20%.

(Seventh Embodiment) First to sixth embodiments will be described with reference to FIG.
An example in which an image forming apparatus is manufactured using the electron-emitting device according to the embodiment will be described.

The electron-emitting devices were arranged in a 10 × 10 MTX shape. As for the wiring, the X-directional wiring 62 was connected to the layer of the cathode electrode 2 and the Y-directional wiring 63 was connected to the layer of the gate electrode 4 as shown in FIG.

The electron-emitting device 64 has a width of 150 μm and a height of 3 μm.
They were arranged at a pitch of 00 μm. A phosphor, which is an anode electrode, is disposed above the electron-emitting device 64 at a distance of 2 mm. A voltage of 5 kV was applied to the phosphor.

As a result, a high-definition image forming apparatus capable of matrix driving was formed.

[0193]

As described above, in the electron-emitting device according to the present invention, the insulating layer interposed between the cathode electrode and the gate electrode is formed by a layer having a different dielectric constant having a layer having a large dielectric constant on the cathode electrode side. By providing a stacked multilayer structure, the equipotential surface near the surface of the electron-emitting film in the hole is formed parallel or concave with the surface of the electron-emitting film. It is possible to reduce the proportion of the electron beam that travels substantially perpendicular to the surface of the emission film and collides with the side wall of the hole, and reduce the electron beam diameter at the time of reaching the anode.

Since the electron-emitting device of the present invention has a simple laminated structure, it can be easily manufactured and the structure can be easily controlled, so that the electron-emitting characteristics of each electron-emitting device are uniform.

In the electron-emitting device of the present invention, the gate electrode is used as a modulation electrode, and a high voltage can be applied to the anode. Therefore, the emitted electrons collide with the phosphor with sufficient energy to cause the phosphor to emit light. Therefore, a sufficient luminance can be obtained in the phosphor.

In the electron-emitting device of the present invention, the voltage applied between the gate electrode and the cathode electrode can be reduced by reducing the thickness of the insulating layer or selecting a material having a small work function as the electron-emitting film. Accordingly, the element can be driven at a low voltage.

In an electron source having a plurality of electron-emitting devices, the electron-emitting characteristics of each electron-emitting device can be obtained uniformly.

In an image forming apparatus having a plurality of electron-emitting devices, an emission current for causing a phosphor to emit light with sufficient luminance can be obtained. Further, the electron beam diameter of emitted electrons applied to the phosphor is small, and the electron emission characteristics of each element are uniform, so that high definition is possible and high performance display characteristics are obtained. Furthermore, it can be driven at a low voltage and is easy to manufacture.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a configuration of an electron-emitting device according to an embodiment.

FIG. 2 is a schematic plan view illustrating a configuration of an electron-emitting device according to an embodiment.

FIG. 3 is a schematic cross-sectional view showing a state of an electric field in a minute hole formed during operation of the electron-emitting device according to the embodiment.

FIG. 4 is a schematic cross-sectional view showing a configuration example when operating the electron-emitting device according to the embodiment.

FIG. 5 is a diagram illustrating an example of a method for manufacturing the electron-emitting device according to the embodiment.

FIG. 6 is a schematic configuration diagram showing an electron source having a simple matrix arrangement according to the embodiment.

FIG. 7 is a schematic configuration diagram showing an image forming apparatus using an electron source having a simple matrix arrangement according to the embodiment.

FIG. 8 is a diagram showing a fluorescent film used in the image forming apparatus according to the embodiment.

FIG. 9 is a graph showing an electron beam diameter with respect to a Ta ₂ O ₅ stacking ratio of the electron-emitting device according to the first embodiment.

FIG. 10 shows Ta ₂ O _{5 of the} electron-emitting device according to the first embodiment.
It is a graph which shows the gate current rate with respect to the lamination rate.

FIG. 11 is a graph showing an electron beam diameter with respect to a SiN stacking ratio of the electron-emitting device according to the second embodiment.

FIG. 12 is a graph showing a gate current ratio with respect to a SiN stacking ratio of the electron-emitting device according to the second example.

FIG. 13 is a schematic sectional view showing an electron-emitting device according to a third and a fourth embodiment.

FIG. 14 is a schematic sectional view showing an electron-emitting device according to a fifth embodiment.

FIG. 15 is a schematic sectional view showing an electron-emitting device according to a sixth embodiment.

FIG. 16 is a schematic plan view showing an electron-emitting device according to a sixth embodiment.

FIG. 17 is a schematic cross-sectional view showing an example of a conventional hole-type FE electron-emitting device.

FIG. 18 is a schematic cross-sectional view showing an example of a conventional FE-type electron-emitting device in which an insulating layer is composed of a plurality of layers.

FIG. 19 is a schematic cross-sectional view showing an example of a conventional FE-type electron-emitting device having a configuration in which an insulating layer is composed of a plurality of layers.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Cathode electrode 3, 3a, 3b, 3c Insulating layer 4 Gate electrode 5 Electron emission film 6 Equipotential surface 7 Mask pattern 8 Anode electrode 61 Electron source substrate 62 X direction wiring 63 Y direction wiring 64 Electron emitting element 65 Connection 71 Rear plate 72 Support frame 73 Glass substrate 74 Fluorescent film 75 Metal back 76 Face plate 77 Enclosure 81 Black conductive material 82 Phosphor

Claims (18)

[Claims] A first electrode, a second electrode laminated on the first electrode with an insulating layer interposed therebetween, and an electron emitting portion provided on a bottom surface of a hole passing through the second electrode and the insulating layer. Wherein the insulating layer is composed of a plurality of layers, and the dielectric constant of the layer on the first electrode side of the plurality of layers is the dielectric constant of the layer on the second electrode side. An electron-emitting device characterized by being higher than the rate. 2. The method according to claim 1, wherein the surface of the electron-emitting portion is provided closer to the first electrode than an interface between a layer having a large dielectric constant disposed on the first electrode and a layer laminated thereon. The electron-emitting device according to claim 1, wherein: 3. The electron-emitting device according to claim 1, wherein the plurality of layers constituting the insulating layer have a multilayer structure in which the dielectric constant changes continuously. 4. A gate electrode on said cathode electrode interposing a cathode electrode and an insulating layer on an insulating substrate, and electrons provided on the bottom surface of a hole formed through said gate electrode and said insulating layer. An electron emission element comprising: an emission film; and wherein the insulating layer is provided in a multilayer structure in which multiple layers having different dielectric constants are stacked on each other with a layer having a large dielectric constant on the cathode electrode side. Electron emitting device. 5. The electron emission film according to claim 1, wherein a surface of said electron emission film is provided closer to said cathode electrode than an interface between a layer having a large dielectric constant on said cathode electrode side of said insulating layer and a layer stacked thereon. The electron-emitting device according to claim 4, wherein 6. The insulating layer according to claim 4, wherein the insulating layer has a laminated structure of three or more layers, and the dielectric constant of each layer decreases from the cathode electrode side to the gate electrode side. 3. The electron-emitting device according to item 1. 7. The insulating layer has a laminated structure of three or more layers, and a dielectric constant of a layer closest to the cathode electrode and a dielectric layer of a layer closest to the gate electrode are larger than a dielectric constant of a layer between them. The electron-emitting device according to claim 4 or 5, wherein 8. The electron-emitting device according to claim 6, wherein the insulating layer has a multilayer structure in which the dielectric constant changes continuously. 9. The electron-emitting device according to claim 8, wherein said insulating layer is formed by mixing two or more insulating materials having different dielectric constants. 10. When the dielectric constant of the insulating layer decreases from the side of the cathode electrode toward the side of the gate electrode, the surface of the electron emission film is equal to or more than the average of all the dielectric constants of the insulating layer. The electron-emitting device according to claim 8, wherein the electron-emitting device is provided on the side of the cathode which is a region of (b). 11. The method according to claim 4, wherein said hole has a shape of any one of a polygon, a slit, a circle, a part of a circle, an ellipse, and a part of an ellipse. The electron-emitting device according to any one of the above. 12. The electron-emitting device according to claim 4, wherein said electron-emitting film contains diamond-like carbon or diamond. 13. The hole according to claim 4, wherein the hole is formed by dug a part of the cathode electrode.
The electron-emitting device according to any one of the above. 14. An electron-emitting device according to claim 1, wherein a plurality of the electron-emitting devices are arranged in parallel, and at least one row of the electron-emitting devices is connected. Characterized electron source. 15. A device for driving the electron-emitting device, comprising at least one column of the electron-emitting device comprising a plurality of the electron-emitting devices according to claim 1 arranged therein. An electron source, wherein a potential supply wiring and a high potential supply wiring are arranged in a matrix. 16. An electron source according to claim 14, further comprising: an image forming member for forming an image by electrons emitted from said electron source; An image forming apparatus for controlling an amount of electrons. 17. The image forming apparatus according to claim 16, wherein said image forming member is a phosphor. 18. An insulating layer provided on a insulating substrate in a multilayer structure in which a cathode electrode and a layer having a large dielectric constant on the cathode electrode side are stacked in multiple layers having different dielectric constants.
A step of forming a hole through the gate electrode and the insulating layer; and a step of forming an electron emission film on the bottom surface of the hole. A method for manufacturing an electron-emitting device.