JPH07202212A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a thin-film transistor with good electrical characteristics, by forming a channel region with a large grain size in crystal. CONSTITUTION:A manufacturing method comprises a step for forming an amorphous silicon film 12 on an insulating substrate 11, a step for forming a gate insulating film 13 on the amorphous silicon 12, a step for forming a gate electrode 14 on the gate insulating film 13, a step for implanting an impurity in a region around the gate electrode 14 in the amorphous silicon film 12 and forming a source/drain region 16, a step for crystallizing the source/drain region 16 selectively through first heat treatment with a laser beam, and a step for crystallizing the amorphous silicon film 12 in a channel region under the gate electrode 14, with the crystallized source/drain region 16 as a kernel crystal, through second heat treatment for heating the substrate 11 in N2 atmosphere.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly to improvement of a method of manufacturing a top gate type thin film transistor.

[0002]

2. Description of the Related Art A display device using electroluminescence, a light emitting diode, plasma, liquid crystal or the like can have a thin display portion. Therefore, a terminal display device for measuring equipment, office equipment, computers, etc., Alternatively, there is an increasing demand for use as a special display device. Among these, in recent years, an active matrix type liquid crystal display device using a thin film transistor (TFT) as a switching element has been receiving attention.

In such a liquid crystal display device, generally, when the screen becomes a large screen having a diagonal of 10 inches or more, a TFT-LCD is produced using a glass substrate to suppress an increase in production cost. Therefore, an amorphous silicon film that can be formed at a low temperature is used as the active layer of the TFT.

FIG. 5 shows a conventional polycrystalline silicon film TFT.
FIG. 6 is a process cross-sectional view showing the manufacturing method of.

First, as shown in FIG. 5A, an amorphous silicon film 52 is formed on an insulating substrate 51.

Next, as shown in FIG. 5B, the amorphous silicon film 52 is crystallized by heat treatment to form a crystallized silicon film 53. At this point, the crystallization of the active layer is completed.

Next, as shown in FIG. 5C, after patterning the crystallized silicon film 53 into a predetermined shape, a gate insulating film 54 is deposited on the entire surface. Then, after depositing a conductive film 55 to be a gate electrode on the gate insulating film 54, a photoresist pattern 56 for forming a gate electrode is formed on the conductive film 55.

Next, as shown in FIG. 5D, the conductive film 55 is etched using the photoresist pattern 56 as a mask to form a gate electrode 55. Then the gate electrode 5
5, using the photoresist pattern 56 as a mask, P
Ion implantation of (phosphorus) is performed to form source / drain regions 57 in a self-aligned manner.

The term "source / drain region" is used here because the source region and the drain region cannot be distinguished unless they are incorporated in an actual device. In addition, even if incorporated in a device, the source region and the drain region may be switched depending on the usage state.

Next, as shown in FIG. 5E, after removing the photoresist pattern 56, a source / drain region 57a in which P is activated is formed by irradiation with a laser beam. Although the crystalline state of the source / drain region is destroyed by the ion implantation, the laser beam irradiation causes recrystallization to return to the original crystalline state.

Next, as shown in FIG. 5F, after depositing an interlayer insulating film 59 on the entire surface, the interlayer insulating film 59 is etched to open contact holes for the source / drain regions 57.

Finally, after depositing an Al film on the entire surface, the Al film is patterned to form the source / drain electrodes 60, and the basic structure of the TFT is completed.

However, such a conventional method for manufacturing a TFT has the following problems.

That is, the T created according to the above method
Although the active layer 53 of the FT is a crystallized silicon film, it has a problem that the crystal grain size is small overall, the mobility of carriers is low, and a TFT having a high operation speed cannot be obtained. Moreover, the arrangement of the crystal grains is also non-uniform, and there is a problem that a TFT having uniform characteristics cannot be obtained.

Further, there is a problem that a crystal defect exists near the boundary between the source / drain region 57 and the active layer 53, and the leak current increases.

[0016]

As described above, the conventional method of manufacturing a thin film transistor has a problem that an active layer (channel region) having large crystal grains cannot be formed and a thin film transistor having a high operating speed cannot be obtained. .

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a method of manufacturing a thin film transistor capable of increasing the crystal grains in the channel region.

[0018]

In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention comprises a step of forming an amorphous semiconductor film on an insulating substrate, and a step of forming the amorphous semiconductor film on the amorphous semiconductor film. Forming a gate insulating film on the gate insulating film, forming a gate electrode on the gate insulating film, and introducing impurities into a portion of the amorphous semiconductor film outside the gate electrode to form a source / drain region. A step of selectively crystallizing the source / drain regions by a first heat treatment with an energy beam, and a second heat treatment by heating the substrate.
And a step of crystallizing the amorphous semiconductor film as a channel region under the gate electrode by using the drain region as a seed crystal.

[0019]

According to the present invention, after the source / drain regions are crystallized, the amorphous semiconductor film in the channel region below the gate electrode is crystallized. Crystallization proceeds using the impurity region as a seed crystal.

Therefore, it becomes possible to form a channel region having large crystal grains having a uniform size in the channel direction.

[0021]

Embodiments will be described below with reference to the drawings.

FIG. 1 is a process sectional view showing a method of manufacturing a thin film transistor according to an embodiment of the present invention.

First, as shown in FIG. 1A, an amorphous silicon film 12 having a thickness of 50 nm is formed on an insulating substrate 11.
Are formed by a plasma CVD method.

Next, as shown in FIG. 1B, after patterning the amorphous silicon film 12 into a predetermined shape,
A gate insulating film 13 made of silicon oxide and having a thickness of 70 nm is formed on the entire surface by plasma CVD.

Then, a silicon film containing P (phosphorus) to be a gate electrode is formed on the gate insulating film 13 by a plasma CVD method. After that, a resist pattern 15 for forming a gate electrode is formed on the silicon film, and the silicon film is etched using this as a mask to form the gate electrode 14.

Next, as shown in FIG. 1C, P (phosphorus) is introduced by an ion doping method using a phosphine gas and a hydrogen gas with the gate electrode 14 and the resist pattern 15 as a mask, and the self The source / drain regions 16 are formed in a consistent manner.

Next, as shown in FIG. 1D, after removing the resist pattern 15, 450 ° C. in a nitrogen atmosphere,
Heat treatment is performed for 1 hour. Then, the excimer laser is irradiated from above the insulating substrate 11 (first heat treatment).

As a result, P introduced by the ion doping method is activated, and source / drain regions 16a in which amorphous silicon is crystallized are obtained.

Next, as shown in FIG. 1 (e), the substrate is heated by heat treatment at 600 ° C. for 8 hours in a nitrogen atmosphere (second
Heat treatment) to crystallize the amorphous silicon film 12 below the gate electrode 14 to form an active layer 17 of a crystallized silicon film.

Here, 600 ° C. was selected as the heat treatment temperature, but 400 ° C. or more and 1200 ° C. or less is preferable, and 500 ° C. or more and 700 ° C. or less is preferable.

Next, as shown in FIG. 1F, a 600 nm thick silicon oxide film as an interlayer insulating film 18 is formed on the entire surface by a thermal CVD method, and then the interlayer insulating film 18 is etched to form a source. A contact hole for the drain region 16 is opened.

Next, after depositing an Al film on the entire surface by sputtering, the Al film is patterned and the source / drain electrodes 19 are formed to complete the basic structure of the TFT.

Thereafter, for example, the following post-processing is performed.

First, after heat treatment at 450 ° C. for 30 minutes, hydrogen plasma treatment is performed using a parallel plate type plasma device. The conditions of this hydrogen plasma treatment are, for example, a substrate temperature of 350, a treatment time of 30 minutes, and a hydrogen gas pressure of 1 Tor.
r, and discharge power density is 200 mW / cm ² . Next, after hydrogen treatment, 250 ° C. and 30 ° C. in a nitrogen atmosphere.
Heat treatment for minutes.

FIG. 2 shows the current-voltage characteristics of the TFT of the present invention manufactured according to the method of this embodiment and that of the conventional method.

It can be seen from FIG. 2 that the leakage current of the TFT of the present invention (in this case, the current when the voltage is -5 V) is about one digit lower than that of the conventional one.

FIG. 3 shows the mobility distributions of 20 TFTs of the present invention manufactured according to the method of this embodiment and those of the conventional method.

It can be seen from FIG. 3 that in the case of the present invention, the mobility value is concentrated at about 120 (cm ² / V · s), but in the conventional case, the mobility value varies. Moreover, it is understood that the mobility distribution of the TFT of the present invention is located on the higher mobility side than that of the conventional one.

FIG. 4 shows the crystal structures of the active layer (channel region) and the source / drain regions of the TFT of the present invention produced according to the method of this embodiment, and those of the conventional method.

In the case of the present invention, as shown in FIG.
It can be seen that the crystal grain size of the channel region is large and the crystal grain sizes are uniform in the channel direction.

On the other hand, in the case of the conventional method, as shown in FIG. 4 (b), it can be seen that the crystal grain size of the channel region varies and the crystal grain size is disordered in the channel direction.

The reason why such a difference occurs is considered as follows.

That is, in the case of the conventional method, since the entire amorphous silicon film is first crystallized, there is no specific seed crystal when recrystallizing the channel region, so that the crystal grain size of the channel region is large. Not, and
It becomes a disorderly arrangement.

Therefore, the mobility becomes small, and
The problem arises that the characteristics of individual TFTs vary.

Since the source / drain regions are formed by crystallizing the entire amorphous silicon film and then introducing impurities, a large number of crystal defects exist near the boundary between the source / drain region and the channel region. Come to do.

Therefore, there arises a problem that the junction characteristics between the source / drain region and the channel region are deteriorated.

On the other hand, in the case of the present invention, first, the amorphous silicon film in the source / drain regions is selectively crystallized, and then the amorphous silicon film in the channel region is crystallized. Crystal growth occurs toward the channel region using the drain region as a seed crystal.

Therefore, in the channel region, crystals with a large grain size (1 μm or more) grow in the direction in which the current flows, that is, the direction in which the source and drain are connected by a straight line.
The crystal grain sizes are made uniform in the channel direction, and the mobility of electrons and holes in the channel region is improved.

Since the channel region is crystallized by heat treatment after introducing impurities into the channel region, a large amount of crystal defects does not occur near the boundary between the source / drain region and the channel region.

Therefore, the junction characteristics between the source / drain region and the channel region are improved, and the leak current at the time of off is reduced.

Thus, according to this embodiment, since the amorphous silicon film in the source / drain region is selectively crystallized and then the amorphous silicon film in the channel region is crystallized, a large crystal having a uniform size in the channel direction is formed. Grains can be formed in the channel region, and a TFT having high mobility and less variation in characteristics can be obtained.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the copra type T
Although the case of FT has been described, the present invention is a forward stagger type T
It can also be applied to FT.

Further, an amorphous semiconductor film other than the amorphous silicon film may be used.

Besides, various modifications can be made without departing from the scope of the present invention.

[0055]

As described above in detail, according to the present invention, it is possible to form a channel region made of a crystallized semiconductor having large crystal grains having a uniform size in the channel direction, so that it is possible to improve the variation in mobility and characteristics. Like

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing current-voltage characteristics of the TFT of the present invention and conventional ones.

FIG. 3 is a diagram showing a mobility distribution of the TFT of the present invention and a conventional mobility distribution.

FIG. 4 shows the channel region and source of the TFT of the present invention.
Diagram showing the crystal structure of the drain region and that of the conventional method

FIG. 5 is a process sectional view showing a conventional method for manufacturing a TFT.

[Explanation of symbols]

 11 ... Insulating substrate 12 ... Amorphous silicon film 13 ... Gate insulating film 14 ... Gate electrode 15 ... Resist pattern 16 ... Source / drain region 17 ... Active layer (channel region) 18 ... Interlayer insulating film 19 ... Source / drain electrode

Claims (1)

[Claims] 1. A step of forming an amorphous semiconductor film on an insulating substrate, a step of forming a gate insulating film on the amorphous semiconductor film, and a step of forming a gate electrode on the gate insulating film. And a step of forming a source / drain region by introducing an impurity into a portion of the amorphous semiconductor film outside the gate electrode, and selecting the source / drain region by a first heat treatment with an energy beam. And the second heat treatment by heating the substrate to form the crystallized source / drain regions as seed crystals to crystallize the amorphous semiconductor film as the channel region below the gate electrode. A method of manufacturing a thin film transistor, comprising: