JPH04506435A - Cold cathode field emission device controlling or integrally having a non-field emission device controlled - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Cold cathode field emission with integrally controlled or controlled non-field emission device device Industrial applications The present invention generally relates to cold cathode field emission devices.

Background technology Semiconductor cold field emission devices (FEDs) are known.

In such devices, electron emission occurs at the cold cathode. This technology has high expectations have the benefit of

The prior art teaches that one cold cathode field emission device is arranged integrally and For example, it is possible to support a current that carries a charge commensurate with the capacity. It is possible to anticipate this.

Many problems exist in realizing such devices. For example, one of them is Non-integral control of the FEDs must be provided and that the FEDs are and/or must control non-integrally controlled devices. One or the other must be satisfied. (In the present invention, the FED and other structures are integrated into one Mounted in an integrated structure is called "integral". For example, it is a deposit (d) used to construct an integrated circuit. epos i t 1 on) and a diffusion process. ) Furthermore, FE Conventional techniques for forming Ds include, for example, dry etching processes and non-semiconductor materials. deposition processes that use integrated controls or controlled devices. It is not particularly effective for forming chairs at the same time.

Therefore, both integral control and controlled active devices for FEDs or or a method of forming one or the other, and the resulting device is desired. ing.

Summary of the invention The above and other objects are achieved by the methods and devices disclosed in the present invention. Ru. According to the present invention, it is constructed from a cold cathode emission device and a non-field emission active device. Non-field emission active devices are cold cathode field emission devices. Cold cathode field emission devices and non-field emission active devices are integrally formed with the device. The devices are operatively coupled to each other.

In some embodiments of the invention, the non-field emission active device is a bipolar transistor. It is possible to form it so that it is. In other embodiments, non-field emission active The device can be formed to be a field effect transistor.

In some embodiments of the invention, FEDs can be configured to control non-FEDs. It is Noh. and in another embodiment, the FED is controlled by a non-FED. It is possible to form.

When modifying embodiments of the invention, non-FEDs may be modified by changing the layers that make up the FED. The layer may also include the base wafer itself. FEDs Various embodiments can be formed with such non-FEDs, Planar structure (the various electrodes that make up the FED are arranged almost planarly with respect to each other) ), non-planar FEDs (e.g., the electrodes that make up the FED are almost non-uniform with each other) the emitter is often assumed to be conical), and and inverted (inve r t ed) FED structures (e.g., whose emitters are Not formed on the wafer. )including. This invention can be applied to various products standalone devices, integrated devices, arrays, and flat screen displays.　″ In other embodiments of the invention, at least some layers of the FED are amorphous. or polysilicon semiconductor material, and non-FED devices have a It is formed. The above materials can also be used as electrodes in FEDs.

The successful results obtained by various embodiments of the present invention are demonstrated by the onboard d) Low voltage control of current source arrangement, parallel switching of low power and high speed devices , constructed by combining technologies where each technology contributes appropriately to a specific application. devices and onboard matrix address on flat panel display. Thing.

including.

Brief description of the drawing Figure IA shows a bipolar transistor formed to control the gate of an FED. It is a circuit diagram; Figures IB-A are cross-sectional views of an embodiment implementing the circuit described in Figure IA; Figure 2A is a circuit diagram of a field effect transistor formed to control the gate of an FED. is; 2B-H are cross-sectional views of embodiments implementing the circuit described in FIG. 2A: Figure 3A is a schematic diagram of a bipolar transistor coupled to the emitter of an FED. Ru; 3B-D are cross-sectional views of embodiments implementing the circuit described in FIG. 3A; FIG. 4A is a circuit diagram of a field effect transistor coupled to the emitter of an FED; 4B-D are cross-sectional views of embodiments implementing the circuit described in FIG. 4A; Figure 5 shows multiple bipolar transistors formed to control multiple FEDs. FIG. 6 is a circuit diagram of a transistor formed to control multiple FEDs. Here is a circuit diagram of several field effect transistors: FIG. 7A is a schematic diagram of an FED coupled to the base of a bipolar transistor. ; 7B-D are cross-sectional views of embodiments implementing the circuit described in FIG. 7A; Figure 8A is a circuit diagram of an FED that couples the emitters of bipolar transistors. Ru; 8B-C are cross-sectional views of embodiments implementing the circuit described in FIG. 8A; FIG. 9A is a circuit diagram of an FED coupled to the gate of a field effect transistor; 9B-C are cross-sectional views of embodiments implementing the circuit described in FIG. 9A; FIG. 10A is a circuit of an FED coupled to the source of a field effect transistor: 10B-D are cross-sectional views of embodiments implementing the circuit described in FIG. 1OA. Ru: FIG. 11A shows an FED circuit coupled to the bases of multiple bipolar transistors. It is a road map; FIG. 11B shows an FED coupled to the emitters of multiple bipolar transistors. It is a circuit diagram; FIG. 12A is a circuit diagram of an FED coupled to the gates of multiple field effect transistors. is; FIG. 12B is a circuit diagram of an FED coupled to the sources of multiple field effect transistors. It is.

of for.

Bipolar transistor vs. FED gate layout diagram IA shows the bipolar transistor A gate 101 is coupled to a gate 103 of an FED 104 via its collector 102. 1 is a diagram illustrating a circuit 100. The other terminals shown here are are connected in an appropriate manner depending on the intended use of the circuit. For example, collector Another terminal 106 can be coupled to 102 in a known manner. This way With this configuration, the bipolar transistor 101 performs gate modulation of the FED 104. can be controlled.

FIG. IB is a first embodiment 1001 for implementing the circuit illustrated in FIG. IA.

In this embodiment 101', the FED 104 has a non-planar structure. corn The emitter 107 is formed on or in a semiconductor substrate 108 such as a silicon wafer. It will be done. A gate 103 is deposited on top of the insulating layer 109. Emitter 107 And the gate 103 is made of a metal material or a semiconductor material. these The detailed manufacturing method of the device is well known in the technical field. Therefore, the explanation will be omitted. Also, although not shown here to simplify the drawing, FED 104 also has an anode electrode.

In this embodiment 1001, the bipolar transistor 101 has a substrate material 108. is formed within. In particular, well-known semiconductor manufacturing techniques, deposition, etching Using doping, doping and diffusion techniques, the bipolar transistor 101 has a collector 1 02, a base 111 and an emitter 112. suitable metal depot A conductive path 113 is formed by the switch, and the collector 102 is connected to the FED l04. Coupled to gate 103. Furthermore, other metal depositions 114, 116 This forms a conductive path to the emitter 112 and base 111.

With this configuration, it is possible to use well-known semiconductor material processing methods to The polar transistor 101 and the FED 104 are placed on the same substrate 108 or It can be formed integrally inside.

The IC in the figure has a configuration in which the collector of a bipolar transistor and the gate of an FED are connected. This is a second example 1002. Also in this embodiment, the bipolar transistor 1 01 is formed in a semiconductor wafer 108, and includes a collector 102, a base 111 and and an emitter 112.

Emitter 112 and base are separated by metal deposition regions 114 and 116, respectively. Wiring is being done to the ground 116.

However, in this embodiment 1002, the FED 104 has a substantially flat structure. (Brehner structure). Such a structure has been proposed, for example, by Lee et al. No. 4,827,177, and invented by Kane et al. U.S. Patent Application No. 07/330,050, filed March 29, 1989 It is disclosed in No specific configuration is required for the FED104. , whose gate is here connected to the bipolar transistor 10 by means of a conducting path 117. 1 collector 102. FEDl04 is generally emitter 1 It has a gate that has the function of modulating the emission of electrons from 18, and the emitter is It is formed on the insulating layer 119. Although not shown here, the element is It also has a code. Figure ID is the third embodiment 1 of this bipolar FED configuration circuit. It is 003. In this embodiment, the FED IO4 is placed on the support substrate 121. It includes a formed anode metal layer 122. Here, the support substrate 121 is made of a semiconductor material. It may or may not be formed from. The insulating layer 123 and the anode 122 It is separated from the gate 103. In this embodiment, game) 103 is a pie port. In order to facilitate the formation of the transistor 101, it may be formed from a semiconductor material. It is possible. This will be explained in more detail below. Another insulator layer 124 separates gate layer 103 and emitter 126. Of course, in the appropriate field of application In order to achieve the desired electron emission characteristics, the FED 104 is sealed in a vacuum state. Ru. (For a more detailed explanation of inverted FED construction and fabrication, see Kane Therefore, it was invented on September 29, 1989 as "a Flat Panel Dis". name of “play Using Field Emission Devices” No. 07/414,836, filed in US Pat. ) The gate layer 103 made of a semiconductor material is a bipolar transistor formed by the method described above. It is necessary for forming the resistor 101. In this embodiment 1003, the gate layer 1 03 itself functions as the collector 102 of the bipolar transistor 101. There is. Therefore, collector 102 and gate 103 are not integrally combined. It is.

Figure IE shows the fourth implementation of the structure combining the bipolar collector and the FED gate. This is example 1004. In this embodiment, the bipolar transistor 101 is shown in FIG. Similar to the embodiment, it is formed in the gate layer 103. bipolar transistors The collector 102 of the FED 101 and the gate 103 of the FED 104 are made of the same material. It is configured.

However, in this embodiment, F The ED 104 consists of a non-planar structure with a cone-shaped emitter 127. Ru. Such a cone-shaped emitter 127 is a metal layer formed on the substrate layer 121. (not shown) or directly on substrate layer 121 as shown. It may be formed in contact. The insulating layer 128 is connected to the gate 103 and the metal layer 132 or the substrate. The layers 121 are separated from each other. The second insulating layer 129 forms the gate 103 and the emitter. 127 is separated from the anode 131. with a cone-shaped emitter like this A more detailed explanation of the formation of FEDs is given, for example, in Brodie. No. 4,721,885 and invented by Goronkin et al. On February 9, 1990 a Non-Planar Field Emission Device Having an Emitter Formed Wit h a Substantially Normal Vapor Deposit It is stated in the specification of the application filed under the name “Process”. .

Figure IF shows a configuration in which the collector of the bipolar transistor is connected to the gate of the FED. This is the fifth example 1005. In this embodiment, the FED 104 is As explained above, it has a non-planar structure.

However, in this embodiment, the anode is not shown for the purpose of simplifying the drawing.

In this embodiment, the bipolar transistor 101 is made of amorphous silicon (or (polysilicon) in a layer 134 of semiconductor material. Here, the semiconductor material Layer 134 is formed on a two-part layer consisting of FED gate 103 and insulating material 133. will be accomplished. The amorphous silicon 134 is the collector 1 of the bipolar transistor 101. Contains 02. This amorphous silicon layer 134 is the gate layer 1 of the FED 104. In contact with 03. Therefore, in this embodiment as well, the bipolar transistor The collector 102 of 101 is integrally coupled to the gate 103 of FED 104 .

Figure 1G shows a configuration in which the collector of the bipolar transistor is connected to the gate of the FED. This is a sixth embodiment 100'. In this example, the FED 104 is shown in Figure IF. It has the same structure as the FED. However, in this embodiment, the gate layer 1 03 is formed from an amorphous silicon (or polysilicon) semiconductor material.

As for the other bipolar transistors 101, the bipolar transistor 101 is The collector 102 of the transistor 101 and the gate 103 of the FED 104 are common. It is made of materials.

Figure IH shows a configuration in which the collector of the bipolar transistor is connected to the gate of the FED. This is a seventh embodiment 100'. In this embodiment, the FED 104 is explained in Figure ID. It consists of an inverted emitter structure like the one shown below.

However, in this embodiment, the bipolar transistor 101 is made of amorphous silicon. A layer 134 of silicon (or polysilicon) semiconductor material is formed. semiconductor here The layer of material 134 is substantially planar with the emitter 126 of the FED 104. ). Suitable metal deposition area 136 By using the amorphous material 134, that is, the bipolar transistor 1 The collector 102 of 01 is coupled to the gate 103 of FED 104. this special In the embodiment, at least the electrodes 114 and 116 of the bipolar transistor 101 are It has the advantage that it can be formed substantially outside the partial structure. This allows these electrodes 114, 116 can be easily combined according to a particular application.

Figure 1 shows a configuration in which the collector of the bipolar transistor is connected to the gate of the FED. This is the eighth example 1008. In this embodiment, the FED 104 is the same as in Figure IE. This is a non-planar FED with a cone-shaped emitter as described in . Main implementation In the example, the bipolar transistor 101 is further illustrated in FIG. The collector 1 of the bipolar transistor 101 02 is connected to the gate 103 of FEDl 04 through an appropriate metal wiring layer 136. be combined.

Field effect transistor for FET gate shape Figure 2A is a field effect transistor A conceptual block diagram 200 of a FET 201 is shown, and the FE Coupled to gate 103 of T104. The electrodes 202 of the FET are described in detail below. It may be either the source or the drain, as shown in FIG. This shape is bipo Despite using FET technology as well as for Provides the same control capabilities as described above with respect to the figures.

FIG. 2B shows a first embodiment 2001 of the FET electrode for the FET gate shape. . In this embodiment 2001, FET 104 is as described above with respect to FIG. 1B. It can be configured in the same way as . However, in this embodiment, the semiconductor Substrate 108 connects FET drain 202 and source through known methods. 203 is formed therein. The gate 204 of the FET is made of a metal material in a known manner. Formed on insulating layer 206 through the deposition of material 205 . The metal conductive band 207 is The metal evaporation layer 208 is then deposited on the transistor 201 (FET). Drain 202 is coupled to gate 103 of FET 104.

FIG. 2C shows a second embodiment 2002 of the FET electrode for the FET gate shape.

In this embodiment, FET IO4 is substantially as described above in FIG. 1C. It consists of a planar structure. However, in this embodiment, the semiconductor substrate 1 08 forms the drain 202 and source 203 of the FET 201 in the substrate. Ru. A particular gate 204 is formed by depositing an insulating layer 206 and a metal contact 205. will be accomplished. Drain 202 and FET gate 103 are extensions from gate 103 417 to each other.

FIG. 2D shows a third embodiment 200'' of FET electrodes for FET gate geometries.

In this embodiment, FET 104 has the opposite structure as described above for the first D flash. It is expressed as. However, in this example, for FET 104 The gate layer 103 is divided into two parts to include the semiconductor layer 209, and F The source 2.3 and drain 202 of ET 201 are formed. FET gate 2 o4 is realized by the conductor 205 deposited on the insulating layer 206, as described above. Similarly, the source 203 has a metal layer 207 deposited thereon and a conductive conductor thereon. provide a route. Finally, the drain 202 has a specific conductive path 208 that It is formed between the electric path and the FET gate o3.

FIG. 2E shows a fourth embodiment 200' of the FET electrode for the FET gate shape.

In this embodiment, FET 204 is connected to metal layer 1 in the embodiment of FIG. 1E. 32 is shown. ), the conical emitter 127 is The device may be substantially non-planar. FET201 is related to Figure 2D. The drain 202 of the FET 201 is connected to a specific conductive path. 208 to FET gate 103 .

FIG. 2F shows a fifth embodiment 200' of the FET electrode for the FET gate shape.

In this embodiment 200', FET 104 is the same as described above with respect to FIG. It may be the same. FET 201 is connected to the ammo It may be formed of a layer of Rufus or polysilicon semiconductor material 134. this In an embodiment, drain 202 is coupled directly to A-gate 103.

Fig. 2G shows the sixth embodiment 2 for realizing the FETE pole for the FET gate shape. 006 is shown. In this embodiment, FET 104 is as described above with respect to FIG. 4F. is formed in the same way. The FET 201 has a source 203 and a drain 202. formed in a layer of amorphous silicon (or polysilicon) semiconductor material 211. It is formed in the same manner as described above with respect to the second E, except that it is formed.

FIG. 2H shows a seventh embodiment 2007 of the FET electrode for the FET gate shape.

In this embodiment, FET 104 has the opposite structure as described above with respect to Figure 1H. It may be constructed. FET201 is! The same ammo as described above for the lH diagram formed in a layer of rufus silicon (or polysilicon) semiconductor material 134. Ru. Both source 203 and drain 202 are formed in amorphous layer 134. will be accomplished. The drain 202 is connected to the gate of FET 104 via a specific metal path 136. 103.

Bipolar collector for FET emitter configuration Figure 3A shows the bipolar collector Collector 102 of transistor 101 is connected to emitter 301 of FET 104 FET 104 and bipolar transistor 101 coupled to each other as shown in FIG. A conceptual configuration diagram is shown. For certain applications, emitter 301 may be configured to control the desired mode of operation. coupled to a specific radio wave source 302 to accomplish this.

Figure 3B shows a diagram for realizing this bipolar collector in the form of an FET emitter. 1 Example 3001 is shown. FET 104 has a conical emitter 301. It has a planar structure, with the collector region 102 of the bipolar transistor 101 at the bottom. The first layer is deposited in the second layer, except that the This is substantially similar to that described above with respect to Figure 1B. are connected like that The bipolar collector is a general integrated structure and is connected directly to the FET emitter 301. Continue.

3rd C [! I is a second embodiment of bipolar collector for FET emitter geometry 300''. In this example, FET 104 is shown in FIG. 1C. The gate 103 has a substantially planar structure as shown in FIG. It differs in that it does not include an extension for contacting 02. bipolar tiger The register 101 is substantially similar to that described above with respect to FIG. 1C. This implementation In the example, metal deposit 302 is placed on a transistor core to form the desired shape. The third DrgJ connects the Rector 102 to the FET emitter 301, and the FET emitter 301 is connected to the FET emitter 301. 2 shows a third embodiment of a bipolar collector.

In this embodiment 300', FET 104 is as described above with respect to the first DIH. substantially the opposite structure, requiring that gate 103 be made of a semiconductor material. rather, it is formed through the use of metal deposition. In addition, Ipolar transistor 101 is a semiconductor deposited in close proximity to FET emitter 301. Although in the body layer 303, it is formed in a manner similar to that described above with respect to FIG. 1D. be done. This semiconductor layer can be made of standard silicon material or amorphous (or porous). It may be constructed from a semiconductor material (resilicon). This layer of material 303 results in It functions as the collector of the bipolar transistor 101 composed of It makes contact with the FET emitter and achieves the desired shape.

FET Electrode for FET Emitter Shape FIG. 4A shows the emitter 40 of FET 104. 1 is a conceptual block diagram 400 of a FET 201 having an electrode 202 coupled to a FET 201. identification Although FET emitter 401 may be suitable for certain radio wave applications, 402.

FIG. 4B shows a first embodiment 4001 of FET electrodes for emitter shapes. this In an embodiment, the FET 104 has a conical emitter 401 with a non-brainer The structure is substantially similar to that described above with respect to FIG. 2B. Similarly, FE T is substantially formed in the support substrate 108 as described above in the second BrgJ. However, the drain 202 of FET 201 is deposited in the underlying layer and at least partially They differ in that T emitters 401 make electrical contact between them. this is the FET electrode (drain 202 in this example) and emitter 40 of FET 104. 1 to achieve an integral connection.

FIG. 4C shows a second embodiment 4002 of FET electrodes for FET emitter shapes. . In this embodiment, FET 104 has a structure similar to that described above with respect to FIG. 3C. a metal layer forming a structure and coupling the emitter 401 of the FET 104 to the structure of the preceding layer; 302 included. FETl0I is formed in the same manner as described above with respect to Figure 2C. However, in this embodiment, the drain 202 is at least partially connected to the metal layer 302. located below and coupled to the FET emitter 401, thereby achieving the desired shape. They differ in this respect.

$4 DI! l is the third embodiment 4003 of the FET electrode for the FET emitter shape shows. In this embodiment, FET 104 is implemented as described above with respect to Figure 2H. The structure is qualitatively opposite, and the gate layer 103 is electrically connected to the FET 201. They are significantly different in that they are not. Similarly, FET201 is amorphous a second Hr formed in a layer 134 of silicon or polysilicon semiconductor material; ! This is the same as described above regarding l:i. However, in this example , metal deposition 403 connects the drain 202 of FET 201 to the FET emitter 401. bond to the metal layer formed. Both embodiments have a FET drain 202 and a FET emitter. drain metal layer 401, thereby requiring a drain metal layer 403. It will no longer be that way.

In the schematic representation 700 of FIG. 7A, this multiple bipolar transistor of the FED 104 is shown. In the embodiment shown in FIG. 5, a plurality of bipolar collectors Example with gate connected and bipolar collector connected to FED emitter 300 This is a combination of the following embodiments. In particular, three bipolar transistors 102 is coupled to the gates of the corresponding three FEDs l04 in this example. ing. The collector 102 of the single bipolar transistor 101 is connected to the FED l It is coupled to each emitter 301 of 04. This general form is of course It can be realized using any of the physical embodiments described above, and can be implemented in various ways depending on the particular application. It is possible to obtain the shape.

Multiple FET vs. multiple FED placement FIG. 6 shows a plurality of FEDs 104, and the gate 103 of each FED is shown in FIG. 2A (i 3 and related various physical embodiments), the single-FET 20 1 is coupled to the drain 202 of 1. The emitter 401 of each FED 104 is the fourth A As described above with respect to Figure 1 (and associated physical implementation example) Coupled to the drain 202 of T201. Again, depending on the needs of the individual application , utilizing the various physical embodiments described above to realize the three FET-to-FED combinations. Available for use.

FED collector to bipolar transistor base arrangement with conical emitter It consists of a non-flat structure. 8 individual applications coupled to emitter 801 of 101 The emitter 801 of the bipolar transistor 101 is connected to a suitable voltage. Figure 8B shows the FED anode versus bipolar In one embodiment, a first embodiment 800' of transistor emitter arrangement, the FED 104 and bipolar transistor 101 as described above with respect to FIG. 7C. It can be formed in a similar manner. However, the difference is that in this example, bipolar The direction of the transistor is such that the conductive layer 803 is the emitter of the bipolar transistor lO1. 801 to the anode 704 of FED 104. Figure 8C shows a second implementation of the FED anode to bipolar transistor emitter arrangement. Example 800s In this example, the FED 104 and the bipolar transistor 10 1 can be formed substantially according to the embodiment of FIG. 7D.

However, the difference is that the position of bipolar transistor 101 is 5 bipolar transistors. Distor emitter 801 is suitably electrically coupled to the above FED anode 704 (8 03,709] FED anode to FET gate arrangement in a position that allows In the schematic diagram 900 of FIG. 9A, the FED anode 902 is connected to the gate of FET 201. 901. FET gate 90 as appropriate for individual applications. 1 can be coupled to a suitable bias point or current source 903. In this example, F EDLO 4 may be configured as described above in FIG. 8B. FET20 1 can be shaped as described above in Figure 2B. Just the differences , the source is not coupled to the anode 902 of the FED 104; instead, 7 node 902 extends to a sufficient distance and connects to the gate metal scrap 901 of FET 201. electrically coupled.

FIG. 9C shows a second embodiment 900 of a FED anode to FET gate arrangement. 0 In this example, FED IQ4 is formed as described above with respect to Figure 8C. Wear. FET 201 may be formed as described above with respect to FIG. 2B. Just above The exception for both examples is that the FET gate gold jli 901 is the FED anode 9 02.

FED anode vs. FET source placement FIG. 10A is a schematic diagram 1000 of the FED 104, the anode of the FED 104. 902 is coupled directly to the source 202 of FET 201.

The first QB diagram shows a first embodiment 1000' of the FED anode to FET source arrangement. show. In this example, FED 104 is configured in a flat configuration as described above with respect to FIG. 7B. It is constructed. FET 201 can be formed as described above in FIG. 4C.

However, the difference is that in this embodiment, the source 202 of the FET 201 is It is positioned to electrically contact the anode 9Q2 of No. 4.

The 10th crM is a second embodiment of the FED7/-dose pair FET7-dose arrangement 1000" In this embodiment, the FED 104 is shaped as described above with respect to FIG. 7C. can be attached. FET 201 is shaped as described above with respect to Figure 2B. can be used. However, the difference is that in this embodiment, the FET source 202 is It is electrically coupled to the ED anode 902.

The JIQD diagram shows a third embodiment of the FED anode to FET source arrangement 1000''. In one embodiment shown, the FED is shaped as described above with respect to Figure 7D. Can be done. FET 201 should be shaped as described above for the first oca. , thereby causing FET source 202 to be electrically connected to FED anode 902. They are combined (906).

FED anode to multiple bipolar transistor base arrangement No. 11A5ii1 is the No. 1 of the FED anode to bipolar transistor base arrangement. In this example, the FED anode 704 is ? Ifi is coupled to the base 701 of the bipolar transistor 101. like that The circuit according to any of the physical embodiments described above.

FED anode to multiple bipolar transistor emitter arrangement FIG. 11B shows the fourth example of the FED anode-to-bibolar transistor emic arrangement. In this example, showing example 8004, FED anode 704 includes multiple bipots. is coupled to the emitter of the controller transistor 101. That/such a circuit is can be physically incorporated into a pair of packages according to any of the physical embodiments described above. It is possible.

FED anode to multiple FET gate arrangement FIG. 12A shows the FED anode to multiple FET gate arrangement. In this example, showing a third example 900″ of gate arrangement, the FED anode 90 is coupled to multiple FET gate gold ff1901. Such a circuit is Can be physically integrated into a pair of packages by any of the physical embodiments It is.

FED anode to multiple FET source arrangement Figure 12B shows FED anode to FET source arrangement. In this embodiment, the FED anode 9 02 couples to multiple FET sources 202. Such a circuit is based on the physical Summary that can be physically incorporated into a pair of packages by any of the following embodiments: book Field emission devices and controls such as field effect transistors and bipolar transistors An electronic device that is integrally integrated with a non-field emission device that controls or is controlled. , an embodiment of a field emission device includes a substantially planarly oriented electrode; These include non-planar structures with conical emitters and inverted emitter structures. There is.

international search report

Claims (8)

[Claims] 1. cold cathode field emission devices; and A non-field emission active device formed integrally with the cold cathode field emission device. the law of nature, the cold field emission device is fixedly coupled to a non-field emission active device; An electronic device characterized by: 2. 2. The apparatus of claim 1, wherein: the non-field emission active device is a bipod. 1. A device characterized in that it consists of a polar transistor. 3. 3. The apparatus of claim 2, wherein: the cold cathode field emission device comprises a It is characterized by its operation being at least partially controlled by bipolar transistors. device to do. 4. 3. The device according to claim 2, wherein: the bipolar transistor comprises a The operation is controlled at least partially by a cold cathode field emission device. device to do. 5. 2. The apparatus of claim 1, wherein: the non-field emission active device is a field effect device. A device consisting of a transistor. 6. 6. The apparatus of claim 5, wherein: the cold cathode field emission device comprises a It is characterized by its operation being at least partially controlled by field effect transistors. equipment. 7. 7. The device according to claim 6, wherein: the field effect transistor comprises at least Both are characterized in that their operation is partially controlled by a cold cathode field emission device. equipment. 8. 2. The apparatus of claim 1, wherein: the cold cathode field emission device comprises: that the operation is controlled, at least in part, by a non-field emission semiconductor device; Featured device.