JPS60211982A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS60211982A JPS60211982A JP6763884A JP6763884A JPS60211982A JP S60211982 A JPS60211982 A JP S60211982A JP 6763884 A JP6763884 A JP 6763884A JP 6763884 A JP6763884 A JP 6763884A JP S60211982 A JPS60211982 A JP S60211982A
- Authority
- JP
- Japan
- Prior art keywords
- hydrogenated silicon
- amorphous hydrogenated
- layer
- amorphous
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000010408 film Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052703 rhodium Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 229910052720 vanadium Inorganic materials 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- -1 T i Inorganic materials 0.000 claims 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 19
- 239000011521 glass Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 150000002739 metals Chemical class 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 3
- 239000000203 mixture Substances 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 150000003376 silicon Chemical class 0.000 description 21
- 239000007789 gas Substances 0.000 description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 238000010406 interfacial reaction Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052990 silicon hydride Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は非晶質水素化シリコンを用いた薄膜トランジス
タ（Ｔ Ｐ Ｔ）及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a thin film transistor (TPT) using amorphous hydrogenated silicon and a method for manufacturing the same.
近年、多損晶または非晶質半導体により形成された薄膜
トランジスタ（Ｔ Ｐ Ｔ）が注目されている。特にこ
れらの半導体が低温で形成できる場合にはその基板に対
する限定が緩やかとなり、例えばガラスのような低融点
の基板にも堆積できるので多くの応用が考えられる。例
えば液晶表示素子用のアクティブマトリクス基板があげ
られる。これらの半導体の中でも非晶質水素子シリコン
はプラズマＣＶ Ｄ （Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ
Ｄｅｐｏｓｉｔｉｏｎ）法により２００℃〜３００℃
の低い基板温度で堆積できるため有望な材料として注目
を集めている。2. Description of the Related Art In recent years, thin film transistors (TPTs) formed from polyloss crystals or amorphous semiconductors have been attracting attention. In particular, when these semiconductors can be formed at low temperatures, the restrictions on the substrate are relaxed, and they can be deposited even on substrates with low melting points, such as glass, so that many applications are possible. For example, active matrix substrates for liquid crystal display devices can be mentioned. Among these semiconductors, amorphous hydrogen element silicon is a plasma CVD (Chemical Vapor
200°C to 300°C by Deposition method
It is attracting attention as a promising material because it can be deposited at low substrate temperatures.
第１図に非晶質水素化シリコンを用いた一般的なＴＰＴ
の断面図を示す。ガラス基板１上にゲート電極２．ゲー
ト絶縁膜３．非晶質水素化シリコン層（ｉ層）４．ソー
ス電極５．ドレイン電極６を順次形成した構造となって
いる。ゲート電極２としてはガラスとの接着性の良いＣ
ｒ、Ｎｉ等の金属が用いられ、ゲート絶縁膜３としては
ＳｉＮ。Figure 1 shows a typical TPT using amorphous hydrogenated silicon.
A cross-sectional view is shown. A gate electrode 2 is formed on a glass substrate 1. Gate insulating film 3. Amorphous hydrogenated silicon layer (i-layer)4. Source electrode5. It has a structure in which drain electrodes 6 are sequentially formed. The gate electrode 2 is made of C, which has good adhesion to glass.
Metals such as r, Ni, etc. are used, and the gate insulating film 3 is SiN.
５ｉ０２等が用いられる。ソース電極５．ドレイン電極
６としてはＡ Ｑ 、 Ｎ ｉ Ｃｒ等が用いられる。5i02 etc. are used. Source electrode5. As the drain electrode 6, AQ, NiCr, etc. are used.
ゲート、ソート、ドレインは蒸着あるいはスパッタリン
グで形成され、非晶質水素化シリコン層４゜ゲート絶縁
膜３はプラズマＣＶＤ法で堆積される。The gate, sort, and drain are formed by vapor deposition or sputtering, and the amorphous hydrogenated silicon layer 4 and the gate insulating film 3 are deposited by plasma CVD.
この場合、ゲートを半導体膜に対し、ガラス基板側に設
けたが、この順序とは逆にソース・ドレインをガラス基
板側に設けた場合もある。In this case, the gate was provided on the glass substrate side with respect to the semiconductor film, but in some cases the source and drain were provided on the glass substrate side in the opposite order.
しかし、非晶質水素化シリコン層４は空気中で自然酸化
されやすい、フェルミレベルが通常禁制帯の中央付近に
あるなどの理由でソース、ドレインと非晶質水素化シリ
コン層のオーミック性は十分とはいいがたいものである
。この点を改善するため第２図に示すように非晶質水素
化シリコン層とソース・ドレインの間にｎ＋導電形の非
晶質水素化シリコン層７を設ける事が提案されている。However, because the amorphous silicon hydride layer 4 is easily oxidized naturally in the air and the Fermi level is usually near the center of the forbidden band, the ohmic properties of the source, drain, and amorphous silicon hydride layer are sufficient. It's hard to say. In order to improve this point, it has been proposed to provide an amorphous silicon hydride layer 7 of n+ conductivity type between the amorphous silicon hydride layer and the source/drain as shown in FIG.
このようにすればオーミック性は改善されるが、工程数
は増加し、ｎ＋層とｉ層の選択エツチングの必要がでて
くる。Although this improves the ohmic properties, the number of steps increases and selective etching of the n+ layer and i layer becomes necessary.
また、ソース・ドレイン電極として比較的良く用いられ
るＡＱは２００℃程度の比較的低温で非晶質水素化シリ
コンと反応し、ＡＱとＳｉの相互拡散が起こる。これに
対し、特開昭５７＝−２０４１６８〜２０４１６９中で
はこの問題にふれ、ＡＱの膜厚を厚くしたり、ＡＱの中
にＳｉを１〜２％含んだものを使う事をすすめている。Furthermore, AQ, which is relatively commonly used as source/drain electrodes, reacts with amorphous silicon hydride at a relatively low temperature of about 200° C., causing interdiffusion of AQ and Si. On the other hand, JP-A-57-204168-204169 touches upon this problem and recommends increasing the thickness of AQ or using AQ containing 1 to 2% Si.
しかし、特願昭５７−２２０６４１中で述べたようにＡ
Ｑを厚くするとかえって反応が速くなる。また、非晶質
水素化シリコン層が薄いため、Ｓｔを含んだＡＱの効果
にも限界がある。このような反応はＴＰＴの信頼性を損
い、好ましくない。なお、反応は非晶質水素化シリコン
層の導電形にかかわらず起こる。However, as stated in the patent application No. 57-220641, A.
Increasing Q actually speeds up the reaction. Furthermore, since the amorphous hydrogenated silicon layer is thin, there is a limit to the effectiveness of AQ containing St. Such a reaction impairs the reliability of TPT and is undesirable. Note that the reaction occurs regardless of the conductivity type of the amorphous hydrogenated silicon layer.
本発明の目的は金属と非晶質水素化シリコンの加熱界面
反応とによる導電層をソース電極と非晶質水素化シリコ
ン層、ドレイン電極と非晶質水素化シリコン層の間に介
在させる事により、オン電流が高く、しかも耐熱性の良
好な薄膜トランジスタを提供する事にある。The purpose of the present invention is to interpose a conductive layer between a source electrode and an amorphous silicon hydride layer, and between a drain electrode and an amorphous silicon hydride layer, by interposing a conductive layer through a heated interface reaction between a metal and an amorphous silicon hydride. The object of the present invention is to provide a thin film transistor with high on-current and good heat resistance.
本発明は薄膜トランジスタにおいて非晶質水素化シリコ
ン層とソース・ドレイン電極のオーミック性及び耐熱性
を向上させるために金属と非晶質水素化シリコン層との
加熱界面反応を利用する事を特徴としている。以下、詳
細に本発明を説明する。The present invention is characterized by utilizing a heated interface reaction between a metal and an amorphous silicon hydride layer in order to improve the ohmic properties and heat resistance of the amorphous silicon hydride layer and source/drain electrodes in a thin film transistor. . The present invention will be explained in detail below.
先に述べたようにＡＱと非晶質水素化シリコンはオーミ
ック性が良好でなく、しかも耐熱性において劣っている
。これに対し、たとえばＣｒは非晶質水素化シリコンと
の間の反応の様子が異なっている事を発見した。非晶質
水素化シリコン上に基板温度１００℃以上に加熱してＣ
ｒあるいはＣｒ−ＡＱ、Ｃｒ−Ｎｉ、Ｃｒ−Ｎｉ Ｃｒ
−Ａｕ。As mentioned above, AQ and amorphous hydrogenated silicon do not have good ohmic properties and are also inferior in heat resistance. On the other hand, it has been discovered that, for example, Cr reacts differently with amorphous hydrogenated silicon. C on amorphous hydrogenated silicon by heating the substrate to a temperature of 100°C or higher.
r or Cr-AQ, Cr-Ni, Cr-Ni Cr
-Au.
Ｃｒ−Ｎ１−Ａｎなど（Ｃｒ −Ａ Ｑ等の表示はＣｒ
とＡＱの２層構造を表わし、かっｓｒ ｔｚで結ばれた
前にある金属が先に堆積される事を意味する。Cr-N1-An, etc. (Cr-A Q, etc. is Cr
It represents a two-layer structure of and AQ, and means that the metal in front of it connected by sr tz is deposited first.
以下同様。）を蒸着法あるいはスパッタリング法で堆積
するか、あるいは基板温度がこれ以下でも金属を堆積後
に１００℃以上で加熱処理した後、この金属を除去する
と非晶質水素化シリコン表面にＣｒとの反応層が残る。Same below. ) is deposited by vapor deposition or sputtering, or even if the substrate temperature is lower than this, if the metal is deposited and then heated at 100°C or higher and then this metal is removed, a reaction layer with Cr is formed on the surface of the amorphous silicon hydride. remains.
この反応層は非晶質水素化シリコン層より低抵抗で１０
に０７口以下である。しかも、ＡＱと非晶質水素化シリ
コンの場合には場所的に不均一に反応するが、Ｃｒと非
晶質水素化シリコンの場合には膜全面で均一に反応する
。この反応層の厚さはたかだか数十人程度であり、しか
もある時間以上の熱処理には反応が進行しなくなるため
、耐熱性は十分に高い。また、このような熱処理あるい
は加熱、蒸着によって金属と非晶質水素化シリコンの接
触が、界面反応層と非晶質水素化シリコンの接触におき
かえられるため、オーミック性が良好となる。これは非
晶質水素化シリコンの表面がたとえ十分に洗浄したとし
ても原子レベルでは汚染されているのに、反応後の界面
反応層と非晶質水素化シリコンの界面は反応前は非晶質
水素化シリコンの内部であったところに存在するためと
考えられる。さらに通常金属と半導体の加熱反応層、た
とえばシリサイドは金属と比べて半導体に対する障壁が
低くなる傾向にあるためオーミック性が良好となる。This reaction layer has a lower resistance than the amorphous hydrogenated silicon layer by 10
07 units or less. Moreover, in the case of AQ and amorphous hydrogenated silicon, the reaction occurs unevenly locally, but in the case of Cr and amorphous hydrogenated silicon, the reaction occurs uniformly over the entire surface of the film. The thickness of this reaction layer is about several tens of layers at most, and the reaction does not proceed after heat treatment for a certain period of time, so the heat resistance is sufficiently high. Further, by such heat treatment, heating, and vapor deposition, the contact between the metal and the amorphous silicon hydride is replaced with the contact between the interfacial reaction layer and the amorphous silicon hydride, so that ohmic properties are improved. This is because the surface of amorphous hydrogenated silicon is contaminated at the atomic level even if thoroughly cleaned, but the interface between the interfacial reaction layer and the amorphous hydrogenated silicon after the reaction is amorphous before the reaction. This is thought to be because it exists in a place that used to be inside the silicon hydride. Furthermore, a thermal reaction layer of a metal and a semiconductor, such as silicide, tends to have a lower barrier to semiconductors than a metal, and therefore has good ohmic properties.
Ｃｒ膜の厚さとしてはそれほど選択性はないが、３００
〜２０００人より好ましくは５００〜２０００人を用い
る。あまり膜が薄いと均一性に欠け、あまり膜が厚いと
半導体層への応力で悪影響がでる。配線の直列抵抗を低
減するためには先に記したようにＣｒの上に低抵抗金属
を堆積すれば良い。The thickness of the Cr film is not very selective, but 300
-2000 people, preferably 500-2000 people. If the film is too thin, it will lack uniformity, and if the film is too thick, stress on the semiconductor layer will have an adverse effect. In order to reduce the series resistance of the wiring, a low resistance metal may be deposited on Cr as described above.
反応温度は１００〜２５０℃を用いる。特に２５０℃以
上になると非晶質水素化シリコン中の水素がぬけてしま
うので好ましくない。反応時間は２０〜１時間程度で先
に記したように長時間加熱しても反応は進行しなくなり
、特に利点はない。The reaction temperature used is 100 to 250°C. In particular, if the temperature exceeds 250° C., hydrogen in the amorphous hydrogenated silicon will escape, which is not preferable. The reaction time is about 20 to 1 hour, and as mentioned above, even if heated for a long time, the reaction will not proceed and there is no particular advantage.
更に非晶質水素化シリコン上に金属を堆積する直前に、
表面処理をし、表面酸化層や汚染層を除去する事は反応
を安定に生ぜしぬるのに効果がある。Furthermore, just before depositing the metal on the amorphous hydrogenated silicon,
Surface treatment and removal of surface oxidation layers and contaminant layers is effective in stably generating reactions.
非晶質水素化シリコン層としてはその伝導形がｐ、ｉ、
ｎ型のいずれの場合も同様に反応がおきる。通常用いら
れる不純物であるＰ、Ｂ、Ｃ，Ｎ等を含んでいても同様
である。The conductivity type of the amorphous hydrogenated silicon layer is p, i,
A similar reaction occurs in both n-type cases. The same applies even if it contains commonly used impurities such as P, B, C, and N.
又、非晶質シリコンのダングリングボンド（ｄａｎｇｌ
ｉｎｇ ｂｏｎｄ）のターミネータとして導入されてい
るＨのかわりにＦを用いている場合や、非晶質ＳｉＣや
非晶質５ｉＧｅでも同様である。In addition, dangling bonds (dangl) of amorphous silicon
The same applies to cases where F is used instead of H introduced as a terminator in bonding bond), or when using amorphous SiC or amorphous 5iGe.
非晶質シリコンと反応させる金属としては上ではＯｒの
場合について述べたが、Ｃｒ、Ｎｉ。As the metal to be reacted with amorphous silicon, the case of Or was described above, but Cr and Ni may also be used.
Ｍｏ、Ｔａ、Ｗ＋ Ｔｉ、Ｖ、Ｚｒ、Ｎｂ、Ｈｆ。Mo, Ta, W+ Ti, V, Zr, Nb, Hf.
Ｐｔ、Ｐｄ、Ｒｈ及びＣｏのうちいずれか一つ又は二つ
以上の金属を含んでいれば良い。いずれの場合において
も加熱反応により加熱反応前よりオーミック性が良好と
なり、耐熱性も良好である。It is sufficient if it contains one or more metals among Pt, Pd, Rh, and Co. In either case, the ohmic properties are better due to the heating reaction than before the heating reaction, and the heat resistance is also good.
なかでもＣｒ、Ｎｉ、Ｍｏあるいはこれらの合金は非晶
質シリコンに対する障壁高さが低く、加工性も良好であ
る事から望ましくはこれらのうちから選ぶ。Among these, Cr, Ni, Mo, or an alloy thereof is preferably selected from these materials because they have a low barrier height to amorphous silicon and have good workability.
以下、本発明の実施例を示す。 Examples of the present invention will be shown below.
実施例１
第３図に示すようにガラス基板８上にＣｒ電極９を例え
ばＡｒガスを雰囲気とするスパッタリングにより膜厚０
．３μｍに形成する。その上にプラズマＣＶＤ法により
基板温度３００℃でＳｉＨ４ガス、ＮＨ３ガス、Ｎ２ガ
スを混合比１：２＝１５で混合したガスを用いてＳｉＮ
ゲート絶縁膜１０を堆積、連続してガスを５ｉＨａガス
のみに切換えて非晶質水素化シリコン（ｉ層）１１を順
次堆積する。この２層膜所望のパターンにパターン化後
、基板温度を１００〜２５０℃の範囲とし、Ｃｒを０．
１μｍ、ＡＱを１μｍ蒸着で堆積する。Example 1 As shown in FIG. 3, a Cr electrode 9 is deposited on a glass substrate 8 to a film thickness of 0 by sputtering in an Ar gas atmosphere, for example.
．． Formed to 3 μm. On top of that, SiN was deposited using a gas mixture of SiH4 gas, NH3 gas, and N2 gas at a mixing ratio of 1:2=15 at a substrate temperature of 300°C using the plasma CVD method.
A gate insulating film 10 is deposited, and then the gas is switched to 5iHa gas only, and an amorphous hydrogenated silicon (i-layer) 11 is deposited one after another. After patterning this two-layer film into a desired pattern, the substrate temperature is set to a range of 100 to 250°C, and the Cr content is set to 0.
1 μm, and AQ is deposited by 1 μm evaporation.
その後、ホトエツチングにてソース・ドレイン電極１２
．１３にパターン化する。このようにすると金属電極１
２．１３と非晶質水素化シリコン（ｉ層）１１との間に
反応層１４．１５が形成される。この時、チャネル部分
１６にも反応層が残っているが、弗酸、硝酸の薄い混合
液（例えば混合比は弗酸：硝酸：水＝１：１：３０）に
て除去可能である。After that, the source/drain electrodes 12 are etched by photo-etching.
．． Pattern 13. In this way, metal electrode 1
A reaction layer 14.15 is formed between 2.13 and the amorphous hydrogenated silicon (i-layer) 11. At this time, a reaction layer remains in the channel portion 16, but it can be removed with a dilute mixed solution of hydrofluoric acid and nitric acid (for example, the mixing ratio is hydrofluoric acid: nitric acid: water = 1:1:30).
ここではゲート金属としてＣｒを用いたが、Ｎ ｉ 、
Ｎ ｉ Ｃｒ 、 Ｔ ｄ 、 Ｍ ｏ 、 Ｗ 、
等も用いる事ができる。Here, Cr was used as the gate metal, but N i ,
N i Cr , T d , M o , W ,
etc. can also be used.
また、ここではソースドレイン電極用金属を基板加熱し
つつ蒸着したが、加熱せずに蒸着した後。In addition, here, the metal for the source and drain electrodes was deposited while heating the substrate, but after it was deposited without heating.
加熱処理しても良い。 。Heat treatment may also be applied. .
さらにここではｉ層にソース・ドレインを直接形成した
が、第４図の如く、ｎ＋導電形の非晶質水素化シリコン
１７を間に形成しても良い。Furthermore, although the source and drain are formed directly in the i-layer here, as shown in FIG. 4, an amorphous hydrogenated silicon 17 of n+ conductivity type may be formed between them.
すなわち、１層１１堆積後、ガスを切換えてＰ Ｈ３ガ
スとＳｉＨ４ガスの混合ガス（ＰＨ３／ＳｉＨ４≧０．
５ 体積％）を導入し、プラズマＣＶＤにより５０人〜
１０００人堆積し、しかるのち前述したと同様、この３
層膜をパターン化しソース・ドレイン電極を形成し、チ
ャネル部分の反応層を除去する。この後、ソース・ドレ
インと同形状にｎ＋層１７をパターン化すれば良い。That is, after one layer 11 is deposited, the gas is changed to a mixed gas of PH3 gas and SiH4 gas (PH3/SiH4≧0.
5% by volume) was introduced, and 50 or more people were
1,000 people deposited, and then, as mentioned above, these three
The layer film is patterned to form source and drain electrodes, and the reaction layer in the channel portion is removed. After this, the n+ layer 17 may be patterned in the same shape as the source/drain.
実施例２
実施例１ではチャネル部分に反応層が形成されたが、本
実施例ではこれを避け、かつｉ層のパッシベーションを
はかったものである。第５図に示すように１層１１の堆
積までは前述したものと同じであるが、この後ガスを５
ｉＨａガス、ＮＨ３ガス、Ｎ２ガス（混合比１：２：１
５）の混合ガスに切換えてＳ ｉ Ｎ 、膜１８を１μ
ｍ堆積する。Example 2 In Example 1, a reaction layer was formed in the channel portion, but in this example, this was avoided and the i-layer was passivated. As shown in FIG. 5, the process up to the deposition of one layer 11 is the same as that described above, but after this, the gas is
iHa gas, NH3 gas, N2 gas (mixing ratio 1:2:1
5) Switch to the mixed gas and apply S i N to the membrane 18 by 1μ.
Deposit m.
この３層膜をパターン化後、さらに上部のＳｉＮ膜１８
のみをさらにソース・ドレインが形成できるように加工
する。この上にソース・トレイン金属１２．１３として
Ｃｒ （０，１μｍ） 、 Ｎ ｉ（０，１μｍ） 、
Ａｕ （０，２μｍ）を蒸着法にて堆積し、加工すれ
ばＴＰＴが完成する。After patterning this three-layer film, the upper SiN film 18
Further, the only part is processed so that sources and drains can be formed. On top of this, as the source train metal 12.13, Cr (0,1 μm), Ni (0,1 μm),
TPT is completed by depositing Au (0.2 μm) by vapor deposition and processing.
本発明によればソース・ドレインと非晶質シリコンのオ
ーミック性が良好で、かつ耐熱性にすぐれた薄膜トラン
ジスタを実現する事ができる。According to the present invention, a thin film transistor with good ohmic properties between the source/drain and amorphous silicon and excellent heat resistance can be realized.
第１図、第２図は従来の薄膜トランジスタの断面図、第
３図、第４図、第５図は本発明の実施例になる薄膜トラ
ンジスタの断面図である。
８・・・ガラス基板、９・・・ゲート電極、１０・・・
ゲート絶縁膜、１１・・・非晶質水素化シリコン膜、１
２゜１３・・・ソース・ドレイン電極、１４．１５・・
・界面反応層。
■１図
第Ｚ図1 and 2 are cross-sectional views of conventional thin film transistors, and FIGS. 3, 4, and 5 are cross-sectional views of thin film transistors according to embodiments of the present invention. 8...Glass substrate, 9...Gate electrode, 10...
Gate insulating film, 11...Amorphous hydrogenated silicon film, 1
2゜13...source/drain electrode, 14.15...
・Interfacial reaction layer. ■Figure 1 Figure Z
Claims (1)
非晶質シリコンからなる能動層、ゲート絶縁膜、ゲート
電極金属、ソース電極金属、ドレイン電極金属を有する
薄膜トランジスタにおいてソース電極金属と非晶質シリ
コン層の間、及びドレイン電極金属と非晶質シリオン層
の間に各々の電極金属と非晶質シリコン層の加熱界面反
応による導電層を有する事を特徴とする薄膜トランジス
タ。 ２、前記ソース電極金属、ドレイン電極金属が、Ｃｒ、
Ｎ ｉ、Ｍｏ、Ｗ、Ｔ ｉ、Ｖ、Ｚｒ、Ｎｂ。 Ｔａ、Ｈｆ、Ｐｔ、Ｐｄ、Ｒｈ、およびＧｏのうちいず
れか一つまたは、二つ以上の金属を含む事を特徴とする
特許請求の範囲第１項記載の薄膜トランジスタ。[Claims] 1. In a thin film transistor formed on a semiconductor or insulating substrate and having at least an active layer made of amorphous silicon, a gate insulating film, a gate electrode metal, a source electrode metal, and a drain electrode metal, the source electrode metal and an amorphous silicon layer, and between a drain electrode metal and an amorphous silicon layer, a conductive layer formed by heating interface reaction between each electrode metal and the amorphous silicon layer. 2. The source electrode metal and the drain electrode metal are Cr,
N i, Mo, W, T i, V, Zr, Nb. The thin film transistor according to claim 1, characterized in that the thin film transistor contains one or more of Ta, Hf, Pt, Pd, Rh, and Go.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6763884A JPS60211982A (en) | 1984-04-06 | 1984-04-06 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6763884A JPS60211982A (en) | 1984-04-06 | 1984-04-06 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60211982A true JPS60211982A (en) | 1985-10-24 |
Family
ID=13350734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6763884A Pending JPS60211982A (en) | 1984-04-06 | 1984-04-06 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60211982A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61248564A (en) * | 1985-04-26 | 1986-11-05 | Nec Corp | Thin film transistor and manufacture thereof |
| JPS6293978A (en) * | 1985-10-21 | 1987-04-30 | Hitachi Ltd | Manufacture of thin film transistor |
| JPS62259471A (en) * | 1986-05-02 | 1987-11-11 | Fuji Xerox Co Ltd | Manufacture of thin film transistor |
| JPS63158875A (en) * | 1986-12-22 | 1988-07-01 | Nec Corp | Manufacture of thin-film transistor |
| JPS63168052A (en) * | 1986-12-29 | 1988-07-12 | Nec Corp | Thin film transistor and manufacture thereof |
| JPH01248667A (en) * | 1988-03-30 | 1989-10-04 | Nissan Motor Co Ltd | Field-effect transistor |
| JPH0240962A (en) * | 1988-07-30 | 1990-02-09 | Fuji Xerox Co Ltd | Manufacture of thin film transistor |
| FR2665300A1 (en) * | 1990-07-27 | 1992-01-31 | Samsung Electronics Co Ltd | Process for fabricating a thin-film transistor |
| JPH06163903A (en) * | 1986-05-02 | 1994-06-10 | Fuji Xerox Co Ltd | Thin film transistor |
| US5648663A (en) * | 1985-08-05 | 1997-07-15 | Canon Kabushiki Kaisha | Semiconductor structure having transistor and other elements on a common substrate and process for producing the same |
| US10679847B2 (en) | 2018-03-01 | 2020-06-09 | International Business Machines Corporation | Self-aligned spacerless thin film transistor |
-
1984
- 1984-04-06 JP JP6763884A patent/JPS60211982A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61248564A (en) * | 1985-04-26 | 1986-11-05 | Nec Corp | Thin film transistor and manufacture thereof |
| US5686326A (en) * | 1985-08-05 | 1997-11-11 | Canon Kabushiki Kaisha | Method of making thin film transistor |
| US5648663A (en) * | 1985-08-05 | 1997-07-15 | Canon Kabushiki Kaisha | Semiconductor structure having transistor and other elements on a common substrate and process for producing the same |
| JPS6293978A (en) * | 1985-10-21 | 1987-04-30 | Hitachi Ltd | Manufacture of thin film transistor |
| JPH0669095B2 (en) * | 1985-10-21 | 1994-08-31 | 株式会社日立製作所 | Thin film transistor |
| JPH06163903A (en) * | 1986-05-02 | 1994-06-10 | Fuji Xerox Co Ltd | Thin film transistor |
| JPS62259471A (en) * | 1986-05-02 | 1987-11-11 | Fuji Xerox Co Ltd | Manufacture of thin film transistor |
| JPS63158875A (en) * | 1986-12-22 | 1988-07-01 | Nec Corp | Manufacture of thin-film transistor |
| JPS63168052A (en) * | 1986-12-29 | 1988-07-12 | Nec Corp | Thin film transistor and manufacture thereof |
| JPH01248667A (en) * | 1988-03-30 | 1989-10-04 | Nissan Motor Co Ltd | Field-effect transistor |
| JPH0240962A (en) * | 1988-07-30 | 1990-02-09 | Fuji Xerox Co Ltd | Manufacture of thin film transistor |
| FR2665300A1 (en) * | 1990-07-27 | 1992-01-31 | Samsung Electronics Co Ltd | Process for fabricating a thin-film transistor |
| US10679847B2 (en) | 2018-03-01 | 2020-06-09 | International Business Machines Corporation | Self-aligned spacerless thin film transistor |
| US10692716B2 (en) | 2018-03-01 | 2020-06-23 | International Business Machines Corporation | Self-aligned spacerless thin film transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0239958B1 (en) | Thin film semiconductor device and method of manufacturing the same | |
| US7384831B2 (en) | Thin film transistor and manufacturing method thereof | |
| JPH1093102A (en) | Method of manufacture thin-film transistor | |
| JPS60211982A (en) | Thin film transistor | |
| US6558986B1 (en) | Method of crystallizing amorphous silicon thin film and method of fabricating polysilicon thin film transistor using the crystallization method | |
| KR100607768B1 (en) | Thin film transistor and method for manufacturing same | |
| US6326226B1 (en) | Method of crystallizing an amorphous film | |
| JPH05304171A (en) | Thin-film transistor | |
| EP0068843B1 (en) | Method of producing a conductor in a desired pattern on a semiconductor substrate | |
| JPS6165477A (en) | Semiconductor device | |
| JPS58212177A (en) | Insulated gate type transistor and manufacture thereof | |
| JPS6159873A (en) | Thin film field effect transistor and manufacture thereof | |
| JPH08255769A (en) | Method of manufacturing semiconductor device | |
| JPS6029222B2 (en) | Method for manufacturing solid-state electronic devices | |
| JPH0556016B2 (en) | ||
| JPH0147012B2 (en) | ||
| CN100353565C (en) | Thin-film transistor element and manufacturing method thereof | |
| JP2000252472A (en) | Thin film semiconductor element and manufacture thereof | |
| JPH07162008A (en) | Polysilicon thin-film transistor | |
| JPS6063962A (en) | Manufacture of bi-polar transistor | |
| JPS5968975A (en) | Semiconductor device and manufacture thereof | |
| JPS58173847A (en) | Manufacture of element | |
| JPS61150236A (en) | Semiconductor device | |
| TWI253759B (en) | Method and apparatus for forming thin film transistor | |
| JPS5918632A (en) | Formation of electrode of semiconductor device |