KR100275953B1 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistor Download PDFInfo
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- KR100275953B1 KR100275953B1 KR1019980037795A KR19980037795A KR100275953B1 KR 100275953 B1 KR100275953 B1 KR 100275953B1 KR 1019980037795 A KR1019980037795 A KR 1019980037795A KR 19980037795 A KR19980037795 A KR 19980037795A KR 100275953 B1 KR100275953 B1 KR 100275953B1
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- active layer
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- 239000010409 thin film Substances 0.000 title abstract description 15
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 14
- 239000011651 chromium Substances 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- -1 physicodene (Mo) Substances 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000002161 passivation Methods 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 230000008018 melting Effects 0.000 description 7
- 238000002844 melting Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
Abstract
본 발명은 박막트렌지스터의 제조방법에 관한 것으로서 기판 상에 게이트전극을 형성하는 공정과, 상기 기판 상에 게이트절연층, 활성층, 오믹접촉층 및 제 1 도전층을 순차적으로 형성하고 상기 게이트전극과 대응하는 부분이 남도록 패터닝하는 공정과, 상기 기판 상에 상기 제 1 도전층을 덮도록 제 2 도전층을 형성하는 공정과, 상기 제 2 도전층, 제 1 도전층 및 오믹접촉층을 상기 활성층의 게이트전극과 대응하는 부분과 상기 게이트전극 일측의 상기 활성층 및 투명기판이 노출되도록 패터닝하여 소오스 및 드레인전극과 화소전극을 형성하는 공정과, 상술한 구조의 표면 상의 상기 게이트전극과 대응하는 부분에 보호막을 형성하고 상기 보호막을 마스크로 사용하여 상기 활성층의 상기 게이트전극 일측에 노출된 부분을 선택적으로 식각하는 공정을 구비한다. 따라서, 활성층의 소오스 및 드레인전극과 중첩되지 않은 노출된 부분을 제거하므로 누설전류를 방지할 수 있으며, 또한, 연속적인 에칭에 의해 발생되는 소오스 및 드레인전극의 패턴 불량된 부분을 에칭하므로 수율을 향상시킬 수 있다.The present invention relates to a method of manufacturing a thin film transistor, comprising the steps of forming a gate electrode on a substrate, and sequentially forming a gate insulating layer, an active layer, an ohmic contact layer, and a first conductive layer on the substrate and corresponding to the gate electrode. Patterning the portion so that a portion thereof remains; forming a second conductive layer on the substrate to cover the first conductive layer; and forming the second conductive layer, the first conductive layer, and the ohmic contact layer on the gate of the active layer. Forming a source electrode and a drain electrode and a pixel electrode by patterning the portion corresponding to the electrode and the active layer and the transparent substrate on one side of the gate electrode to expose the protective electrode; A hole for selectively etching portions exposed to one side of the gate electrode of the active layer using the passivation layer as a mask. It includes a. Therefore, since the exposed portions that do not overlap with the source and drain electrodes of the active layer are removed, leakage currents can be prevented, and the poor pattern of the source and drain electrodes generated by the continuous etching is etched to improve the yield. You can.
Description
본 발명은 박막트랜지스터에 관한 것으로서, 특히, 마스크 공정을 감소하는 박막트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, and more particularly, to a method of manufacturing a thin film transistor, which reduces a mask process.
일반적으로 박막트랜지스터는 액정표시소자(LCD ; Liquid Crystal Display)의 스위칭소자나 에스램(SRAM)의 부하트랜지스터로 사용된다.In general, the thin film transistor is used as a switching element of a liquid crystal display (LCD) or a load transistor of an SRAM.
상기에서 박막트랜지스터를 스위칭소자로 사용하는 액정표시소자는 화상 신호를 각 픽셀(Pixel) 영역으로 전달하여 화상을 표시한다. 화상은 화상신호의 레벨에 따라 투과되는 광의 량을 조절하므로 박형화가 가능하여 벽걸이 TV나 PC 등에 사용될 수 있다.The liquid crystal display device using the thin film transistor as the switching device transmits an image signal to each pixel area to display an image. Since the image adjusts the amount of light transmitted according to the level of the image signal, the image can be thinned and used for a wall-mounted TV or a PC.
액정표시소자의 스위칭소자로 사용하는 박막트랜지스터는 유리 등의 절연 특성을 갖는 투명기판 상에 매트릭스 형상으로 형성되는 데, 공정의 간략화, 생산성 향상 및 제조 원가절감을 위해 마스크 공정을 감소시킨 4 마스크 제조 방법이 채택되고 있다.The thin film transistors used as switching elements of liquid crystal display devices are formed in a matrix shape on transparent substrates having insulating properties such as glass, and manufacturing four masks with a reduced mask process to simplify the process, improve productivity, and reduce manufacturing cost. The method is being adopted.
도 1a 내지 1d는 종래 기술에 따른 박막트랜지스터의 제조공정도이다.1A to 1D are manufacturing process diagrams of a thin film transistor according to the prior art.
도 1a를 참조하면, 절연 특성을 갖는 투명기판(11) 상에 크롬(Cr), 물리브덴(Mo), 티타늄(Ti), 탄탈륨(Ta) 또는 텅스텐(W) 등의 고융점 금속을 스퍼터링(sputtering) 방법으로 증착한다. 그리고, 고융점 금속을 반응성이온에칭(Reactive Ion Etching : 이하, RIE라 칭함)을 포함하는 포토리쏘그래피(photolithography) 방법으로 패터닝하여 게이트전극(13)을 형성한다.Referring to FIG. 1A, sputtering a high melting point metal such as chromium (Cr), phybdenum (Mo), titanium (Ti), tantalum (Ta), or tungsten (W) on a transparent substrate 11 having insulating properties Deposition by sputtering method. The gate electrode 13 is formed by patterning the high melting point metal by a photolithography method including reactive ion etching (hereinafter referred to as RIE).
도 1b를 참조하면, 투명기판(11) 상에 게이트전극(13)을 덮도록 게이트절연층(15), 활성층(17), 오믹접촉층(19) 및 제 1 도전층(21)을 순차적으로 형성한다.Referring to FIG. 1B, the gate insulating layer 15, the active layer 17, the ohmic contact layer 19, and the first conductive layer 21 are sequentially disposed to cover the gate electrode 13 on the transparent substrate 11. Form.
상기에서 게이트절연층(15)은 SiNX또는 SiO2등의 절연물질을, 활성층(17)은 비정질실리콘을, 오믹접촉층(19)은 N+비정질실리콘을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 순차적으로 증착하므로써 형성된다. 그리고, 제 1 도전층(21)은 오믹접촉층(19) 상에 크롬(Cr), 물리브덴(Mo), 티타늄(Ti), 탄탈륨(Ta) 또는 텅스텐(W) 등의 고융점 금속을 증착한 후 열처리에 의해 실리사이드화 하므로써 형성된다. 제 1 도전층(21)을 형성할 때 반응하지 않고 잔류하는 고융점 금속을 제거한다.The gate insulating layer 15 is an insulating material such as SiN X or SiO 2 , the active layer 17 is amorphous silicon, the ohmic contact layer 19 is N + amorphous silicon (Chemical Vapor Deposition: Formed by sequential deposition by a CVD method). In addition, the first conductive layer 21 deposits a high melting point metal such as chromium (Cr), phybdenum (Mo), titanium (Ti), tantalum (Ta), or tungsten (W) on the ohmic contact layer 19. It is then formed by silicidation by heat treatment. When the first conductive layer 21 is formed, the high melting point metal remaining without reacting is removed.
제 1 도전층(21), 오믹접촉층(19), 활성층(17) 및 게이트절연층(15)을 게이트전극(13)과 대응하는 부분이 남도록 포토리쏘그래피 방법으로 패터닝한다.The first conductive layer 21, the ohmic contact layer 19, the active layer 17, and the gate insulating layer 15 are patterned by a photolithography method so that portions corresponding to the gate electrodes 13 remain.
도 1c를 참조하면, 투명기판(11) 상에 제 1 도전층(21)을 덮도록 인듐-주석산화물(Indium-Tin Oxide : 이하, ITO라 칭함) 등의 투명한 도전체를 스퍼터링 방법으로 증착하여 제 2 도전층(23)을 형성한다.Referring to FIG. 1C, a transparent conductor such as indium tin oxide (hereinafter referred to as ITO) is deposited on the transparent substrate 11 to cover the first conductive layer 21 by a sputtering method. The second conductive layer 23 is formed.
활성층(17)의 게이트전극(13)과 대응하는 부분이 노출되도록 제 2 도전층(23), 제 1 도전층(21) 및 오믹접촉층(19)을 포토리쏘그래피 방법으로 패터닝한다. 이 때, 게이트전극(13) 일측의 활성층(17) 및 투명기판(11)도 노출되도록 한다.The second conductive layer 23, the first conductive layer 21, and the ohmic contact layer 19 are patterned by a photolithography method so that portions corresponding to the gate electrodes 13 of the active layer 17 are exposed. At this time, the active layer 17 and the transparent substrate 11 on one side of the gate electrode 13 are also exposed.
상기에서 제 2 도전층(23)은 제 1 도전층(21)과 함께 소오스 및 드레인전극(25)(26)을 이루며, 이 소오스 및 드레인전극(25)(26) 사이의 활성층(17)의 노출된 부분은 채널영역이 된다. 또한, 제 2 도전층(23)은 게이트전극(13) 타측의 투명기판(11) 상에 소오스전극(25)과 전기적으로 연결되도록 형성되어 화소전극이 된다.In the above, the second conductive layer 23 forms the source and drain electrodes 25 and 26 together with the first conductive layer 21, and the active layer 17 between the source and drain electrodes 25 and 26 is formed. The exposed part becomes the channel region. In addition, the second conductive layer 23 is formed on the transparent substrate 11 on the other side of the gate electrode 13 to be electrically connected to the source electrode 25 to become a pixel electrode.
도 1d를 참조하면, 상술한 구조 상에 SiNX또는 SiO2등의 절연물질을 CVD 방법으로 증착하여 보호막(27)을 형성한다. 그리고, 보호막(27)을 포토리쏘그래피 방법으로 패터닝하여 화소전극(25)을 노출시킨다.Referring to FIG. 1D, a protective film 27 is formed by depositing an insulating material such as SiN X or SiO 2 on the above-described structure by a CVD method. Then, the protective film 27 is patterned by a photolithography method to expose the pixel electrode 25.
그러나, 상술한 종래 기술은 게이트전극의 타측에 화소전극을 형성하면서 소오스 및 드레인전극을 형성할 때 게이트전극의 일측에도 활성층이 노출되게 잔류하므로 누설전류가 증가되는 문제점이 있었다.However, the above-described conventional technology has a problem in that the leakage current increases because the active layer is also exposed on one side of the gate electrode when the source and drain electrodes are formed while the pixel electrode is formed on the other side of the gate electrode.
또한, 소오스 및 드레인전극을 연속적인 에칭에 의해 형성하므로 패턴 불량이 발생되어 수율이 저하되는 문제점이 있었다.In addition, since the source and drain electrodes are formed by continuous etching, there is a problem in that a defective pattern is generated and the yield is lowered.
따라서, 본 발명의 목적은 화소전극의 반대측에 활성층이 소오스 및 드레인전극에 돌출되게 잔류하는 것을 방지할 수 있는 박막트렌지스터의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor which can prevent the active layer from protruding from the source and drain electrodes on the opposite side of the pixel electrode.
본 발명의 다른 목적은 소오스 및 드레인전극의 패턴 불량이 발생되는 것을 방지하여 수율을 향상시킬 수 있는 박막트렌지스터의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a thin film transistor which can improve yield by preventing pattern defects of the source and drain electrodes from occurring.
도 1a 내지 도 1d는 종래기술에 따른 박막트랜지스터의 제조공정도1a to 1d is a manufacturing process diagram of a thin film transistor according to the prior art
도 2a 내지 도 2d는 본 발명에 따른 박막트랜지스터 제조공정도2a to 2d is a manufacturing process diagram of a thin film transistor according to the present invention
상기의 목적들을 달성하기 위한 본 발명에 따른 박막트렌지스터의 제조방법은 기판 상에 게이트전극을 형성하는 공정과, 상기 기판 상에 게이트절연층, 활성층, 오믹접촉층 및 제 1 도전층을 순차적으로 형성하고 상기 게이트전극과 대응하는 부분이 남도록 패터닝하는 공정과, 상기 기판 상에 상기 제 1 도전층을 덮도록 제 2 도전층을 형성하는 공정과, 상기 제 2 도전층, 제 1 도전층 및 오믹접촉층을 상기 활성층의 게이트전극과 대응하는 부분과 상기 게이트전극 일측의 상기 활성층 및 투명기판이 노출되도록 패터닝하여 소오스 및 드레인전극과 화소전극을 형성하는 공정과, 상술한 구조의 표면 상의 상기 게이트전극과 대응하는 부분에 보호막을 형성하고 상기 보호막을 마스크로 사용하여 상기 활성층의 상기 게이트전극 일측에 노출된 부분을 선택적으로 식각하는 공정을 구비한다.A method of manufacturing a thin film transistor according to the present invention for achieving the above objects is a step of forming a gate electrode on a substrate, and sequentially forming a gate insulating layer, an active layer, an ohmic contact layer and a first conductive layer on the substrate. And patterning a portion corresponding to the gate electrode to remain, forming a second conductive layer on the substrate so as to cover the first conductive layer, and forming the second conductive layer, the first conductive layer, and the ohmic contact. Patterning a layer to expose a portion corresponding to the gate electrode of the active layer, the active layer and the transparent substrate on one side of the gate electrode to form a source and drain electrode, and a pixel electrode, and the gate electrode on the surface of the above structure; A protective film is formed on a corresponding portion, and the exposed portion of one side of the gate electrode of the active layer is lined using the protective film as a mask. And a step of etching the enemy.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 2d는 본 발명에 따른 박막트랜지스터의 제조 공정도이다.2a to 2d is a manufacturing process diagram of a thin film transistor according to the present invention.
도 2a를 참조하면, 절연 특성을 갖는 투명기판(31) 상에 Al 또는 AlNd 등의 저저항 금속을 500∼1000Å 정도의 두께로 증착하고, 이 저저항 금속 상에 크롬(Cr), 물리브덴(Mo), 티타늄(Ti), 탄탈륨(Ta) 또는 텅스텐(W) 등의 고융점 금속을 스퍼터링 방법으로 500∼1000Å 정도의 두께로 증착한다. 그리고, 저저항 금속과 고융점 금속을 RIE를 포함하는 포토리쏘그래피 방법으로 패터닝하여 게이트전극(33)을 형성한다.Referring to FIG. 2A, a low-resistance metal such as Al or AlNd is deposited to a thickness of about 500 to 1000 GPa on a transparent substrate 31 having insulating properties, and chromium (Cr) and High melting point metals such as Mo), titanium (Ti), tantalum (Ta) or tungsten (W) are deposited to a thickness of about 500 to 1000 kPa by the sputtering method. The low resistance metal and the high melting point metal are patterned by a photolithography method including RIE to form the gate electrode 33.
도 2b를 참조하면, 투명기판(31) 상에 게이트전극(33)을 덮도록 게이트절연층(35), 활성층(37), 오믹접촉층(39) 및 제 1 도전층(41)을 순차적으로 형성한다.Referring to FIG. 2B, the gate insulating layer 35, the active layer 37, the ohmic contact layer 39, and the first conductive layer 41 are sequentially disposed to cover the gate electrode 33 on the transparent substrate 31. Form.
상기에서 게이트절연층(35)은 SiNX또는 SiO2등의 절연물질을, 활성층(37)은 비정질실리콘을, 오믹접촉층(39)은 N+비정질실리콘을 CVD 방법으로 순차적으로 증착하므로써 형성된다. 그리고, 제 1 도전층(41)은 오믹접촉층(39) 상에 크롬(Cr), 물리브덴(Mo), 티타늄(Ti), 탄탈륨(Ta) 또는 텅스텐(W) 등의 고융점 금속을 스퍼터링 방법으로 500∼1000Å 정도의 두께로 증착하므로써 형성된다.In the above, the gate insulating layer 35 is formed by sequentially depositing an insulating material such as SiN X or SiO 2 , the active layer 37 by amorphous silicon, and the ohmic contact layer 39 by depositing N + amorphous silicon by a CVD method. The first conductive layer 41 is sputtered on the ohmic contact layer 39 with a high melting point metal such as chromium (Cr), physicodene (Mo), titanium (Ti), tantalum (Ta), or tungsten (W). It is formed by depositing at a thickness of about 500 to 1000 mW by the method.
제 1 도전층(41), 오믹접촉층(39), 활성층(37) 및 게이트절연층(35)을 게이트전극(33)과 대응하는 부분이 남도록 포토리쏘그래피 방법으로 패터닝하여 투명기판(31)을 노출시킨다.The first conductive layer 41, the ohmic contact layer 39, the active layer 37, and the gate insulating layer 35 are patterned by a photolithography method so that portions corresponding to the gate electrodes 33 remain. Expose
도 2c를 참조하면, 투명기판(31) 상에 제 1 도전층(41)을 덮도록 ITO 또는 주석산화물(Tin Oxide : TO) 등의 투명한 도전체를 스퍼터링 방법으로 증착하여 제 2 도전층(43)을 형성한다.Referring to FIG. 2C, the second conductive layer 43 is deposited by sputtering a transparent conductor such as ITO or tin oxide (TO) to cover the first conductive layer 41 on the transparent substrate 31. ).
제 2 도전층(43), 제 1 도전층(41) 및 오믹접촉층(39)을 활성층(37)의 게이트전극(33)과 대응하는 부분이 노출되도록 포토리쏘그래피 방법으로 패터닝한다. 이 때, 게이트전극(33) 일측의 활성층(37) 및 투명기판(31)도 노출된다.The second conductive layer 43, the first conductive layer 41, and the ohmic contact layer 39 are patterned by a photolithography method so that portions corresponding to the gate electrodes 33 of the active layer 37 are exposed. At this time, the active layer 37 and the transparent substrate 31 on one side of the gate electrode 33 are also exposed.
상기에서 제 1 도전층(41)과 제 2 도전층(43)은 접촉되어 소오스 및 드레인전극(45)(46)을 이루며, 이 소오스 및 드레인전극(45)(46) 사이의 활성층(37)의 노출된 부분은 채널영역이 된다. 또한, 게이트전극(33) 타측의 투명기판(31) 상에 잔류하는 제 2 도전층(43)은 소오스전극(25)과 전기적으로 연결되어 화소전극이 된다.The first conductive layer 41 and the second conductive layer 43 are in contact with each other to form source and drain electrodes 45 and 46, and an active layer 37 between the source and drain electrodes 45 and 46. The exposed part of becomes the channel region. In addition, the second conductive layer 43 remaining on the transparent substrate 31 on the other side of the gate electrode 33 is electrically connected to the source electrode 25 to become a pixel electrode.
도 2d를 참조하면, 상술한 구조 상에 SiNX또는 SiO2등의 절연물질을 CVD 방법으로 증착하여 보호막(47)을 형성한다. 그리고, 보호막(47)을 게이트전극(33)과 대응하는 부분에만 잔류하도록 포토리쏘그래피 방법으로 패터닝한다. 이 때, 게이트전극(33) 일측에 활성층(37) 및 투명기판(31)이 노출되고 타측에 화소전극(25)이 노출된다.Referring to FIG. 2D, an insulating material such as SiN X or SiO 2 is deposited on the above-described structure by CVD to form a protective film 47. Then, the protective film 47 is patterned by a photolithography method so that only the portion corresponding to the gate electrode 33 remains. At this time, the active layer 37 and the transparent substrate 31 are exposed on one side of the gate electrode 33, and the pixel electrode 25 is exposed on the other side.
보호막(47)을 마스크로 사용하여 활성층(37)의 게이트전극(33) 일측에 노출된 부분을 선택적으로 식각한다. 그러므로, 활성층(37)의 게이트전극(33) 일측에 소오스 및 드레인전극(25)(26)과 중첩되지 않은 노출된 부분을 통해 흐르던 누설전류를 방지할 수 있다. 또한, 활성층(37)을 제거할 때 연속적인 에칭에 의해 발생되는 소오스 및 드레인전극(45)(46)의 패턴 불량된 부분도 에칭할 수 있으므로 수율을 향상시킬 수 있다.The exposed portion of one side of the gate electrode 33 of the active layer 37 is selectively etched using the passivation layer 47 as a mask. Therefore, leakage current flowing through an exposed portion of the active layer 37 not overlapping with the source and drain electrodes 25 and 26 on one side of the gate electrode 33 can be prevented. In addition, the defective portions of the source and drain electrodes 45 and 46 generated by continuous etching when the active layer 37 is removed can be etched, so that the yield can be improved.
상술한 바와 같이 본 발명에 따른 박막트렌지스터의 제조방법은 제 2 도전층, 제 1 도전층 및 오믹접촉층을 연속적으로 패터닝하여 소오스 및 드레인전극과 화소전극을 형성하고, 보호막을 형성한 후 게이트전극과 대응하는 부분에만 잔류하도록 패터닝할 때 활성층의 게이트전극 일측에 노출된 부분을 선택적으로 식각하면서 소오스 및 드레인전극의 패턴 불량된 부분도 에칭한다.As described above, in the method of manufacturing the thin film transistor according to the present invention, the second conductive layer, the first conductive layer, and the ohmic contact layer are successively patterned to form a source and drain electrode and a pixel electrode, and a protective film to form a gate electrode. When the patterning is performed so as to remain only in the portion corresponding to the photoresist layer, the portions exposed to one side of the gate electrode of the active layer are selectively etched, and the pattern defective portions of the source and drain electrodes are also etched.
따라서, 본 발명은 활성층의 소오스 및 드레인전극과 중첩되지 않은 노출된 부분을 제거하므로 누설전류를 방지할 수 있으며, 또한, 연속적인 에칭에 의해 발생되는 소오스 및 드레인전극의 패턴 불량된 부분을 에칭하므로 수율을 향상시킬 수 있는 잇점이 있다.Therefore, the present invention eliminates the exposed portions that do not overlap with the source and drain electrodes of the active layer, thereby preventing leakage current, and also etching the defective portions of the pattern of the source and drain electrodes generated by the continuous etching. There is an advantage in improving yield.
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