CA2150679C - Improved structure for cdse tft - Google Patents
Improved structure for cdse tft Download PDFInfo
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- CA2150679C CA2150679C CA002150679A CA2150679A CA2150679C CA 2150679 C CA2150679 C CA 2150679C CA 002150679 A CA002150679 A CA 002150679A CA 2150679 A CA2150679 A CA 2150679A CA 2150679 C CA2150679 C CA 2150679C
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- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000010409 thin film Substances 0.000 claims abstract description 15
- 239000012212 insulator Substances 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000011109 contamination Methods 0.000 claims description 5
- 238000000992 sputter etching Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims 1
- 239000011521 glass Substances 0.000 abstract description 6
- 239000000463 material Substances 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000011651 chromium Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
A thin film transistor, comprising: a glass substrate; a gate electrode deposited on the substrate; a gate insulator layer deposited on the substrate so as to overly the gate electrode; a thin film semiconductor channel layer deposited on the gate insulator layer and substantially aligned with the gate electrode;
a passivation layer deposited on the gate insulator layer so as to overly the thin film semiconductor channel layer; a pair of via holes etched though the passivation layer to the semiconductor channel layer; and a pair of source and drain electrodes deposited on the passivation layer and extending through the via holes for contacting the semiconductor channel layer.
a passivation layer deposited on the gate insulator layer so as to overly the thin film semiconductor channel layer; a pair of via holes etched though the passivation layer to the semiconductor channel layer; and a pair of source and drain electrodes deposited on the passivation layer and extending through the via holes for contacting the semiconductor channel layer.
Description
IMPROVED STRUCTURE FOR CdSe TFT
Field of the Invention This invention relates in general to thin film transistors (TFTs), and more particularly to an improved structure for CdSe thin film transistors for use in an active matrix liquid crystal display.
Background of the Invention Thin film transistor-based active matrix liquid crystal displays are now in production at a number of large electronics companies. These displays, used for personal television and lap-top computer screens, use amorphous silicon as the semiconductor.
Each dot in an active matrix liquid crystal display (AMLCD) acts as an analog sample and hold circuit, for sampling the video data and~holding it until the next data refresh cycle. The ability of an AMLCD to present good video pictures is directly related to the accuracy of the sample and hold circuits at each dot or pixel.
The TFT must have sufficiently high on-conductance to fully charge the pixel capacitance during the line address time, while having sufficiently low off-conductance to hold the charge accurately for the refresh period of the display.
Amorphous silicon TFTs used in early displays were known for their low leakage current in the "off" state while exhibiting enough "on" current to fully charge the pixel capacitance and activate the liquid crystal.
Amorphous silicon is rather a low mobility semiconductor however, so as the number of addressable lines in AMLCDs has increased, and the line address time has decreased, methods to increase the "on" current of the TFTs have been investigated.
The current output of amorphous silicon TFTs can be increased by simply increasing the gate voltage swings, increasing the channel width to length ratio, or by using a high dielectric constant gate insulator to decrease the channel capacitance.
2150b79 One prior art TFT design is disclosed in U.K. Patent GB
2087147 (National Research Development Corporation). As will be discussed in greater detail below, this prior art design suffers from the disadvantage that the thin metal source and drain layers can be contaminated prior to deposition of the semiconductor channel layer. Furthermore, once the semiconductor channel layer is deposited and patterned, it must be crystallized since it is formed of polycrystalline material. During crystallizing, the semiconductor material is subjected to high temperatures so that the source and drain contact material tends to diffuse into the semiconductor channel material and shortens the channel length.
In addition, when used as an AMLCD, an additional lithography step is required to ensure adequate current carrying capability of the source contact.
Summary of the Invention According to the present invention, an AMLCD design is provided in which the source and drain electrodes are deposited for connection to the semiconductor layer as the last step of the fabrication process. This avoids unwanted diffusion of the source and drain metallic contacts into the semiconductor material. Furthermore, according to the invention, the source and drain electrodes may be made of a desired thickness for increased current conduction, and no extra lithography step is required. In addition, the problem of organic contamination from residual lift-off photoresist, which arises in the prior art system disclosed in the UK
Patent, does not occur.
An aspect of the present invention is as follows:
Field of the Invention This invention relates in general to thin film transistors (TFTs), and more particularly to an improved structure for CdSe thin film transistors for use in an active matrix liquid crystal display.
Background of the Invention Thin film transistor-based active matrix liquid crystal displays are now in production at a number of large electronics companies. These displays, used for personal television and lap-top computer screens, use amorphous silicon as the semiconductor.
Each dot in an active matrix liquid crystal display (AMLCD) acts as an analog sample and hold circuit, for sampling the video data and~holding it until the next data refresh cycle. The ability of an AMLCD to present good video pictures is directly related to the accuracy of the sample and hold circuits at each dot or pixel.
The TFT must have sufficiently high on-conductance to fully charge the pixel capacitance during the line address time, while having sufficiently low off-conductance to hold the charge accurately for the refresh period of the display.
Amorphous silicon TFTs used in early displays were known for their low leakage current in the "off" state while exhibiting enough "on" current to fully charge the pixel capacitance and activate the liquid crystal.
Amorphous silicon is rather a low mobility semiconductor however, so as the number of addressable lines in AMLCDs has increased, and the line address time has decreased, methods to increase the "on" current of the TFTs have been investigated.
The current output of amorphous silicon TFTs can be increased by simply increasing the gate voltage swings, increasing the channel width to length ratio, or by using a high dielectric constant gate insulator to decrease the channel capacitance.
2150b79 One prior art TFT design is disclosed in U.K. Patent GB
2087147 (National Research Development Corporation). As will be discussed in greater detail below, this prior art design suffers from the disadvantage that the thin metal source and drain layers can be contaminated prior to deposition of the semiconductor channel layer. Furthermore, once the semiconductor channel layer is deposited and patterned, it must be crystallized since it is formed of polycrystalline material. During crystallizing, the semiconductor material is subjected to high temperatures so that the source and drain contact material tends to diffuse into the semiconductor channel material and shortens the channel length.
In addition, when used as an AMLCD, an additional lithography step is required to ensure adequate current carrying capability of the source contact.
Summary of the Invention According to the present invention, an AMLCD design is provided in which the source and drain electrodes are deposited for connection to the semiconductor layer as the last step of the fabrication process. This avoids unwanted diffusion of the source and drain metallic contacts into the semiconductor material. Furthermore, according to the invention, the source and drain electrodes may be made of a desired thickness for increased current conduction, and no extra lithography step is required. In addition, the problem of organic contamination from residual lift-off photoresist, which arises in the prior art system disclosed in the UK
Patent, does not occur.
An aspect of the present invention is as follows:
2150b79 A method of fabricating a thin film transistor, comprising the steps of:
a) providing a substrate;
b) depositing a gate electrode on said substrate;
c) depositing a gate insulator layer on said substrate so as to overly said gate electrode;
d) depositing a thin film semiconductor channel layer on said gate insulator layer so as to be substantially aligned with said gate electrode;
e) depositing a passivation layer on said gate insulator layer so as to overly said thin film semiconductor channel layer;
f) etching a pair of via holes through said passivation layer to said semiconductor channel layer; and g) depositing a pair of source and drain electrodes on said passivation layer so as to extend through said via holes for contacting said semiconductor channel layer.
Brief Description of the Drawings A detailed description of the preferred embodiment and of the prior art is provided herein below, with reference to the following drawings, in which:
Figure 1 is a plan view showing a prior art TFT array for AMLCD;
Figure 2 is a sectional view showing the prior art in Figure 1 taken along the line II-II thereof;
Figure 3 is a simplified schematic diagram of the sample and hold structure of the TFT shown in Figures 1 and 2;
Figures 4a, 4b and 4c show successive steps in the fabrication process of a TFT according to the preferred a..
21506.79 embodiment of the present invention;
Figure 5 is a graph showing current-voltage characteristics of the TFT according to the preferred embodiment of the present invention; and Figure 6 is a cross sectional view of an AMLCD
incorporating the TFTs of the present invention.
Detailed Description of the Preferred Embodiment and Prior Art Figures 1 and 2 show structures of an inverted TFT
a) providing a substrate;
b) depositing a gate electrode on said substrate;
c) depositing a gate insulator layer on said substrate so as to overly said gate electrode;
d) depositing a thin film semiconductor channel layer on said gate insulator layer so as to be substantially aligned with said gate electrode;
e) depositing a passivation layer on said gate insulator layer so as to overly said thin film semiconductor channel layer;
f) etching a pair of via holes through said passivation layer to said semiconductor channel layer; and g) depositing a pair of source and drain electrodes on said passivation layer so as to extend through said via holes for contacting said semiconductor channel layer.
Brief Description of the Drawings A detailed description of the preferred embodiment and of the prior art is provided herein below, with reference to the following drawings, in which:
Figure 1 is a plan view showing a prior art TFT array for AMLCD;
Figure 2 is a sectional view showing the prior art in Figure 1 taken along the line II-II thereof;
Figure 3 is a simplified schematic diagram of the sample and hold structure of the TFT shown in Figures 1 and 2;
Figures 4a, 4b and 4c show successive steps in the fabrication process of a TFT according to the preferred a..
21506.79 embodiment of the present invention;
Figure 5 is a graph showing current-voltage characteristics of the TFT according to the preferred embodiment of the present invention; and Figure 6 is a cross sectional view of an AMLCD
incorporating the TFTs of the present invention.
Detailed Description of the Preferred Embodiment and Prior Art Figures 1 and 2 show structures of an inverted TFT
(Figure 2) and a TFT array (Figure 1) obtained by arranging a plurality of such inverted TFTs on an insulating substrate. The plurality of TFTs 1 are arranged on a transparent insulating substrate 2, such as glass, in the form of a matrix. Gate electrodes 3 of each TFT 1 are commonly connected though gate line 4 so as to form select lines of the array. Source electrodes 5 of each TFT 1 are commonly connected to source lines 6 to form data lines of the array. Drain electrode 7 of each TFT 1 is connected to a transparent electrode 8 which is formed as a rectangular pixel output pad between the gate lines 4 and source lines 6 of the array.
Turning to the cross-sectional view of Figure 2, the profile of a TFT 1 is shown comprising a series of overlapping layers. The metallic gate electrode 3 is deposited on transparent glass substrate 2. A gate insulator layer 9 is then deposited on the glass substrate 2 so as to overly the gate electrode 3. The gate insulating layer 9 may consist of silicon oxide or silicon nitride, or other suitable insulating material.
Next, the source and drain electrodes 5 and 7 are deposited on the gate insulating layer 9, and a layer of semiconductor material 10 is then deposited so as to overlap the source and drain electrodes 5 and 7, forming a thin-film semiconductor channel therebetween.
The prior art pixel cell design shown in Figure 3 corresponds to the structure of Figure 1, and includes a storage capacitor 12 which is formed by the overlap of the output pad 8 with a previously scanned gate.
Finally, a passivation layer il is deposited over the entire structure.
In order to cause the semiconductor layer 10 to overlap the source and drain electrodes, the semiconductor layer must be thicker than the thickness of the metallic source and drain electrodes 5 and 7. In order to avoid the deposition of an excessively thick semiconductor layer which would be inappropriate for thin film applications, the metallic contacts 5 and 7 are made thin. However, according to the prior art, for large displays, the data lines must be built up at source or data lines in order to provide sufficient current carrying capabilities. Therefore, according to the prior art TFT design of Figure 2, an additional lithography step is required to add thicker metal to region 6.
Other disadvantages of the illustrated prior art TFT
are that the thin metal source and drain electrodes 5 and 7 can become contaminated in the time between the lithography step implemented to deposit these layers and the time that semiconductor layer 10 is deposited thereover. In order to remove the contaminated areas, ion beam etching or sputter etching is required to remove the contamination. Unfortunately, these additional etching procedures can cause damage to the interface between the semiconductor layer 10 and oxide layer 9.
Furthermore, when the semiconductor layer 10 is deposited and patterned, it must be crystallized since it is formed from polycrystaline material. During the crystallizing step, the semiconductor material is subjected to high temperatures which can cause diffusion of the metallic source and drain contacts into the semiconductor material, thereby shortening the active channel length of the TFT 1.
The TFT design of the present invention avoids the extra metal lithography step required during fabrication of the illustrated prior art TFT. The TFT design of the present invention also minimizes any contamination of the source and drain contacts, thereby alleviating the necessity to conduct ion beam etching or sputter etching for cleaning the contacts. Finally, the TFT design according to the present invention avoids unwanted diffusion of the metallic source and drain contact material into the semiconductor.
Turning now to Figures 4a, 4b and 4c illustrating the fabrication steps according to the present invention, a layer of chromium (Cr) is deposited on a CorningTM 7059 glass substrate 13, and patterned to form gate electrode 14. A 5000 A film of PECVD SiOX, serving as the gate insulator 15, is then deposited, followed by a 500A layer of the evaporated CdSe semiconductor. After annealing, the semiconductor layer 16 is patterned and then passivated with a SiOX layer 17. Following this, indium tin oxide (ITO) is deposited and patterned to form the pixel output pad 18.
The final two steps in the process of the present invention are to open up contact vias 19a and 20a in the passivation oxide, deposit the source/drain metal, and pattern the metal to form the source and drain electrodes 19 and 20.
The contact vial are formed by a dry etch process using reactive gases. Since conductivity properties of the semi-IS conductor are disturbed when the semiconductor is uncovered as a result of the reactive ion etch, i.e. bulk doping occurs, a sputter etch is performed, according to the present invention, to etch away contaminated areas. Accordingly, the reactive ion etch to form the source and drain vial results in bulk doping of the semiconductor while etching. By the time reactive etching is completed, the source and drain areas are adequately doped to allow instant ohmic contact when the metal electrode contacts are deposited. Therefore, an extra doping step is not required. A final anneal is then performed to ensure good ohmic contact between the semiconductor 16 and the source and drain electrodes 19 and 20.
Since the source and drain electrodes 19 and 20 are contacted to the semiconductor later 16 as the last step of the process according to the present invention, unwanted diffusion of the source and drain metal into the semiconductor layer is eliminated. The source and drain electrodes 19 and 20 can easily be made as thick as required for achieving proper current carrying capabilities, since the prior art problem of step coverage of the semiconductor over the source and drain electrodes does not arise in the TFT design according to the present invention. Furthermore, the problem of organic contamination of the source and drain contacts which results from residual lift-off photoresist in the fabrication process according to the prior art, does not occur in the process according to the present invention WO 94113019 ~ I 5 0 6 7 9 PCT/CA92100520 since the via holes 19a and 20a are formed by an etch process.
Typical I-V characteristics for the TFT of the present invention are shown in Figure 5.
The highest temperature used in the process according to the present invention is 400°C., allowing for the use of readily available low cost substrates.
Proximity printing is effected using lithographic exposure to pattern each layer, resulting in the creation of features with as little as 12 micron resolution.
Turning to Figure 6, the overall construction of a liquid crystal cell according to the present invention, is shown in profile. The active matrix LCD (AMLCD) comprises a plurality of TFT devices as shown in Figure 4c arranged on a polarizer~2l. Liquid crystal material 23 (i.e. nematic liquid) is confined between alignment layers 22 and 24.
A glass substrate 31 and top polarizer 32 are provided, onto which a black chromium (CrOX) grid 27 is deposited and patterned to form a light shielding/contrast enhancement layer. Then, the first colour filter (e. g. red filter 28) is spun on, patterned and cured. This process is then repeated for the next two colours (e. g. green filter 29 and blue filter 30).
The colour filters 28-30 are fabricated using dyed polyimide material. Finally, the filter is planarized with clear polyimide to form planarization layer 26 and then deposited with ITO layer 25 which forms the back plane electrode.
The colour AMLCD of Figure 6, using CdSe TFTs according to the present invention, has applications in military land vehicles and avionics. However, it is contemplated that commercial applications of the invention are, in fact, extremely broad, including displays for lap top and desk top computers, and other applications in which an active matrix display may be used to replace a CRT. The drive electronics (not shown) SUBSTITiJTE SHEET
21506'9 used to ccztrol the display can be identical to those used in prior art amorphous silicon AMLCDs. Furthermore, the TFT fabrication process according to the present invention utilizes equipment and methods common to the amorphous silicon process, the main exceptions being that CdSe is evaporated instead of plasma deposited as in the prior art amorphous silicon technology, and that proximity printing is used due to the larger features possible with the CdSe design.
It is believed that this compatibility with existing amorphous silicon fabrication techniques and driver chip technology, coupled with the increasingly apparent limitations of prior art amorphous silicon TFTs, will speed the development of new applications for CdSe based AMLCDs such as discussed herein throughout avionics and other industries requiring thin film AMLCDs.
Other embodiments and variations of the invention are possible within the sphere and scope of the claims appended hereto.
SUBSTITUTE SHEET
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Turning to the cross-sectional view of Figure 2, the profile of a TFT 1 is shown comprising a series of overlapping layers. The metallic gate electrode 3 is deposited on transparent glass substrate 2. A gate insulator layer 9 is then deposited on the glass substrate 2 so as to overly the gate electrode 3. The gate insulating layer 9 may consist of silicon oxide or silicon nitride, or other suitable insulating material.
Next, the source and drain electrodes 5 and 7 are deposited on the gate insulating layer 9, and a layer of semiconductor material 10 is then deposited so as to overlap the source and drain electrodes 5 and 7, forming a thin-film semiconductor channel therebetween.
The prior art pixel cell design shown in Figure 3 corresponds to the structure of Figure 1, and includes a storage capacitor 12 which is formed by the overlap of the output pad 8 with a previously scanned gate.
Finally, a passivation layer il is deposited over the entire structure.
In order to cause the semiconductor layer 10 to overlap the source and drain electrodes, the semiconductor layer must be thicker than the thickness of the metallic source and drain electrodes 5 and 7. In order to avoid the deposition of an excessively thick semiconductor layer which would be inappropriate for thin film applications, the metallic contacts 5 and 7 are made thin. However, according to the prior art, for large displays, the data lines must be built up at source or data lines in order to provide sufficient current carrying capabilities. Therefore, according to the prior art TFT design of Figure 2, an additional lithography step is required to add thicker metal to region 6.
Other disadvantages of the illustrated prior art TFT
are that the thin metal source and drain electrodes 5 and 7 can become contaminated in the time between the lithography step implemented to deposit these layers and the time that semiconductor layer 10 is deposited thereover. In order to remove the contaminated areas, ion beam etching or sputter etching is required to remove the contamination. Unfortunately, these additional etching procedures can cause damage to the interface between the semiconductor layer 10 and oxide layer 9.
Furthermore, when the semiconductor layer 10 is deposited and patterned, it must be crystallized since it is formed from polycrystaline material. During the crystallizing step, the semiconductor material is subjected to high temperatures which can cause diffusion of the metallic source and drain contacts into the semiconductor material, thereby shortening the active channel length of the TFT 1.
The TFT design of the present invention avoids the extra metal lithography step required during fabrication of the illustrated prior art TFT. The TFT design of the present invention also minimizes any contamination of the source and drain contacts, thereby alleviating the necessity to conduct ion beam etching or sputter etching for cleaning the contacts. Finally, the TFT design according to the present invention avoids unwanted diffusion of the metallic source and drain contact material into the semiconductor.
Turning now to Figures 4a, 4b and 4c illustrating the fabrication steps according to the present invention, a layer of chromium (Cr) is deposited on a CorningTM 7059 glass substrate 13, and patterned to form gate electrode 14. A 5000 A film of PECVD SiOX, serving as the gate insulator 15, is then deposited, followed by a 500A layer of the evaporated CdSe semiconductor. After annealing, the semiconductor layer 16 is patterned and then passivated with a SiOX layer 17. Following this, indium tin oxide (ITO) is deposited and patterned to form the pixel output pad 18.
The final two steps in the process of the present invention are to open up contact vias 19a and 20a in the passivation oxide, deposit the source/drain metal, and pattern the metal to form the source and drain electrodes 19 and 20.
The contact vial are formed by a dry etch process using reactive gases. Since conductivity properties of the semi-IS conductor are disturbed when the semiconductor is uncovered as a result of the reactive ion etch, i.e. bulk doping occurs, a sputter etch is performed, according to the present invention, to etch away contaminated areas. Accordingly, the reactive ion etch to form the source and drain vial results in bulk doping of the semiconductor while etching. By the time reactive etching is completed, the source and drain areas are adequately doped to allow instant ohmic contact when the metal electrode contacts are deposited. Therefore, an extra doping step is not required. A final anneal is then performed to ensure good ohmic contact between the semiconductor 16 and the source and drain electrodes 19 and 20.
Since the source and drain electrodes 19 and 20 are contacted to the semiconductor later 16 as the last step of the process according to the present invention, unwanted diffusion of the source and drain metal into the semiconductor layer is eliminated. The source and drain electrodes 19 and 20 can easily be made as thick as required for achieving proper current carrying capabilities, since the prior art problem of step coverage of the semiconductor over the source and drain electrodes does not arise in the TFT design according to the present invention. Furthermore, the problem of organic contamination of the source and drain contacts which results from residual lift-off photoresist in the fabrication process according to the prior art, does not occur in the process according to the present invention WO 94113019 ~ I 5 0 6 7 9 PCT/CA92100520 since the via holes 19a and 20a are formed by an etch process.
Typical I-V characteristics for the TFT of the present invention are shown in Figure 5.
The highest temperature used in the process according to the present invention is 400°C., allowing for the use of readily available low cost substrates.
Proximity printing is effected using lithographic exposure to pattern each layer, resulting in the creation of features with as little as 12 micron resolution.
Turning to Figure 6, the overall construction of a liquid crystal cell according to the present invention, is shown in profile. The active matrix LCD (AMLCD) comprises a plurality of TFT devices as shown in Figure 4c arranged on a polarizer~2l. Liquid crystal material 23 (i.e. nematic liquid) is confined between alignment layers 22 and 24.
A glass substrate 31 and top polarizer 32 are provided, onto which a black chromium (CrOX) grid 27 is deposited and patterned to form a light shielding/contrast enhancement layer. Then, the first colour filter (e. g. red filter 28) is spun on, patterned and cured. This process is then repeated for the next two colours (e. g. green filter 29 and blue filter 30).
The colour filters 28-30 are fabricated using dyed polyimide material. Finally, the filter is planarized with clear polyimide to form planarization layer 26 and then deposited with ITO layer 25 which forms the back plane electrode.
The colour AMLCD of Figure 6, using CdSe TFTs according to the present invention, has applications in military land vehicles and avionics. However, it is contemplated that commercial applications of the invention are, in fact, extremely broad, including displays for lap top and desk top computers, and other applications in which an active matrix display may be used to replace a CRT. The drive electronics (not shown) SUBSTITiJTE SHEET
21506'9 used to ccztrol the display can be identical to those used in prior art amorphous silicon AMLCDs. Furthermore, the TFT fabrication process according to the present invention utilizes equipment and methods common to the amorphous silicon process, the main exceptions being that CdSe is evaporated instead of plasma deposited as in the prior art amorphous silicon technology, and that proximity printing is used due to the larger features possible with the CdSe design.
It is believed that this compatibility with existing amorphous silicon fabrication techniques and driver chip technology, coupled with the increasingly apparent limitations of prior art amorphous silicon TFTs, will speed the development of new applications for CdSe based AMLCDs such as discussed herein throughout avionics and other industries requiring thin film AMLCDs.
Other embodiments and variations of the invention are possible within the sphere and scope of the claims appended hereto.
SUBSTITUTE SHEET
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Claims (3)
PROPERTY OF PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of fabricating a thin film transistor, comprising the steps of:
a) providing a substrate;
b) depositing a gate electrode on said substrate;
c) depositing a gate insulator layer on said substrate so as to overly said gate electrode;
d) depositing a thin film semiconductor channel layer on said gate insulator layer so as to be substantially aligned with said gate electrode;
e) depositing a passivation layer on said gate insulator layer so as to overly said thin film semiconductor channel layer;
f) etching a pair of via holes through said passivation layer to said semiconductor channel layer; and g) depositing a pair of source and drain electrodes on said passivation layer so as to extend through said via holes for contacting said semiconductor channel layer.
a) providing a substrate;
b) depositing a gate electrode on said substrate;
c) depositing a gate insulator layer on said substrate so as to overly said gate electrode;
d) depositing a thin film semiconductor channel layer on said gate insulator layer so as to be substantially aligned with said gate electrode;
e) depositing a passivation layer on said gate insulator layer so as to overly said thin film semiconductor channel layer;
f) etching a pair of via holes through said passivation layer to said semiconductor channel layer; and g) depositing a pair of source and drain electrodes on said passivation layer so as to extend through said via holes for contacting said semiconductor channel layer.
2. The method of claim l, wherein said step of etching said pair of via holes comprises subjecting said passivation layer to at least one reactive ion etching gas, resulting in simultaneous doping of an area of said semiconductor where said source and drain electrodes are to be formed through said via holes.
3. The method of claim 2, further comprising sputter etching said semiconductor layer for cleaning contamination prior to depositing said pair of source and drain electrodes.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6512599A JPH08511130A (en) | 1992-12-01 | 1992-12-01 | Improved structure for CdSe thin film transistor |
| PCT/CA1992/000520 WO1994013019A1 (en) | 1992-12-01 | 1992-12-01 | IMPROVED STRUCTURE FOR CdSe TFT |
| CA002150679A CA2150679C (en) | 1992-12-01 | 1992-12-01 | Improved structure for cdse tft |
| EP92923643A EP0672302A1 (en) | 1992-12-01 | 1992-12-01 | IMPROVED STRUCTURE FOR CdSe TFT |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CA1992/000520 WO1994013019A1 (en) | 1992-12-01 | 1992-12-01 | IMPROVED STRUCTURE FOR CdSe TFT |
| CA002150679A CA2150679C (en) | 1992-12-01 | 1992-12-01 | Improved structure for cdse tft |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2150679A1 CA2150679A1 (en) | 1994-06-09 |
| CA2150679C true CA2150679C (en) | 2000-01-11 |
Family
ID=25677986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002150679A Expired - Fee Related CA2150679C (en) | 1992-12-01 | 1992-12-01 | Improved structure for cdse tft |
Country Status (2)
| Country | Link |
|---|---|
| CA (1) | CA2150679C (en) |
| WO (1) | WO1994013019A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6043113A (en) * | 1995-07-31 | 2000-03-28 | 1294339 Ontario, Inc. | Method of forming self-aligned thin film transistor |
| CN104020621B (en) * | 2014-05-26 | 2017-03-01 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5010027A (en) * | 1990-03-21 | 1991-04-23 | General Electric Company | Method for fabricating a self-aligned thin-film transistor utilizing planarization and back-side photoresist exposure |
-
1992
- 1992-12-01 WO PCT/CA1992/000520 patent/WO1994013019A1/en not_active Application Discontinuation
- 1992-12-01 CA CA002150679A patent/CA2150679C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| WO1994013019A1 (en) | 1994-06-09 |
| CA2150679A1 (en) | 1994-06-09 |
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