JP2742725B2 - Display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active display device, particularly to an active liquid crystal display device, in which two thin films of a P-channel type and an N-channel type are complementary to each pixel. A pixel is constituted by providing a type insulating gate field effect transistor (hereinafter referred to as TFT), and an output voltage having the same phase as the gate voltage is supplied to the pixel. In order to compensate for this, two or more pixels and / or complementary thin film transistors (hereinafter referred to as C / TFTs) are used.

[Related Art] Conventionally, an active liquid crystal display device using a TFT has been known. In this case, a semiconductor having an amorphous or polycrystalline structure is used for the TFT, and a TFT having only one of the P and N conductivity types is used for one pixel.
That is, generally, an N-channel TFT (referred to as NTFT) is serially connected to a pixel. FIG. 1 shows a typical example.

In FIG. 1, a liquid crystal (12) was provided, and an NTFT (11) was provided in series with the liquid crystal (12), which was arranged in a matrix. Generally, 640 x 480 or 1260 x 960, but
In this drawing, a 2 × 2 matrix is simply arranged in the same meaning. A peripheral circuit (1
Voltages were applied from (6) and (17) to selectively turn on predetermined pixels and turn off other pixels. Then this TFT (11)
In general, when the on / off characteristics of the device are good, a liquid crystal display device having a large contrast can be manufactured. However, when actually manufacturing such a liquid crystal display device, when the output of the TFT, that is, the input to the liquid crystal (the liquid crystal potential), the voltage V _LC (1
0) is often “1” (Hig) when it should be “1” (High)
h), and conversely, it does not become “0” (Low) when it should become “0” (Low). The liquid crystal (12) is inherently insulating in its operation, and the liquid crystal potential (V _LC ) floats when the TFT is off. Since this liquid crystal (12) is equivalently a capacitor, the charge stored there
_VLC is determined. May become the charge liquid is a relatively small resistance R _LC, dust, there when R _GS (15) is caused by leakage or, also pinholes of the gate insulating film of the TFT due to the presence of ionic impurities Charge leaks from _VLC
Will be in an incomplete state. Therefore, in a liquid crystal display device having 200,000 to 5,000,000 pixels in one panel, a high yield cannot be achieved. In particular, the liquid crystal (12) is generally TN (twinted nematic)
Liquid crystal is used. A rubbed alignment film is provided on each electrode to align the liquid crystal. Weak dielectric breakdown occurs due to static electricity generated by this rubbing process,
Leakage between adjacent pixels or between adjacent wires,
In addition, the gate insulating film is weak and leaks.

In an active-type liquid crystal display device, it is extremely important to keep the liquid crystal potential at the same level as the initial value for one frame to keep a predetermined level. However, in reality, there are many defects and it is not always the case.

[Object of the Invention] The present invention solves such a problem and increases the current margin, that is, increases the response speed. In addition, the potential of the pixel in each pixel, that is, the liquid crystal potential _VLC is fixed to “1” and “0” sufficiently and stably so that the level does not drift during one frame.

Further, by setting the voltage applied to each pixel to an intermediate value between “1” and “0”, a halftone (gray scale) is displayed.

“Constitution of the Invention” The present invention relates to an active-type display device, particularly an active-type liquid crystal display device, in which an electrode constituting one pixel of each pixel, for example, a TF complementary to an electrode of a transparent conductive film.
This is a connection of the output terminals of T. The invention also relates to a driving method in which an output voltage having the same phase as the input voltage is supplied to a pixel. That is, a P-channel type TFT (hereinafter PTFT)
) And NTFT are connected to the output of a complementary type (hereinafter, referred to as C / TFT) to a pixel to constitute one of the pixels.

One pixel may be configured by connecting two or more C / TFTs to one pixel. Furthermore, one pixel is divided into two or more, and C / TF
One or more Ts may be connected.

Representative examples of the present invention are shown as circuit diagrams in FIG. 2, FIG. 3, and FIG. Examples of actual pattern layouts (arrangement diagrams) are shown in FIGS. 6, 7, and 8, respectively.

NTFT and PTFT in the 2 × 2 matrix example in FIG.
Are connected to each other, and further connected to V _GG (22) or V _GG ′ (22 ′), which is referred to as a line Y in the Y-axis direction. The common output terminal of the C / TFT is connected to the liquid crystal (12). NTF
The input end of T (V _DD side) is called the X-axis direction line X-ray) V _DD
(18), connected to V _DD '(18') and
_SS side) is connected to Vss (19) and Vss '(19').
Then, when V _DD (18) and V _GG (22) are “1”, the liquid crystal potential (V _LC ) (10) becomes “1”, and V _DD (18) becomes “1” and V _DD (18).
_{When GG} (22) is “0”, the liquid crystal potential (10) becomes “0”. The pixel (12) of the liquid crystal (12) is turned on when it becomes "1" with respect to the opposite electrode (23) (generally, the ground potential (13)). Conversely, when the liquid crystal potential (10) is "0", the liquid crystal is turned off.

As described above, since the liquid crystal potential (V _LC ) (10) can be fixed to either V _DD (18) or V _SS (19), it does not float.

In the example of FIG. 3, X-rays V _DD (18), Vss (19),
For V _DD ′ (18 ′) and Vss ′ (19 ′), the Y line is V _GG (2
2), V _GG ′ (22 ′) is converted to NTFT (1
1), PTFT (21), NTFT (11 ') that constitutes the second C / TFT,
PTFT (21 ') was commonly linked to V _GG (22). Also, the output of the two C / TFTs is shared and one liquid crystal (1
It is connected to the pixel (33) which is one electrode of 2).
Thus, even if one of the two NTFTs or the two PTFTs leaks somewhat, the pixels can be driven because they have the same phase.

FIG. 4 shows that one pixel (34) has two pixels (33), (33 ') and two C / TFTs corresponding to each pixel.
Are provided. The gate electrode of the two C / TFTs is made common, and the first input is performed. The input of each NTFT and each PTFT of each C / TFT is connected to V _DD (1
8), connected to Vss (19). By doing so, one of the two pixels in one pixel is in the same phase due to a defect such as TFT leak, so that it does not become inactive,
Even if the operation is delayed, the other operates normally, so that the defect is less noticeable in the matrix configuration operation.

 Hereinafter, the present invention will be described based on examples.

Example 1 This example is for configuring Examples 2, 3, and 4, and is shown using FIG.

The manufacturing process when forming a C / TFT on a glass substrate will be described with reference to FIGS. 9 (A) to 9 (F).

In FIG. 9 (A), a quartz glass or the like that can withstand a heat treatment of 700 ° C. or less, for example, about 600 ° C. such as NO glass (manufactured by Nippon Electric Glass), LE-30 (manufactured by HOYA), Vycor 7913 (manufactured by Corning), Magnetron RF on inexpensive glass
A silicon oxide film as a blocking layer (36) was formed to a thickness of 1000 to 3000 ° by (high frequency) sputtering.

The process conditions were a 100% oxygen atmosphere, a film formation temperature of 150 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The deposition rate using quartz or single crystal silicon as the target was 30 to 100 ° / min.

A silicon film was formed thereon by an LPCVD (low pressure gas phase) method, a sputtering method, or a plasma CVD method.

When formed by the reduced pressure gas phase method, 100 to 2
00 ° C. lower 450 to 550 ° C., for example 530 ° C. In disilane (Si ₂ H ₆₎
Alternatively, trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus to form a film. The pressure in the reactor was 30 to 300 Pa. Deposition rate is 50-2
It was 50Å / min. In order to control the threshold voltage (Vth) of NTET and PTFT substantially the same, boron may be added during film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane.

When performing the sputtering method, the back pressure before sputtering is 1 × 10 ^-5
The pressure was set to Pa or less, and a single crystal silicon was used as a target in an atmosphere in which hydrogen was mixed with 20 to 80% of argon. For example, argon was 20% and hydrogen was 80%. The film formation temperature was 150 ° C., the frequency was 13.56 MHz, and the sputter output was 400 to 800 W. The pressure was 0.5 Pa.

When a silicon film is formed by a plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into the PCVD equipment, and 13.
The film was formed by applying a high frequency power of 56 MHz.

Coatings formed by these methods have an oxygen content of 5 ×
It is preferably 10 ²¹ cm ⁻³ or less. If the oxygen concentration is high, crystallization is difficult, and the thermal annealing temperature must be increased or the thermal annealing time must be increased. If the amount is too small, the leakage current in the off state increases due to the backlight. Therefore, the range was set to 4 × 10 ¹⁹ to 4 × 10 ²¹ cm ⁻³ . Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon is 4 × 10 ²² cm ^-3
Was 1 atomic%.

In the present invention, in order to further promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less, and a TFT constituting a pixel is formed.
Oxygen only in the channel formation region of
You may add so that it may be set to * 10 < ²⁰ > -5 * 10 < ²¹ > cm < ^-3 >.

At this time, since light is not irradiated to the TFTs constituting the peripheral circuit, it is effective to reduce the mixing of oxygen and to have a higher carrier mobility for high-frequency operation.

Thus, the amorphous silicon film is formed in a range of 500 to 5000
After being formed to a thickness of, for example, 1500 °, a heat treatment at a medium temperature in a non-oxide atmosphere was performed at a temperature of 450 to 700 ° C. for 12 to 70 hours. For example, it was kept at a temperature of 600 ° C. in a nitrogen or hydrogen atmosphere.

Since a silicon oxide film having an amorphous structure is formed on the substrate surface below the silicon film, no specific nucleus is present in this heat treatment, and the whole is uniformly heat-annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

By the annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and a part thereof exhibits a crystalline state. In particular, a region having a relatively high order at the time of forming a silicon film is particularly likely to be crystallized to be in a crystalline state. However, since the silicon existing between these regions is bonded to each other, silicon mutually pulls each other. When measured by laser Raman spectroscopy, a peak shifted from the single crystal silicon peak 522 cm ^-1 to a lower frequency side is observed. Calculated from its half-width, the apparent particle size is 50 to 500 mm, which is like a microcrystal.In fact, there are many regions with high crystallinity and a cluster structure. A film having a semi-amorphous structure bonded (anchored) by silicon was able to be formed.

As a result, the coating is substantially grain boundary (GB
). Carriers can easily move from one cluster to another through anchored locations, resulting in higher carrier mobility than so-called GB polycrystalline silicon. That is, hole mobility (μh) = 10 to ²⁰⁰ cm ² / Vsec, electron mobility (μ
e) = 15-300 cm ² / Vsec is obtained.

On the other hand, instead of annealing at medium temperature as described above, 900-1
When the film is polycrystallized by high temperature annealing at 200 ° C, segregation of impurities in the film occurs due to solid phase growth from the nucleus.
GB has many impurities such as oxygen, carbon, and nitrogen, and has a high mobility in the crystal. However, a barrier is formed in the GB to hinder the movement of carriers there. As a result 10
The reality is that mobility of cm ² / Vsec or more cannot be easily obtained.

That is, in the embodiment of the present invention, a silicon semiconductor having a semi-amorphous or semi-crystalline structure is used for such a reason.

In FIG. 9 (A), the silicon film is subjected to photo-etching using a first photomask, and a PTFT region (21) (channel width 20 μm) is on the right side of the drawing, and an NTFT region (11) is on the left side. Prepared.

On this, a silicon oxide film is used as a gate insulating film of 500 to 2000
It was formed to a thickness of {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix the sodium ions.

Thereafter, a silicon film containing phosphorus in a concentration of 1 to 5 × 10 ²¹ cm ⁻³ or a silicon film having molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ thereon.
Was formed. This was patterned using a second photomask to obtain FIG. 9 (B). A gate electrode (4) for PTFT and a gate electrode (4 ') for NTFT were formed. For example, a channel length is 10 μm, phosphorus-doped silicon is formed as a gate electrode at 0.2 μm, and molybdenum is formed thereon at a thickness of 0.3 μm.

In FIG. 9 (C), a photoresist (31 ') is formed using a photomask, and a source (5),
A dose of boron of 1 to 5 × 10 ¹⁵ cm ⁻² was added to the drain (6) by ion implantation.

Next, as shown in FIG. 9D, a photoresist (31) was formed using a photomask. 1-5 × 10 ¹⁵ phosphorus as source (5 ′) and drain (6 ′) for NTFT
An amount of cm ⁻² was added by ion implantation.

These were performed through the gate insulating film (3). However, in FIG. 6B, the silicon oxide on the silicon film may be removed using the gate electrodes (4) and (4 ') as a mask, and then boron and phosphorus may be directly ion-implanted into the silicon film.

Next, heat annealing was performed again at 600 ° C. for 10 to 50 hours. The source (5) and drain (6) of PTFT and the source (5 ') and drain (6') of NTFT are activated with impurities.
These were prepared as P ⁺ and N ⁺ .

Under the gate electrodes (4) and (4 '), channel forming regions (7) and (7') are formed as semi-amorphous semiconductors.

Thus, even though the self-alignment method is used, 70
C / TFT without adding temperature in all processes above 0 ℃
Can be made. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and this is a process very suitable for the large pixel liquid crystal display device of the present invention.

Thermal annealing was performed twice in FIGS. 9A and 9D. However, the annealing in FIG. 9 (A) may be omitted depending on the required characteristics, and both may be omitted by the annealing in FIG. 9 (D) to shorten the manufacturing time. In FIG. 9E, an interlayer insulator (8) was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD,
A VD method and a normal pressure CVD (TEOS-ozone) method may be used. For example, it was formed to a thickness of 0.2 to 0.6 μm, and thereafter, a window (32) for an electrode was formed using a photomask.

Further, aluminum is formed on the entire surface by sputtering, and leads (9), (9 ') and contacts (2) are formed.
9) and (29 ') were fabricated using a photomask.

An organic resin (39) for flattening, for example, a translucent polyimide resin was applied to the surface, and a hole was formed in the electrode again using a photomask.

As shown in FIG. 9 (F), in order to make the two TFTs complementary and to connect the output terminal thereof to the electrode of one pixel of the liquid crystal device as a transparent electrode, ITO (indium tin oxide film) is formed by sputtering. Was formed. It was etched using a photomask to form an electrode (33). This ITO was formed at room temperature to 150 ° C. and achieved by annealing at 200 to 400 ° C. in oxygen or atmosphere.

Thus, the PTFT (21), the NTFT (11), and the transparent conductive film electrode (33) were formed on the same glass substrate (1).

 The characteristics of such a TFT will be abbreviated.

Mobility (μcm ² / Vs) Vth (V) PTFT 20 −5.9 NTFT 40 +5.0 By using such a semiconductor, a large mobility could be produced even with a TFT which was generally considered impossible. Therefore, for the first time, an active-type liquid crystal display device in which each pixel of the liquid crystal display device shown in FIGS. 2, 3 and 4 has a complementary TFT in each pixel can be manufactured. Peripheral circuits can also be turned on glass (a method of forming TFTs on the same substrate by the same TFT manufacturing process).

Embodiment 2 FIG. 6A shows an embodiment corresponding to FIG. V _DD (18), V _SS (19), V _DD '(18'), V _SS '
(19 ') was formed. V _GG (22), V _GG ′
(22) was formed.

FIG. 6 (A) is a plan view, and FIG. 6 (B) is a longitudinal sectional view taken along the line AA ′. FIG. 6C shows a vertical sectional view taken along line BB '.

NTFT (11) is provided at the intersection of X-ray V _DD (18) and Y-ray V _GG (22), and at the intersection of V _DD (18) and V _GG ′ (22 ′) for other pixels. NTFT (11 ') is similarly provided. PTFT
(21) is provided at the intersection of V _SS (19) and V _GG (22). Below the intersection of V _DD '(18') and V _GG (22), an NTFT for another pixel is provided. It has a matrix configuration using C / TFT.

The NTFT (11) is connected to the X-ray V _DD (18) via the contact (32) at the input terminal of the drain (6 '), and the gate (4) is connected to the multilayered Y-ray V _GG (22). Are linked. The output terminal of the source (5 ') is connected to the pixel electrode (33) via the contact (29).

On the other hand, the input terminal of the drain (6) of the PTFT (21) is connected to the X-ray V _SS (19) through the contact (32 '), and the gate (4) is connected to the Y-line V _GG (22) and the source ( The output terminal of 5) is connected to the pixel (33) via the contact (29 '). Thus, between the two X-rays (18) and (19) (inside), one pixel was constituted by the pixel (33) made of a transparent conductive film and the C / TFT.

By repeating such a structure left, right, up and down, 2 ×
One example of 2 matrix or 640x4 which expanded it
It has become possible to make liquid crystal display devices with large pixels of 80, 1280 x 960.

6 (B) and 6 (C) correspond to the numbers in FIG. 9 (F).

The feature here is that two TFTs are provided in one pixel in a complementary configuration, and the pixel (33) is a liquid crystal potential V _LC
However, under the condition that the gate voltage is higher than the drain voltage, the gate voltage is fixed to the value of the gate voltage −Vth.

 The operation is abbreviated using FIG.

In the pair of electrodes (33) and (23) sandwiching the liquid crystal (12), the other electrode (23) is set to the ground potential (13), and the input terminal of the NTFT (11) is connected to V _DD (19) Is + 10V, for example, and Vss (18) to which the input terminal of the PTFT (21) is connected is −10V, for example, V _1C (10) is fixed at a voltage of V _GG −Vth. Furthermore, V _GG can be varied from 20 to 10V, and when Vth is 5.0V,
The output has the same polarity and varies from 15 to 5V. By changing the value of _VGG according to the degree of driving of each pixel as compared with the conventionally known liquid crystal device using only the NTFT shown in FIG. Has been found to be possible, ie a gray scale. That is
V _DD (18), Vss (19), and ground (13) can be set for three types of potentials, indicating that one more control element has been added.

In addition, as is apparent from FIG. 6, the control element Vss (19)
However, the number of Vss wires only increases by one line as X-rays, and the aperture ratio (the ratio of the area (33) of the liquid crystal actually displayed to the total area (34)) of the liquid crystal device is the same as the conventional one. 1 is not greatly reduced as compared with the case where only one conductivity type TFT of FIG. 1 is connected to each pixel, and is not so disadvantageous.

In FIG. 6, considering the wiring of V _GG (22),
By using an aluminum wiring (41) as an overline wiring (upper wiring), an underline wiring (43) (lower wiring) made of the same material as the gate electrode and their contacts (42), X-ray and Y-ray It is no longer necessary to increase the number of new photomasks for multilayer wiring at the intersection.

In FIG. 6, an alignment film and an alignment treatment are performed on the transparent conductive film, and the substrate and the other liquid crystal electrode (the fifth
The substrates having the structure shown in FIG. 23 are arranged at a constant interval from each other by a known method. In the meantime, liquid crystal was injected or wiring was completed.

If TN liquid crystal is used for the liquid crystal material, the interval should be about 10μ.
m, and it is necessary to form an alignment film on both transparent conductive films by rubbing.

When FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is ± 20 V and the cell interval is 1.5 to 3.5 μm.
For example, the thickness may be set to 2.3 μm, an alignment film may be provided only on the opposite electrode (FIG. 4) (34), and rubbing may be performed.

When a dispersion type liquid crystal or a polymer liquid crystal is used, an alignment film is unnecessary and a switching speed is increased.
The operating voltage was ± 10 to ± 15 V, and the cell spacing was as thin as 1 to 10 μm.

In particular, when a dispersion type liquid crystal is used, since a polarizing plate is not required, the amount of light can be increased both in a reflection type and in a transmission type. Since the liquid crystal does not have a threshold, as shown in the C / TFT of the present invention, by using a C / TFT type in which a clear threshold voltage is defined, a large contrast and crosstalk (bad with a neighboring pixel) are obtained. Interference) could be eliminated.

"Embodiment 3" This embodiment corresponds to FIGS. 3 and 7. FIG.

As is clear from this drawing, the _VGG (22) of the Y line is disposed at the center, and the portion sandwiched between _VDD (18) and Vss (19) of the X line is one pixel (34). One pixel consists of one transparent conductive pixel (33) and two NTFTs (1
1), (11 '), and two C / TFTs composed of two PTFTs (21), (21'). Gate electrodes are all V _GG
(22) and the two NTFTs (11) and (11 ') are V _DD
(18), and the two PTFTs (21) and (21 ') are Vss (1
9) is connected. One of these two NTFTs or P
Even when one of the TFTs is defective due to a leak between the gate electrode and the channel formation region, the TFT can be operated as a pixel because it has the same phase.

Others are the same as the second embodiment, and the C / TFT uses the first embodiment.

"Embodiment 4" This embodiment corresponds to FIGS. 4 and 8. FIG. One pixel is composed of two C / TFTs and two pixels. That is, C / TFT consisting of NTFT (11) and PTFT (21)
The pixel (33) of the liquid crystal 12 connected to the output of the other NTFT (1
1 ') and a pixel (33') of the liquid crystal (12 ') connected to the output of the C / TFT comprising the PTFT (21') constitute one pixel (34). Pixels (33) and (33 ') correspond to the combined pixel (33) that constitutes one pixel.

In this way, even if one of the pixels operates only halfway, the other pixel operates normally, and when colorized, the degree of gray scale deterioration can be reduced.

In addition, what is not described in Examples 1 and 2
Is the same as that described in.

[Effects of the Invention] The present invention connects a complementary TFT to each of the pixels in a matrix to achieve 1) achievement of gray scale (halftone) 2) C / TFT output and pixel voltage such as liquid crystal potential 3) Expansion of operation margin 4) Even if some defective TFTs are in-phase output, compensation can be performed to some extent 5) The number of photomasks required for fabrication is the same as the conventional example using only NTFT 9 (C) and 9 (D).
6) Since the carrier mobility is more than 10 times larger than the case where amorphous silicon is used, the size of the TFT can be reduced and even if two TFTs are provided in one pixel. It has many features with little decrease in aperture ratio.

Therefore, active TF using only NTFT
Compared to the T liquid crystal device, it is possible to achieve several steps of production yield and the vividness of the screen.

In the present invention, semi-amorphous or semi-crystal was used as the semiconductor for the C / TFT. However, semiconductors of other crystal structures may be used if possible for the same purpose. High-speed processing was performed by a self-aligned C / TFT. However, a TFT may be formed by a non-self-aligned method without using the ion implantation method. Needless to say, the type of the TFT may be a type TFT instead of the type star.

The display medium in the present invention can be used as a transmission type liquid crystal display device or a reflection type liquid crystal display device. As the liquid crystal material, the above-mentioned TN liquid crystal, FLC liquid crystal, dispersion liquid crystal, and polymer liquid crystal can be used.

In addition, by adding an ionic dopant to a guest-host type or dielectric anisotropic type nematic liquid crystal and applying an electric field, an electric field is applied to a mixture of the cholesteric liquid crystal and the nematic liquid crystal, and the nematic phase and the cholesteric phase are mixed. A phase change liquid crystal that causes a phase change between the two and realizes a transparent or opaque display can also be used. In addition to the liquid crystal, for example, a so-called electrophoretic display dispersion system in which pigment particles having different colors are dispersed in an organic solvent colored with a dye can be used.

In the present invention, when a liquid crystal is used as a display medium, C /
The output of the TFT is the liquid crystal potential. In addition, since a medium other than liquid crystal may be used, it is generally referred to as an output voltage of a C / TFT.

[Brief description of the drawings]

FIG. 1 shows a liquid crystal device using a conventional active TFT (thin film transistor). 2, 3 and 4 are circuit diagrams of an active liquid crystal device using the complementary TFT of the present invention. FIG. 5 is a drawing showing the operation of the complementary TFT. FIG. 6 shows a plan view (A), longitudinal sectional views (B) and (C) of one substrate of the liquid crystal display device corresponding to FIG. FIG. 7 is a drawing of one substrate of the liquid crystal display device corresponding to FIG. FIG. 8 is a drawing of one substrate of the liquid crystal display device corresponding to FIG. FIG. 9 shows a method of manufacturing a complementary TFT used in the liquid crystal device of the present invention. (1) ... glass substrate (2), (2 ') ... silicon semiconductor (3) ... gate insulating film (4), (4') ... gate electrode (5), (5 ') ... source (6), (6 ') ... drain (7), (7') ... channel formation region (10) ... liquid crystal potential ( _VLC ) (11), (11 '), (11A), (11A '), (11B), (1
1B ') N-channel thin film transistor (NTFT) (12), (12'), (12A), (12A '), (12B), (1
2B ') ... Liquid crystal (14), (15) ... Resistance causing leakage (16), (17) ... Peripheral circuit (18), (18') ... V _DD (one of X-rays) ( 19), (19 ') ... Vss (one of X-rays) (21), (21'), (21A), (21A '), (21B), (2
1B ') P-channel thin film transistor (PTFT) (22), (22') _VGG , _VGG '(Y-line) (23), (33), (33'), (33A), ( 33A '), (33
B), (33B ') ... Pixel made of transparent electrode (34) ... Pixel (36) ... Blocking layer-Process using photomask

Claims (11)

(57) [Claims] 1. A substrate having an insulating surface, a plurality of thin film transistors including at least a P-channel first thin film transistor and an N-channel second thin film transistor formed on the insulating surface, A display device, wherein the gate electrodes of the first and second thin film transistors are made of phosphorus-doped silicon and a metal or metal silicide laminated thereon. 2. The phosphorous-doped silicon constituting the gate electrode contains 1
2. The display device according to claim 1, wherein phosphorus is doped in a concentration of from × 10 ^{21 to} 5 × 10 ²¹ cm ⁻³ . 3. The display device according to claim 1, wherein the metal constituting the gate electrode comprises molybdenum or tungsten. 4. The display device according to claim 1, wherein the metal silicide forming the gate electrode comprises molybdenum silicide or tungsten silicide. 5. The display device according to claim 1, wherein the first and second thin film transistors form a complementary transistor pair. 6. A display medium, one or more pixel electrodes provided on one surface of the display medium, first, second, and third control lines, and control of the first to third control lines. A control circuit for supplying a signal, wherein a source of the second thin film transistor is connected to a first pixel electrode of the pixel electrodes, and a source of the first thin film transistor is connected to the first pixel electrode or another A first electrode connected to a pixel electrode; a drain of the second thin film transistor connected to the first control line; a drain of the first thin film transistor connected to the second control line; and the first and second thin film transistors The display device according to claim 1, wherein both of the gates are connected to a third control line. 7. The display device according to claim 6, wherein the display medium is a liquid crystal. 8. The display device according to claim 6, wherein a plurality of pixel electrodes are arranged in a matrix, and one pixel electrode constitutes one pixel. 9. The display device according to claim 6, further comprising a back electrode on the other surface of the display medium, the back electrode being in close contact with the display medium, and a voltage being applied between the back electrode and the pixel electrode. . 10. A display medium on a substrate, a pixel electrode formed in close contact with the display medium, first and second control lines to which a scanning signal is supplied, and a third signal to which a data signal is supplied. And a control line, wherein a complementary transistor pair constituted by first and second thin film transistors is used as a switching element, and all gates of the first and second thin film transistors are connected to the third control line; All output terminals of the first and second thin film transistors are connected to the pixel electrode, and the source or drain of the second thin film transistor that is not connected to the output terminal is connected to the first control line. The source or the drain of the first thin film transistor that is not connected to the output terminal is connected to the second control line. Patent display range first claim of claim to. 11. A display medium on a substrate, a pixel electrode pair including two pixel electrodes formed in close contact with one surface of the display medium, two X-rays per row to which a scanning signal is supplied, And a Y line to which a data signal is supplied, wherein the first and second thin film transistors form a complementary transistor pair, each pixel electrode is connected to an output terminal of the complementary transistor pair, 2. The device according to claim 1, wherein said complementary transistor pair is connected to a source or drain other than an output terminal of the thin film transistor, and a gate of said complementary transistor pair is connected to said Y line. Display device.