JP3013259B2 - Liquid crystal display - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an active type liquid crystal display device, and in particular, to each pixel, two thin film type insulated gate field effect transistors (hereinafter referred to as TFTs) are provided in a complementary manner. Liquid crystal panel.

[Related Art] Conventionally, an active liquid crystal display device using a TFT has been known. In this case, an amorphous or polycrystalline semiconductor is used for the TFT, and a TFT having only one of the P and N conductivity types is used for one pixel. That is, generally, an N-channel TFT (referred to as NTFT) is serially connected to a pixel. FIG. 1 shows a typical example.

In FIG. 1, there is a liquid crystal (12), which is connected in series with an NTFT (11). This is a matrix arrangement. Generally 640x480 or 1260x
Although the number is increased to 960, in this drawing, a 2 × 2 matrix is simply arranged in the same meaning. A voltage is applied to each pixel from the peripheral circuits (16) and (17), a predetermined pixel is selectively turned on, and the other pixels are turned off. Then, if the on / off characteristics of this TFT are generally good,
A liquid crystal display device with high contrast can be manufactured. However, when actually manufacturing such a liquid crystal display device, the output of the TFT, that is, the voltage V _LC (10) of the input to the liquid crystal (referred to as the liquid crystal potential) is often “1” (High).
Does not become “1” (High) when it should be, and conversely “0”
(0) (Low) in some cases when it should be (Low). The liquid crystal (12) is inherently insulating in its operation,
When the TFT is off, the liquid crystal potential (V _LC ) is in a floating state. Since this liquid crystal (12) is equivalently a capacitor,
The _VLC is determined by the charge stored there. This charge liquid crystal or a relatively small resistance R _LC, dust,
If _RGS (15) occurs due to leakage due to the presence of ionic impurities or _RGS (15) due to a pinhole in the gate insulating film of the TFT, the charge leaks therefrom, and the _VLC is in an incomplete state. Therefore, in a liquid crystal display device having 200,000 to 5,000,000 pixels in one panel, a high yield cannot be achieved. In particular, the liquid crystal (12)
A TN (twisted nematic) liquid crystal is used. For the alignment of the liquid crystal, a rubbed alignment film is provided on each electrode. A weak dielectric breakdown occurs due to static electricity generated by the rubbing process, and leakage occurs between adjacent pixels or adjacent conductors, or the gate insulating film is weak and leaks. In an active-type liquid crystal display device, it is extremely important to keep the liquid crystal potential at the same level as the initial value for one frame to keep a predetermined level. However, in reality, there are many defects and it is not always the case.

When the liquid crystal material is a ferroelectric liquid crystal, a large injection current is required. For this purpose, there is a disadvantage that the current margin must be increased by increasing the TFT.

"Object of the Invention" The present invention has solved such a problem, and has a configuration in which the aperture ratio of the panel of the liquid crystal device is the same or substantially the same as that of the conventional system using one TFT even in the complementary type. .
_VLC is fixed to "1" and "0" sufficiently stably so that the level does not drift during one frame.

"Constitution of the Invention" In the present invention, an output terminal of a complementary TFT is connected to an electrode of one transparent conductive film of each pixel arranged in a matrix. That is, a P-channel TFT (hereinafter referred to as “PTFT”) and an NTF
And T are linked as a complementary type (hereinafter referred to as C / TFT).

A typical example of the present invention is shown as a circuit in FIG. FIG. 5 shows an example of an actual pattern layout (arrangement diagram).

To illustrate the present invention, an example of the 2 × 2 matrix of FIG. 2 is shown. The gates of the PTFT and the NTFT were connected to each other, and further connected to the Y-axis direction line V _GG (22) or V _GG (23). The common output of the C / TFT is connected to the liquid crystal (12). Connect the PTFT input (Vss side) to the X axis line V _DD (18), V _DD
Linked to (18 '), ground input of NTFT the (V _SS side) (1
9), (19 '). Then V _DD (18), V _GG (22)
Is “1”, the liquid crystal potential (10) becomes “0” and V _DD (1
When 8) is “1” and V _GG (22) is “0”, the liquid crystal potential (10) is “1”
Becomes And the liquid crystal pixel (12) has the opposite electrode potential (1
3) It turns on when it becomes "1" compared to (generally, ground potential). Conversely, when the liquid crystal potential (10) is "0", the liquid crystal is turned off.

Since the liquid crystal potential (10) is fixed to either V _DD (18) or ground or V _SS (19), it does not float.

In the example of the present invention shown in FIG. 3, the wiring (1
8) and (18 '), the ground terminals (19) and (19')
Wired in the axial direction. Then, (19) in FIG. 2,
V _SS (19) is obtained using (19 ′) in common. When forming a 2 × 2 matrix, V _SS (19) is a common wiring between the upper pixel and the lower pixel.

In this case, the liquid crystal potential V _LC can be fixed at V _DD or V _SS . Since it is complementary to PTFT (21) and NTFT (11), there is no problem even if there is dust or ionic leakage in _RLC (14).

Also, even if there is a small leak between the adjacent wiring, V _DD (18) or V _SS (19) constantly supplies the charge to _VLC , so the level in the frame is constant instead of floating. It can be.

 Hereinafter, the present invention will be described based on examples.

Example 1 This example is shown with reference to FIGS. 3, 5 and 6. FIG.

FIG. 6 shows a manufacturing process when a C / TFT is formed on a glass substrate.

In FIG. 6, magnetron RF is placed on a glass such as AN glass or Pyrex glass that can withstand heat treatment at about 600 ° C.
A silicon oxide film (3 ') as a blocking layer was formed to a thickness of 1000 to 3000 [deg.] By (high frequency) sputtering.

The process conditions were a 100% oxygen atmosphere, a film formation temperature of 150 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The deposition rate using quartz or single crystal silicon as the target was 30 to 100 ° / min.

Furthermore, a silicon film is formed on this by LPCVD (low pressure gas phase) method,
It was formed by a sputtering method or a plasma CVD method.

When formed by the reduced pressure gas phase method, 100 to 2
00 ° C. lower 450 to 550 ° C., for example 530 ° C. In disilane (Si ₂ H ₆₎
Alternatively, trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus to form a film. The pressure in the reactor was 30 to 300 Pa. Film formation speed 50-250
Å / min. In order to control the threshold voltage (Vth) between NTET and PTFT substantially the same, boron may be added during film formation at a concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ using diborane.

When performing the sputtering method, the back pressure before sputtering is 1 × 10 ^-5
The pressure was set to Pa or less, and the reaction was performed in an atmosphere in which hydrogen was mixed with argon to 20 to 80% using single crystal silicon as a target. For example, argon was 20% and hydrogen was 80%. The film formation temperature was 150 ° C., the frequency was 13.56 MHz, and the sputter output was 400 to 800 W. The pressure was 0.5 Pa.

When a silicon film is formed by a plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into a PCVD apparatus, and a film was formed by applying a high frequency power of 13.56 MHz.

The film formed by these methods has oxygen of 7 ×
The concentration is preferably 10 ¹⁹ cm ^-3 or less, and more preferably 1 × 10 ¹⁹ cm ^-3 or less. When making the typical crystallization,
This is because the degree of crystallization can be promoted. For example SIMS
As a result of (secondary ion mass spectrometry) method, 8 × 10 ¹⁸ cm ⁻³ of oxygen and 3 × 10 ¹⁶ cm ⁻³ of carbon were obtained. In addition, hydrogen is 4
It was × 10 ²⁰ cm ^-3 , which was 1 atomic% when compared with silicon 4 × 10 ²² cm ^-3 .

Thus, the amorphous silicon film is 500-3000Å,
For example, after making to a thickness of 1500 mm, at a temperature of 450 to 700 ° C
Medium-temperature heat treatment was performed in a non-oxide atmosphere for 12 to 70 hours. For example, it was kept at a temperature of 600 ° C. in a nitrogen or hydrogen atmosphere.

Since an amorphous silicon oxide film is formed on the surface of the substrate below the silicon film, no specific nucleus is present in this heat treatment, and the whole is uniformly heat-annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

By this annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and a part of the silicon film exhibits a crystalline state. In particular, a region having a relatively high order at the time of forming a silicon film is particularly likely to be crystallized to be in a crystalline state. However, since the silicon existing between these regions is bonded to each other, silicon mutually pulls each other. When the crystal is measured by laser Raman spectroscopy, a peak shifted from the single crystal silicon peak 522 cm ^-1 to a lower frequency side is observed. Its apparent particle size, calculated from the half width, is 50
It is like a micro crystal with ~ 500 mm,
Actually, there are many such high crystallinity regions having a cluster structure, and a film having a semi-amorphous structure in which each cluster is bonded to each other by silicon (anchoring) can be formed.

As a result, the coating exhibits a state substantially free of grain boundaries (GB). Carriers can easily move from one cluster to another through anchored locations, resulting in higher carrier mobility than so-called GB polycrystalline silicon. That is, hole mobility (μh) = 10 to ²⁰⁰ cm ² / Vsec and electron mobility (μe) = 15 to 300 cm ² / Vsec are obtained.

On the other hand, instead of annealing at medium temperature as described above, 900-1
When the film is polycrystallized by high-temperature annealing at a temperature of 200 ° C, segregation of impurities in the film occurs due to solid phase growth from the nucleus, and GB contains a large amount of impurities such as oxygen, carbon, and nitrogen. Mobility is high, but barrier in GB (barrier)
To hinder the movement of carriers there. As a result, it is difficult to obtain a mobility of 10 cm ² / Vsec or more.

That is, in the embodiment of the present invention, as described above, a silicon semiconductor having a semi-amorphous or semi-crystalline structure is used.

In FIG. 6 (A), this silicon film was subjected to photo-etching using a first photomask to produce a PTFT region (21) on the right side of the drawing and an NTFT region (11) on the left side. .

In addition, a silicon oxide film is used as a gate insulating film on the
It was formed at 500-2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. A small amount of fluorine may be added during this film formation.

Thereafter, a silicon film containing phosphorus in a concentration of 1 to 5 × 10 ²⁰ cm ^-3 or molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned using a second photomask. Then, a gate electrode (4) for PTFT and a gate electrode (4 ') for NTFT were formed. For example, a channel length is 10 μm, phosphorus-doped silicon is formed as a gate electrode at 0.2 μm, and molybdenum is formed thereon at a thickness of 0.3 μm.

In FIG. 2 (C), a photoresist (31 ') is formed using a photomask, and a source (5),
Boron was added to the drain (6) at a dose of 1 × 10 ¹⁵ cm ⁻² by ion implantation.

Next, as shown in FIG. 6D, a photoresist (31) was formed using a photomask. Phosphorus is used as a source (5 ′) and a drain (6 ′) for NTFT at 1 × 10 ¹⁵ cm ^−2.
Was added by ion implantation.

These were performed through the gate insulating film (3). However, in FIG. 6 (B), the silicon oxide on the silicon film is removed using the gate electrodes (4) and (4 ') as a mask.
Boron and phosphorus may be directly implanted into the silicon film.

Next, heat annealing was performed again at 600 ° C. for 10 to 50 hours. And PTFT source (5), drain (6), NTFT
The source (5 ') and drain (6') of the semiconductor were made P ⁺ and N ⁺ by activating impurities.

Under the gate electrodes (4) and (4 '), channel forming regions (7) and (7') are formed as semi-amorphous semiconductors.

Thus, even though the self-alignment method is used, 70
C / TFT can be made without adding all temperatures above 0 ° C. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and this is a process that is extremely suitable for the large pixel liquid crystal display device of the present invention.

Thermal annealing was performed twice in FIGS. 6A and 6D. However, the annealing in FIG. 6 (A) may be omitted depending on the required characteristics, and both may be combined by the annealing in FIG. 6 (D) to shorten the manufacturing time. In FIG. 6 (E),
The interlayer insulator (8) was formed as a silicon oxide film by the sputtering method described above. This silicon oxide film is formed by LPCVD
Method or photo-CVD method may be used. For example, it was formed to a thickness of 0.2 to 0.4 μm. Thereafter, an electrode window (32) was formed using a photomask.

Further, the whole of these was formed by sputtering aluminum, and leads (9), (9 ') and contacts (2) were formed.
9) and (29 ') were fabricated using a photomask.

Further, as shown in FIG. 6 (F), in order to complement the two TFTs and connect the output terminals thereof to one of the transparent electrodes of the liquid crystal device, ITO (indium tin oxide film) was formed by a sputtering method. . It was etched using a photomask to form an electrode (33). This ITO was deposited at room temperature to 150 ° C., which was achieved by annealing at 200 to 400 ° C. in oxygen or atmosphere.

Thus, the PTFT (21), the NTFT (11), and the transparent conductive film electrode (33) were formed on the same glass substrate (1).

 The characteristics of such a TFT will be abbreviated.

Mobility (μcm ² / Vs) Vth (V) PTFT 20 −3 NTFT 30 +3 By using such a semiconductor, a large mobility could be produced in a TFT which was generally considered impossible. Therefore, the complementary TFT for the liquid crystal display device shown in FIGS. 3 and 5 can be constituted for the first time.

Embodiment 2 FIG. 5A shows an embodiment of the present invention corresponding to FIG. V _DD (18), V _SS (19), V _DD '(18') in the X-axis direction
(Hereinafter, also referred to as X-ray) having the following. In the Y-axis direction, V _GG (22), V _GG , (23) and wiring in the Y-axis direction (hereinafter also referred to as Y line) were formed.

FIG. 5 (A) is a plan view, and FIG. 5 (B) shows a longitudinal sectional view taken along the line AA ′. FIG. 5C shows a vertical sectional view taken along line BB '.

In addition, a PTFT (21) is provided at the intersection of the X-ray V _DD (18) and the Y-ray V _GG (22), and the intersection of the V _DD (18) and V _GG ′ (23) is used for another pixel. PTFT (21 ') is also provided. NTFT (11) is provided at the intersection of V _SS (19) and V _GG (22). Below the intersection of V _SS (19) and V _GG (22), an NTFT (11 ′) for another pixel is provided. C / TFT
A matrix configuration using was used. The source (5) receives the X-ray V _DD (1) through the contact (32).
8) and the gate (4) is a multilayered Y
Connected to line V _GG (22). The drain (6) is connected to an electrode (33) of a transparent conductive film via a contact (29).

On the other hand, in the NTFT, the source (5 ') is connected to the X-ray V _SS (19) via the contact (32)', and the gate (4 ') is
At line V _GG (22), drain (6 ') is connected to contact (2
It is connected to the transparent conductive film (33) through 9 '). Thus, one pixel was constituted by the transparent conductive film and the C / TFT between (inside) between the two X-rays (18) and (19). By repeating such a structure left and right, up and down,
One example of a 2x2 matrix or enlarged
It has become possible to produce liquid crystal display devices with large pixels, such as 640 × 480 and 1280 × 960.

Wherein the feature is, V _SS of the V _DD, V _SS sandwiching one pixel is to have is common with other V _SS, V _SS of other pixels sandwiched by V _DD '. By repeating this, even if two TFTs are provided for one pixel, the aperture ratio is not different from the conventional example shown in FIG. Another feature is V _LC
Is fixed at V _DD or V _SS .

 The operation is abbreviated using FIG.

In the pair of electrodes (33) and (34) sandwiching the liquid crystal (12), the other electrode (34) is set to the ground potential (13), while V _DD (19) is set to + 7V and V _SS (18) is set to If it is -7V, _VLC (10) will be fixed at + 7V or -7V. That is, as compared with the liquid crystal device using only the conventionally known NTFT shown in FIG. 1, _VLC does not float and has a constant potential. That is, it is understood that three types of potentials, V _DD , V _SS , and ground, can be set, and the number of control elements is increased by one.

Therefore, even if PTFT (21) or NTFT
Either one of (11) becomes unnecessary, and it is broken down by laser due to open state or leaking, and the degree is reduced to half even if it is in oven state, but it has the feature that it can drive liquid crystal (12) to some extent ing.

In FIG. 5, when considering the wiring of V _GG (22), an aluminum wiring (41) as an overline wiring (upper wiring) and an underline wiring (43) (lower wiring) made of the same material as the gate electrode ) And their contacts (42), it is not necessary to increase the number of new photomasks for multilayer wiring at the intersection of X-rays and Y-rays.

In order to make the pair of electrodes (33) and (34) of the liquid crystal (12) more parallel and flat to each other, aluminum wiring is applied in the step of FIG. 6 (F), and then an organic resin such as polyimide is applied. A transparent flat conductive film may be formed thereon. Further, an opening for contact of the transparent conductive film (33) is formed using an additional photomask,
It may be used to connect to the contacts (29) and (29 ').

In FIG. 5, an alignment film and an alignment treatment are performed on the transparent conductive film, and the substrate and the other liquid crystal electrode (the fourth
The substrates having the configuration shown in FIG. 34 were spaced from each other by a known method at a predetermined interval. Liquid crystal was injected during that time to complete the process.

If TN liquid crystal is used for the liquid crystal material, the interval should be about 10μ.
m, and it is necessary to form an alignment film on both transparent conductive films by rubbing.

When an FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is ± 20 V, and the cell interval is 1.5 to 3.5.
It is sufficient to provide an alignment film only on the opposite electrode (FIG. 4) (34) and perform a rubbing treatment.

When a dispersion type liquid crystal or a polymer liquid crystal is used, an alignment film is unnecessary and a switching speed is increased.
Operating voltage is ± 10 ~ ± 15V, cell interval is 1 ~ 10μm
And thinned.

In particular, when a dispersion type liquid crystal is used, since a polarizing plate is not required, the amount of light can be increased both in a reflection type and in a transmission type. Since the liquid crystal does not have a threshold, as shown in the C / TFT of the present invention, a C / TFT type in which a clear threshold voltage is defined enables a large contrast and crosstalk (bad interference with adjacent pixels). ) Could be excluded.

The second embodiment, a PTFT to V _DD side in C / TFT, V _SS
NTFT was formed on the side. The output can then determine a distinct level to create V _DD or V _SS . However, for _VGG , _VLC becomes an inverter.

This shows a case where _VGG and _VLC have the same phase (electrodes in the same direction).

Example 3 In this example, in the C / TFT, NTFT was placed on the V _DD side and V _SS
PTFT connected to the side. Then V _LC which is the output becomes V _GG and the in-phase, output potential is given by V _GG -Vth. Thus, there is a disadvantage that V _GG must be larger than V _DD , but there is a feature that little or no care is required between the gate electrode and _VLC .

In such a case, in FIG. 3, PTFT (21) and NTFT (1
What is necessary is just to provide mutually opposite to 1). That is, in FIG. 5, similarly, the PTFT and the NTFT may be provided opposite to each other. Therefore, the manufacturing steps and the aperture ratios in the second embodiment and FIG. 5 can have exactly the same values.

[Effects of the Invention] The present invention connects a complementary TFT to each pixel in a matrix, thereby 1) clarifying the threshold value 2) V _DD and V _SS are alternately arranged in each pixel. The switching speed can be reduced because they can be commonly used. 3) The switching margin can be increased. 4) The operating margin can be increased. 4) Some defective TFTs can be compensated for to some extent. 5) The number of photomasks required for fabrication. 6 shows that the photomasks of FIGS. 6 (C) and (D)
It has many features that it is only necessary to increase the number of times.

As a result, compared to the conventional active TFT liquid crystal devices, it has become possible to achieve several stages of manufacturing yield and a vividness of the screen.

In the present invention, semi-amorphous or semi-crystal was used as the semiconductor for the C / TFT. However, semiconductors of other crystal structures may be used if possible for the same purpose. High-speed processing was performed by using a self-aligned C / TFT. However, needless to say, a TFT may be manufactured by a non-self-alignment method without using the ion implantation method.

[Brief description of the drawings]

FIG. 1 shows a crystal apparatus using a conventional active TFT (thin film transistor). 2 and 3 are circuit diagrams of an active liquid crystal device using the complementary TFT of the present invention. FIG. 4 shows the operation of the complementary TFT. FIG. 5 shows a plan view (A), longitudinal sectional views (B) and (C) of one substrate of the liquid crystal display device corresponding to FIG. FIG. 6 shows a method of manufacturing a complementary TFT used in the liquid crystal device of the present invention. (1) glass substrate (2), (2 ') silicon semiconductor (3) gate insulating film (3') blocking layer (4), (4 ') gate electrode (5) , (5 ') ... source (6), (6') ... drain (7), (7 ') ... channel forming region (10) ... liquid crystal potential (V _LC ) (11) ... N channel -Type thin film transistor (NTFT) (12) Liquid crystal (14), (15) Resistor that causes leakage (16), (17) Peripheral circuit (18), (18 ') _Vss (X-ray (19), (19 ') ... V _DD (one of X-rays) (21) ... P-channel thin film transistor (PTFT) (22), (23) ... V _GG , V _GG ' (Y line) (33), (34) ... Transparent electrode-Process using photomask

Claims (2)

(57) [Claims] A plurality of gate wirings, a plurality of source wirings, first and second N-channel thin film transistors,
First and second P-channel thin film transistors;
And a second pixel electrode, wherein the gate electrodes of the N-channel thin film transistor and the P-channel thin film transistor are connected to one of the gate lines.
And the source of the first N-channel type thin film transistor is:
The source of the first and second P-channel thin film transistors is connected to one of the source wirings, and the source of the second N-channel thin film transistor is connected to the other of the source wirings.
The first pixel electrode is connected to a drain of the first N-channel type thin film transistor and the drain of the first P-channel type thin film transistor, and the second pixel electrode is The liquid crystal display device is connected to the drains of the second N-channel thin film transistor and the second P-channel thin film transistor. 2. The liquid crystal display device according to claim 1, wherein said N-channel thin film transistor and said P-channel thin film transistor have a crystalline silicon semiconductor layer.