JP3000177B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active display device, and more particularly to an active liquid crystal display device. Two P-channel and N-channel thin-film insulated gate field effect transistors are complementary to each pixel. (Hereinafter referred to as a TFT).

[0002]

2. Description of the Related Art Conventionally, an effective display device has been
2. Description of the Related Art An active liquid crystal display device using an FT is known. In this case, a semiconductor having an amorphous or polycrystalline structure is used for the TFT, and a TFT having only one of the P and N conductivity types is used for one pixel. That is, generally, an N-channel TFT (referred to as NTFT) is connected in series to the pixel. FIG. 6 shows a typical example.

In general, an active matrix type liquid crystal display device has a very large number of pixels of 480 × 640 or 1260 × 960. FIG. 6 shows the same meaning as above, and is shown in a 2 × 2 matrix arrangement for simplicity of explanation. Arranged orthogonally plurality of gate lines G _1, G ₂ and a plurality of signal lines D _1, and D _2, is provided with a pixel display element at the intersection of the matrix. This pixel display element includes a liquid crystal unit 102 and a TFT unit 101. A signal is applied to each pixel from the peripheral circuits 106 and 107, and a predetermined pixel is selectively turned on or off to perform display.

However, when these liquid crystal display devices are actually manufactured and displayed, the output of the TFT, that is, the voltage _VLC 100 of the input to the liquid crystal (referred to as liquid crystal potential) is often “1” (High). It does not become "1" (High) when it should be, and "0" (Low) when it should become "0" (Low)
do not become. This occurs because there is no symmetry in the characteristics of a switching element for applying a signal to a pixel, that is, a TFT. In other words, this is because the state of charge and the state of discharge to the pixel electrode have a difference in electrical characteristics. The liquid crystal 102 is inherently insulating in its operation, and
When the TFT is off, the liquid crystal potential (V _LC ) is in a floating state. Since the liquid crystal 102 is equivalently a capacitor,
_VLC is determined by the electric charge stored therein. This charge or a relatively small resistance the liquid crystal is in R _LC, Li by the presence of dust or ionic impurities - or click and TFT
Pin hole of the gate insulating film - charge therefrom when R _GS 105 has occurred leaked by Le, V _LC becomes the limbo. For this reason, 200,000 to 50 per panel
A liquid crystal display device having 100,000 pixels has a problem that a high yield cannot be achieved.

As the liquid crystal 102, a TN (twisted nematic) liquid crystal is generally used. A rubbed alignment film is provided on each electrode to align the liquid crystal.
A weak dielectric breakdown occurs due to static electricity generated by the rubbing process, leading to leakage between adjacent pixels or adjacent conductors, or leakage due to weak gate insulating film. I will.

[0006]

In an active type liquid crystal display device, it is extremely important to keep the liquid crystal potential at the same level as the initial value during one frame to keep a predetermined level. However, in practice, there are many malfunctions of the active element, and in fact, the liquid crystal potential cannot always be kept at the same value as the initial value and maintained at a predetermined level during one frame.

Therefore, as shown in FIG. 7, a pair of first and second signal lines are arranged in the X direction and a third signal line is arranged in the Y direction in a matrix for one pixel. In which a complementary type thin film transistor and a pixel electrode are provided at the intersection of the N-channel thin film transistor 2 connected to the pixel.
The source (drain) portion of the P-channel thin film transistor 1 connected to the pixel is connected to the first signal line 35 of the pair of signal lines in the X direction, and the second signal line of the pair of signal lines in the X direction is connected to the pixel. 38, and the gates of the P-channel thin film transistor and the N-channel thin film transistor are connected to a third signal line 33.

According to this, the above-mentioned problem is solved, and the current margin is increased, that is, the response speed is increased. In addition, the potential of the pixel in each pixel, that is, the liquid crystal potential _VLC is fixed to "1" and "0" with sufficient stability so that the level does not drift during one frame.

However, since this circuit configuration requires three signal lines per unit pixel, the "aperture ratio" which is one of the factors determining the display quality of the liquid crystal display device is reduced. Because, it was a problem.

[0010]

According to the present invention, in a liquid crystal display device having a plurality of pixels arranged in a matrix, a first P-channel thin film transistor and a second P-channel type thin film transistor are provided on each of pixel electrodes provided on one substrate. One of the input / output terminals of a complementary thin film transistor in which one N-channel thin film transistor is configured to be complementary is connected to the pixel electrode, and the other is connected to the input / output terminal of a second P-channel thin film transistor and a second N-channel thin film transistor, respectively. Connected to the input / output end of the thin film transistor,
The other input / output terminal of the second P-channel thin film transistor is connected to a first signal line in the X-axis direction of the substrate, and the other input / output terminal of the second N-channel thin film transistor is connected to the first input / output terminal in the X-axis direction. Connected to two signal lines, commonly connected to the gate electrodes of the first P-channel thin film transistor and the first N-channel thin film transistor, and connected to a third signal line in the Y-axis direction of the substrate; A gate electrode of a second P-channel thin film transistor is connected to the second signal line, a gate electrode of the second N-channel thin film transistor is connected to the first signal line, and the second signal line is connected to the second signal line. A display device provided as a first signal line of a plurality of thin film transistors connected to other pixel electrodes adjacent to each other with the second signal line interposed therebetween.

That is, the complementary thin film transistor circuit of the present invention comprises an N-channel thin film transistor, a P-channel thin film transistor for controlling the potential of the pixel electrode in contact with the display means, a P-channel thin film transistor for controlling the operation of these complementary circuits, and an N-channel thin film transistor. The channel type thin film transistors are configured as one group.

With this configuration, the signal lines connected to the adjacent pixels can be shared by a group of thin film transistors corresponding to the pixels adjacent to each other across the signal line in the X-axis direction. It ended up with just a single signal line. As a result, the aperture ratio could be improved.

As a configuration of the display device to which the present invention can be applied, one pixel may be configured by connecting two or more thin film transistor groups to one pixel.
Further dividing one pixel into two or more,
One or more thin film transistor groups may be connected to each.

With such a configuration, when the C / TFT connected to the pixel is actually driven, the PTFT and the NTF are used.
When T is close to each other and the input signal is applied, up to twice the voltage of V _DD (V _SS ) is applied between the signal lines, and leakage occurs between the signal lines. Since the signal lines that have become the same have the same function (signal lines to NTFT or signal lines to PTFT), only a maximum voltage of about V _DD ( _VSS ) is applied between the signal lines. It has the characteristic that there is little leak in.

A typical example of the structure of a display device to which the present invention can be applied is shown as a circuit diagram in FIGS. First, the present invention will be described with reference to the circuit diagram of FIG. 1. FIG. 2 shows an example of the actual pattern layout (arrangement diagram) of FIG. For simplicity of description, a 2 × 2 matrix configuration is exemplified here. In the example of the 2 × 2 matrix shown in FIG. 1, the first PTFT 1 and the first NTFT 2
The gate 3,4 is connected to each other with, and further connected to a third signal line V _G1 in the Y-axis direction and connects the common output terminal 6 of the C / TFT in the liquid crystal 7. The input terminal 8 of the first PTFT 1 is connected to the output terminal 9 of the second PTFT 20 and the second PTFT
Is connected to the signal line V _D1 in the X-axis direction, and the gate 12 of the second PTFT is connected to the signal line V _D2 in the X-axis direction.

Furthermore the output terminal 14 of the first NTFT2 to the input end 15 of the second NTFT17, and connects the output terminal 16 of the second NTFT to the signal line V _D2 in the X-axis direction. Further, the gate 18 of the second NTFT is connected to the signal line V in the X-axis direction.
_It is connected to _D1 .

In such a configuration, as shown in FIG. 2, during a period in which a selection (ON) signal waveform is applied between the pair of first signal line V _D1 and second signal line V _D2. When a display (ON) signal waveform is applied to the third signal line _VG1 ,
The liquid crystal potential (V _LC ) 19 at point A is PTFT 20 and NTFT
The gate electrodes 12 and 18 are forward biased and PT
Since the FT 20 and the NTFT 17 are conductive, the PTF
It is controlled by the operation of T1 and NTFT2. This PTFT1, operation of NTFT2 are connected signal lines V _G1 by the controlled voltage of the signal line V _G1 (V _G) and the voltage of the signal line V _D1 of the gate electrodes 3, 4 of each TFT (V _D1), the signal line voltage V _D2 (V _D2), when illustrating an operation in the liquid crystal potential 19 (V _CL), when _{V G <V D2 + V TH} (NTFT2), V
_CL 19 ≒ V _D11 , and V _G > V _D1 −V _TH (PTFT
In the case of 2), it is controlled to the value of V _CL 19 ≒ V _D2 13.

Conversely, when the third signal line V _G1 is displayed (when an ON signal is applied), the first signal line V _D1 and the second signal line V _D2 are not selected (the value that becomes the OFF signal). ), V _D1 ≒
If V _D2 , V _D1 <V _D2 , PTFT20 and NTFT1
7 is reverse-biased and PTFT 20 and NTFT 17 are insulated, so that the above-mentioned condition indicating the operation of PTFT 1 and NTFT 2 is satisfied. Even if PTFT 1 or NTFT 2 becomes conductive, liquid crystal potential 19 (V _CL ) is insulated from other potentials State. Therefore, the liquid crystal potential 19 (V _CL ) is in a non-selected state with respect to the third signal line V _G1, and keeps the current liquid crystal potential.

As described above, the liquid crystal potential (V _CL ) is given according to the voltage applied to the second signal line corresponding to the first signal line of another pixel adjacent to the first signal line. By varying the voltage of the signal applied to the line, the potential difference applied to the liquid crystal can be arbitrarily varied.

The counter electrode 16 is connected to an offset voltage (V
_OFFSET ) is applied, and the voltage actually applied to the liquid crystal 15 is V _D1 + V _OFFSET or V _D2 + V _OFFSET .
In the driving method of the present invention, the on / off of the liquid crystal driving can be arbitrarily changed by changing the offset voltage V _OFFSET applied to the counter electrode. Also, since the threshold for actually driving the liquid crystal differs depending on the liquid crystal material, an arbitrary threshold can be adjusted only by changing the offset voltage V _OFFSET to match the value of the liquid crystal. it can.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, description will be made using a liquid crystal display device having a circuit configuration as shown in FIG. FIG. 2 shows an actual arrangement of electrodes and the like corresponding to this circuit configuration. For simplification of description, only portions corresponding to 2 × 2 are described.

First, a method for manufacturing a liquid crystal display device used in this embodiment will be described with reference to FIGS. In FIG. 3A, a silicon oxide film as a blocking layer 151 is formed on a glass 150 which can withstand a heat treatment at 700 ° C. or less, which is not expensive, for example, about 600 ° C., using a magnetron RF (high frequency) sputtering method. It is made to a thickness of 3000 mm. The process conditions are an atmosphere of 100% oxygen, a film formation temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa.
And The film formation rate using quartz or single crystal silicon as a target was 30 to 100 ° / min.

On top of this, a silicon film is formed by LPCVD (low pressure vapor phase method, sputtering method or plasma CVD method.
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus at 450 to 550 ° C., for example, 530 ° C., lower by 0 to 200 ° C. to form a film. Reactor pressure is 30 ~ 300P
a. The deposition rate was 50-250 ° / min. N
In order to control the threshold voltage of the TFT and the PTFT substantially equal to Vth, boron is changed to 1 by using diborane.
It may be added during film formation as a concentration of × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ .

When the sputtering method is used, the back pressure before sputtering is set to 1 × 10 ⁻⁵ Pa or less, and single crystal silicon is used as a target in an atmosphere containing 20 to 80% of hydrogen mixed with argon. For example, argon was 20% and hydrogen was 80%.
The film formation temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into a PCVD apparatus, and a high-frequency power of 13.56 MHz was applied to form a film.

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. If the oxygen concentration is high, it is difficult to crystallize, and the heat annealing temperature must be increased or the heat annealing time must be increased.
If the amount is too small, the lamp is turned off by the backlight.
Current increases. Therefore, 4 × 10 ¹⁹ to 4 × 10 ²¹
The range was cm ⁻³ . Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon 4
It was 1 atomic% when compared with × 10 ²² cm ⁻³ . Also,
In order to promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ^−3.
cm ⁻³ or less, and oxygen is ion-implanted only in a channel formation region of a TFT constituting a pixel to form 5 × 10 ^{20 to} 5 × 10
You may add so that it may be set to ²¹ cm- ³ . At this time, since light is not irradiated to the TFTs constituting the peripheral circuit, it is effective to reduce the mixing of oxygen and to have a higher carrier mobility for high-frequency operation.

Next, a silicon film in an amorphous state is
After fabrication to a thickness of ~ 5000mm, for example 1500mm, 4
Medium-temperature heat treatment in a non-oxide atmosphere at a temperature of 50 to 700 ° C. for 12 to 70 hours, for example, 600 hours in a hydrogen atmosphere
It was kept at a temperature of ° C. Since a silicon oxide film having an amorphous structure is formed on the surface of the substrate under the silicon film, no specific nucleus is present in this heat treatment, and the whole is annealed uniformly. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

Due to the annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and a part of the silicon film exhibits a crystalline state. In particular, a region having a relatively high order in a state after the formation of silicon is particularly likely to be crystallized to be in a crystalline state. However, since the silicon existing between these regions is bonded to each other, silicon mutually pulls each other. When measured by laser Raman spectroscopy, a single crystal silicon peak 522 is obtained.
A peak shifted to a lower frequency side than cm ⁻¹ is observed. Its apparent particle size is 50 to 5 when calculated from the half width.
Although it is a microcrystal with a size of 00Å, there are actually a large number of regions with high crystallinity and a cluster structure, and a semi-amorphous structure film in which each cluster is bonded to each other by silicon (anchoring). Could be formed.

As a result, the coating exhibits a state substantially free of grain boundaries (hereinafter referred to as GB). Carriers can easily move from one cluster to another through anchored locations, resulting in higher carrier mobility than so-called GB polycrystalline silicon. That is, the hole mobility (μh = 10 to 200 cm ² / V)
Sec), electron mobility (μe = 15-300 cm ² / VS)
ec) is obtained.

On the other hand, when the film is polycrystallized by high-temperature annealing at 900 to 1200 ° C. instead of annealing at the medium temperature as described above, segregation of impurities in the film occurs due to solid phase growth from nuclei. , GB contain a large amount of impurities such as oxygen, carbon, and nitrogen, and have high mobility in the crystal. However, the barrier in GB (a barrier is formed and movement of carriers there is hindered. As a result, 10 cm ² / In fact, it is difficult to obtain a mobility of Vsec or more, that is, in this embodiment, a silicon semiconductor having a semi-amorphous or semi-crystalline structure is used for the above reason.

In FIG. 3A, a silicon film is subjected to photoetching using a first photomask, and a PTFT region 122 (channel width 20 μm) is placed on the right side of the drawing in NT.
A region 113 for FT was formed on the left side.

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix the sodium ions.

Thereafter, 1 to 5 × 10 ²¹ cm of phosphorus is placed on the upper side.
^-3 silicon film or molybdenum (Mo), tungsten (W), MoSi ₂ or
A multilayer film with WSi ₂ was formed. This was patterned using a second photomask to obtain FIG. PTFT
Gate electrode 121 for NTFT, gate electrode 109 for NTFT
Was formed. For example, a channel length was 10 μm, and a gate electrode was formed of 0.2 μm of phosphorus silicon, and molybdenum was formed thereon with a thickness of 0.3 μm. In FIG. 3 (C),
A photoresist 157 is formed using a photomask, and a source 118 for PTFT and a drain 120 are formed.
Boron was added at a dose of 1-5 × 10 ¹⁵ cm ^-2 by ion implantation. Next, as shown in FIG. 3D, a photoresist 161 was formed using a photomask. NTFT
Source 1 and phosphorus 1 to 5 as drain 112
It was added by ion implantation at a dose of × 10 ¹⁵ cm ^-2 .

These steps were performed through the gate insulating film 154. However, in FIG. 3B, the gate electrodes 121, 1
09 is used as a mask to remove silicon oxide on the silicon film,
Thereafter, boron or phosphorus may be directly ion-implanted into the silicon film.

Next, annealing was performed again at 600 ° C. for 10 to 50 hours. The source 118 and the drain 120 of the PTFT and the source 110 and the drain 112 of the NTFT were manufactured as P ⁺ and N ⁺ by activating impurities. The channel formation region 11 is formed below the gate electrodes 121 and 109.
9, 111 are formed as semi-amorphous semiconductors.

In this way, a C / TFT can be manufactured without applying a temperature to 700 ° C. or more in all steps, even though it is a self-aligned system. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and this is a process very suitable for the large pixel liquid crystal display device of the present invention.

In this embodiment, the thermal annealing is performed as shown in FIG.
(D) was performed twice. However, the annealing in FIG. 3A may be omitted depending on the desired characteristics, and both may be replaced by the annealing in FIG. 3D to shorten the manufacturing time. In FIG. 3E, the interlayer insulator 165 was formed as a silicon oxide film by the above-described sputtering method. This silicon oxide film may be formed by an LPCVD method, a photo CVD method, or a normal pressure CVD method. For example, it was formed to a thickness of 0.2 to 0.6 μm, and then a window 166 for an electrode was formed using a photomask. Further, aluminum is formed on the entire surface by sputtering, and leads 171 and 172 and contact 1 are formed.
After producing 67 and 168 using a photomask, the surface was coated with a flattening organic resin 169, for example, a light-transmitting polyimide resin, and the electrode drilling was performed again using the photomask.

As shown in FIG. 3 (F), in order to connect the two TFTs to a complementary structure and connect the output terminals thereof to the electrodes of one pixel of the liquid crystal device as transparent electrodes, ITO (indium oxide) is formed by sputtering. A tin oxide film). It is etched using a photomask and the electrode 1
17 were constructed. This ITO film was formed at room temperature to 150 ° C., and was achieved by oxygen at 200 to 400 ° C. or annealing in air. Thus, PTFT 122 and NT
The FT 113 and the electrode 117 made of a transparent conductive film were formed on the same glass substrate 150. The electrical characteristics of the obtained TFT are PTFT, the mobility is 20 [cm ² / Vs], and the Vth is −5.9.
In [V], the mobility of NTFT was 40 [cm ² / Vs, Vth] of 5.0 [V].

A transparent electrode is provided on the entire surface of one of the substrates for the liquid crystal device and the other glass substrate manufactured according to the method as described above, and these substrates are laminated to form a liquid crystal cell.
A TN liquid crystal material was injected therein.

FIG. 2 shows the arrangement of the electrodes and the like of the liquid crystal display device. PTFT 1 and 20 are connected to the first signal line V
It is provided at the intersection of _D1 and the third signal line _VG1 . Meanwhile NTFT2,17 is provided at the intersection between the second signal line V _D2 third signal line V _G1. Such C / TF
A matrix configuration using T was provided.

The PTFT 20 is connected to the first signal line V _D1 via a contact at the input end of the drain 10, and the gate 12 is connected to the signal line V _D2 on which a multilayer wiring is formed via a wiring 22. The output terminal of source 9 is PTFT1
And the source 23 of the TFT is connected to the pixel electrode 6 via a contact. The gate 3 of the TFT is connected to the third electrode 5.

On the other hand, the NTFT 17 is connected to the second signal line V _D2 via a contact at the input terminal of the drain 16, and
The gate 18 is connected via a wiring 21 to a signal line _VD1 on which a multilayer wiring is formed. The output terminal of source 15 is N
The drain 15 of the TFT 2 is connected through a diffusion layer, and the source 24 of the TFT 2 is connected to the pixel electrode 6 through a contact. The gate 3 of the TFT is connected to the third electrode 5.

By repeating such a structure horizontally and vertically, a 2 × 2 matrix is expanded to 640 × 4.
A liquid crystal display device having a large pixel size of 80, 1280 × 960 can be obtained.

In this way, a laptop display device was produced. Also, this is not only laptop type,
A projection type display device, a viewfinder of a video camera, a projection type display device, and the like have substantially the same steps and structures.

In this embodiment, an example in which a group of thin film transistors is provided for one pixel has been described. However, the present invention is not particularly limited to this configuration. One pixel is constituted by a plurality of pixel electrodes. A configuration in which a group of thin film transistors is provided in each of them and a configuration in which a plurality of groups of thin film transistors are provided for one pixel are also included in the scope of the present invention.
In this case, even if a defective operation is found in some of the TFTs, the function can be supplemented by other parts or an area gray scale can be achieved.

[0046]

As described above, according to the driving method of the present invention, since the liquid crystal potential is not floating, a stable display can be performed. Also, since the driving capability of the C / TFT as the active element is high, the operation margin can be expanded, and the peripheral driving circuit can be made simpler, so that the display device can be downsized and the manufacturing cost can be reduced. There is. In addition, high driving capability can be exhibited with very simple signals to the three signal lines and the counter electrode.

Even if some of the defective TFTs are in-phase output, it can be compensated to some extent.

Further, since no high potential difference is applied between the signal lines connected to the adjacent pixels, no leakage occurs. Further, since the pixel and the signal line can be used in common, the actual number of signal lines per unit pixel is two, and the aperture ratio of the display device can be improved.

As the display medium in the present invention, a transmission type liquid crystal display device or a reflection type liquid crystal display device can be used. As a usable liquid crystal material, a TN liquid crystal, an FLC liquid crystal, a dispersion liquid crystal, or a polymer liquid crystal as described above can be used. In addition, an ionic dopant is added to a guest-host type or dielectric anisotropic type nematic liquid crystal and an electric field is applied to apply the electric field to a nematic liquid crystal and a mixture of the cholesteric liquid crystal and a nematic phase and a cholesteric phase. A phase change liquid crystal which causes a phase change between the liquid crystal and the liquid crystal and realizes a transparent or cloudy display can also be used. In addition to the liquid crystal, for example, a so-called electrophoretic display dispersion system in which pigment particles having different colors are dispersed in an organic solvent colored with a dye can be used.

[Brief description of the drawings]

FIG. 1 shows a circuit diagram of the invention.

FIG. 2 shows an element configuration of the present invention.

FIG. 3 shows an example of a process according to the invention.

FIG. 4 shows a driving waveform according to the present invention.

FIG. 5 shows a circuit diagram according to the invention.

FIG. 6 shows a circuit diagram according to a conventional example.

FIG. 7 shows a circuit diagram according to a conventional example.

FIG. 8 shows a circuit diagram according to the invention.

[Explanation of symbols]

 1 first PTFT 2 first NTFT 17 second NTFT 20 second PTFT

Claims (3)

(57) [Claims] 1. A plurality of pixels are provided in a matrix .
In Viewing device, connect the common output terminal of the complementary thin film transistor constructed in complementary with the first P-channel thin film transistor and a first N-channel type thin film transistor to each of the pixel electrodes provided on one of the substrates The first
Of the P-channel type thin film transistor of the second
Connected to the output terminal of the channel type thin film transistor,
Output terminal of the N-channel type thin film transistor
Connected to the input terminal of the channel type thin film transistor,
Of the input terminal of the P-channel type thin film transistor in the X-axis direction.
Connected to the first signal line, and connected to the second N-channel thin film transistor.
Connect the output end of the transistor to the second signal line in the X-axis direction
And a gate of the first P-channel thin film transistor
Electrodes and gay of the first n-channel thin film transistor
And to the third signal line in the Y-axis direction
Connected to the gate of the second P-channel thin film transistor.
Light source electrode connected to the second signal line in the X-axis direction,
The gate electrode of the second N-channel transistor is connected to the X
Connected to the first signal line in the axial direction,
The signal line is an image adjacent to the first signal line side in the X-axis direction.
The second signal line in the X-axis direction in the element, and
The second signal line in the X-axis direction is the second signal in the X-axis direction.
To the first signal line in the X-axis direction in the pixel adjacent to the line side
A display device characterized by being equal . 2. The pixel according to claim 1, wherein the pixel includes a plurality of pixel electrodes, and a first N-channel thin film transistor, a first P-channel thin film transistor, and a second P-channel thin film transistor correspond to each of the pixel electrodes. Wherein the N-channel type thin film transistor and the second P-channel type thin film transistor are provided. Wherein in correspondence with each of the pixel electrode according to claim 1, wherein the first N-channel thin film transistor, the first P
A display device, comprising a plurality of groups each including a channel thin film transistor, a second N-channel thin film transistor, and a second P-channel thin film transistor.