JP3476763B2 - Active matrix device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal electro-optical device using a thin film transistor (hereinafter referred to as TFT) as a driving switching element.

[0002]

2. Description of the Related Art Conventionally, an active matrix type liquid crystal electro-optical device using a TFT has been known. in this case,
Amorphous or polycrystalline semiconductors are used for TFTs, and only one of P-type or N-type TFTs is used for one pixel. That is, generally N
A channel type TFT (referred to as NTFT) is connected in series to the pixel. A typical example thereof is shown in FIG.

FIG. 2 schematically shows an equivalent circuit of a liquid crystal electro-optical device, and 22 shows a liquid crystal portion of one pixel. An NTFT 21 is provided in series with it. Such pixels are arranged in a matrix. Generally, it has a large number of pixels of 640 × 480 or 1260 × 960, but in this drawing, a 2 × 2 matrix array is simply drawn with the same meaning. When signals are applied to the respective pixels from the peripheral circuits 26 and 27 to selectively turn on predetermined pixels and turn off other pixels, when the on / off characteristics of the TFT are generally good, time-division driving is performed. As a result, it is possible to realize a liquid crystal electro-optical device having a large contrast even when the duty is high.

[0004]

However, when actually manufacturing such a liquid crystal electro-optical device, a TFT is formed.
Output, ie, the input voltage V _LC 20 for the liquid crystal
(Liquid crystal potential) often does not become "1" (High) when it should be "1" (High), and conversely does not become "0" (Low) when it should be "0" (Low). . This is because the TFT, which is a switching element that applies a signal to the pixel, is placed in an asymmetrical state in the ON and OFF states.

The liquid crystal 22 is inherently insulating in its operating condition, and the liquid crystal potential (V _LC ) when the TFT is off.
Is in a floating state. Since this liquid crystal 22 is a capacitor in terms of an equivalent circuit, V _LC is determined by the electric charge accumulated therein. This charge leaks due to the resistance R _LC 24 of the liquid crystal being a relatively small resistance, and the presence of dust and ionic impurities in the liquid crystal.

In addition, R _GS 25 is provided between the gate electrode and the input / output end of the TFT due to the pinhole of the gate insulating film of the TFT 21.
In the case of occurrence of the charge, the charge leaks from the charge, and the V _LC 20 is in a halfway state.

Therefore, one panel has 200,000 to 500
In a liquid crystal display device having ten thousand pixels, since TFTs are also present, the above-mentioned problems occur and a high yield cannot be achieved. In particular, the liquid crystal 22 is generally a TN (twisted nematic) liquid crystal. For the alignment of the liquid crystal, a rubbing alignment film is provided on each electrode. Due to the static electricity generated by this rubbing process, a weak dielectric breakdown occurs in the TFT, and leak occurs between the pixel and the adjacent conductive line, or the gate insulating film is weak and leaks. Resulting in. In the active matrix type liquid crystal electro-optical device,
It is extremely important to keep the liquid crystal potential at a predetermined level by keeping the liquid crystal potential the same as the initial value for one frame. However, the reality is that there are many defects and they are not always fulfilled.

If the liquid crystal material is a ferroelectric liquid crystal, it is necessary to increase the injection current. For this reason, there is a drawback that the element size of the TFT must be increased to increase the current margin.

The present invention has a problem caused by the asymmetry of the states when the driving elements for driving the respective pixels of the display device are turned on and off, that is, the potential of the display portion is fixed to "1" and "0" sufficiently and stably. However, it is an object of the invention to solve the problem that the level drifts during one frame.

In addition, there is proposed a liquid crystal electro-optical device having a compensation function in the case where a malfunction of TFTs existing in a large number in one liquid crystal electro-optical device (mainly a defect due to a short circuit between a source and a drain or a leak) occurs. It is a thing.

[0011]

The present invention is a liquid crystal electro-optical device in which a plurality of pixels having a matrix structure are provided on a substrate, and each pixel electrode has a P-channel type thin film transistor and an N-channel type thin film transistor. A plurality of sets of complementary thin film transistors configured to be complementary to each other are provided, the input and output ends of the plurality of complementary thin film transistors are connected in series, one of the input and output ends is connected to the pixel electrode, and the other is connected to the first signal. The liquid crystal electro-optical device is characterized in that it is connected to a line and all gate electrodes of the plurality of complementary thin film transistors are connected to a second signal line.

Here, the complementary type thin film transistor is N
One of the input / output portions of the channel type thin film transistor (hereinafter referred to as NTFT) and one of the input / output portions of the P channel type thin film transistor (hereinafter referred to as PTFT) are respectively connected, and the gate electrodes of the P and N channel type thin film transistors are Complementary thin film transistors (hereinafter referred to as C / TF) that are connected to each other, and these connected portions serve as source, drain and gate electrodes for input and output.
It is called T).

A liquid crystal electro-optical device in which a plurality of pixels having a matrix structure are provided on a substrate, and each pixel electrode has a plurality of P-channel type thin film transistors and a plurality of N-channel type thin film transistors. Input / output terminals of the source and drain regions of the plurality of P-channel type thin film transistors are connected in series, one of the input / output terminals is connected to the pixel electrode, and the other is connected to the first signal line. Input / output terminals of the source and drain regions of the N-channel thin film transistor are connected in series, one of the input / output terminals is connected to the pixel electrode, and the other is connected to the same first signal line, and all of the thin film transistors are connected. Is connected to the same second signal line as the liquid crystal electro-optical device.

A typical example of the present invention is shown as a circuit in FIG.
2 × driven by the peripheral circuits 1 and 2 shown in FIG.
2 shows an example of an active matrix liquid crystal electro-optical device of No. 2. In the figure, two PTFTs and two NTFTs are connected in a complementary configuration corresponding to one pixel portion 3. PTFT out of 4 TFTs
The source region and the drain region are electrically connected to the NTFT and the NTFT, and form a set of C / TFT. These two C / TFTs are electrically connected in series to the pixel electrodes, and one input / output section 4 is connected to the signal line V _DD1 arranged in a matrix and the other input / output section 5 is connected. Is connected to the pixel electrode 6 of the liquid crystal.

The gate electrodes of the four TFTs are connected to the same signal line V _GG1 , and two sets of C / TFTs are provided in one pixel portion.

An active matrix type liquid crystal electro-optical device is constructed by arranging pixel portions having TFTs having such a configuration in a matrix.

By adopting such a configuration, the PT
The potential of the pixel portion 3 when the C / TFT including the FT and the NTFT is turned on and off is stably fixed to "1" and "0", and the level does not drift during one frame. A display device can be obtained.

Further, according to the present invention, such C / TFT
A plurality of TFTs are provided in series, and even if some of the four TFTs malfunction (specifically, a short circuit or leak between the source and drain), the other TFTs can compensate the operation. It is. That is, since the C / TFT is provided in series with the pixel, even if a part of the pixel is always in the conductive state, the remaining TFT turns on and off the pixel.
This is because the FF can be controlled.

Since they are arranged in series, they are turned off.
The minute current leak in the state is less likely to occur due to the double resistance of a normal TFT, and the potential of the pixel portion 3 can be fixed to "1" and "0" sufficiently stably. Became.

FIG. 3 shows another example of the present invention.
In FIG. 3, as in FIG. 1, an example in which a 2 × 2 matrix is arranged is shown for the sake of explanation.

In the figure, two PTFTs and two NTFTs are connected in a complementary configuration corresponding to one pixel portion 3. That is, the source and drain regions of two PTFTs out of four TFTs are connected in series, and the source and drain regions of two NTFTs are also connected in series. Such PTFT group and NTFT
The source and drain regions of the group are electrically connected,
It constitutes a set of C / TFTs. The C / TFT has an input / output section electrically connected in series to the pixel electrode, one input / output section 30 is connected to the signal line V _DD1 arranged in a matrix, and the other input / output section 31 is a liquid crystal. Is connected to the pixel electrode 6 of.

Further, the gate electrodes of the four TFTs are connected to the same signal line V _GG1, and one pixel portion is provided with a set of C / TFTs composed of four TFTs.

As described above, in the present invention, a plurality of TFTs are provided in series with the pixel electrode, and the TFTs are individually or entirely made to function as C / TFTs.
The present invention is characterized in that the function of compensating for the malfunction of is realized, and the invention is not limited to the above example, but can be realized by providing a plurality of TFTs.

Further, in the example of FIG. 1, PTFT and N
Even if the relative positional relationship with the TFT is changed, the exact same function can be realized, and a degree of freedom can be given to the layout of the liquid crystal electro-optical device.

[0025]

[Embodiment 1] This embodiment is a liquid crystal electro-optical device corresponding to the equivalent circuit shown in FIG. 3, in which one pixel is provided with two PTFTs and two NTFTs.

Further, FIG. 4 shows a top view and a sectional view thereof, and FIG. 5 shows a manufacturing process diagram of the TFT used in this embodiment.
These figures are drawn for the sake of explanation, and the dimensions of the actual device are different, and details are omitted for the sake of explanation.

First, the manufacturing process of the PTFT 41 and the NTFT 40 will be described with reference to FIG. The basic manufacturing method of the PTFT and the NTFT are the same except for the type of impurities to be introduced, and therefore the description will be given using FIG.

First, a glass substrate 50 such as AN glass and Pyrex (registered trademark) glass that can withstand a heat treatment at about 600 ° C. is coated with a silicon oxide film 51 as a blocking layer by a magnetron RF (high frequency) sputtering method. 3000Å
Was manufactured to a thickness of. The process conditions were an atmosphere of 100% oxygen, a film forming temperature of 150 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa.
Quartz or single crystal silicon was used for the target, and the film formation rate was 30 to 100 Å / min. Further, a silicon film 52 is formed thereon by LPCVD (Low Pressure Vapor Phase) method, sputtering method or plasma CVD method, and the shape of (A) is obtained through a known patterning process such as photolithography.

When this silicon film is formed by the reduced pressure vapor phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature.
For example, disilane (Si ₂ H ₆ ) or trisilane (Si ₃
H ₈ ) was supplied to the CVD device to form a film. The reactor pressure is 3
It was set to 0 to 300 Pa. The film formation rate was 50 to 250 Å / min. The threshold voltage of the NTFT and PTFT (V
In order to control the th) to be approximately the same, boron may be added during the film formation with diborane at a concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ .

When this silicon film is obtained by the sputtering method, the back pressure before sputtering is set to 1 × 10 ^-5 Pa or less,
Use single crystal silicon as a target, and add hydrogen to argon to 20
It was conducted in an atmosphere mixed with -80%. Eg Argon 20
% And hydrogen 80%. Deposition temperature is 150 ° C, frequency is 13.5
6MHz, sputter output 400-800W. Pressure is 0.5 Pa
Met.

When this silicon film is obtained by the plasma CVD method, the film forming temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) can be used as a reaction gas. Such a reactive gas was introduced into the PCVD apparatus, and high-frequency power of 13.56 MHz was applied to form a film.

The coating formed by these methods is
It is preferable that oxygen is 7 × 10 ²⁰ cm ⁻³ or less. When the oxygen concentration is high, the semiconductor layer is hard to crystallize, and therefore the thermal annealing temperature must be increased or the thermal annealing time must be lengthened. On the other hand, if the amount is too small, the leak current in the off state increases when the semiconductor layer is irradiated with light by the backlight used in the liquid crystal electro-optical device.
Therefore, in the range of 4 × 10 ¹⁹ to 4 × 10 ²¹ cm ⁻³ , it is possible to easily crystallize by thermal annealing at a medium temperature (600 ° C. or lower). For example, the coating used in this example was measured for impurities by SIMS (Secondary Ion Mass Spectroscopy). As a result, an oxygen amount of 8 × 10 ¹⁸ cm ⁻³ and carbon of 3 × 10 ¹⁶ cm ⁻³ were obtained. The hydrogen content was 4 × 10 ²⁰ cm ^-3 , which was 1 atom% in comparison with silicon 4 × 10 ²² cm ^-3 .

In order to further promote crystallization in the source and drain regions, the oxygen concentration is set to 7 × 10 ²⁰ cm ^-3 or less, preferably 7 × 10 ¹⁹ cm ^-3 or less, and a TFT constituting a pixel is formed. It is also effective to add oxygen, carbon or nitrogen to only a part of the channel forming region of the above by ion implantation so as to have a concentration of 5 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ to weaken the sensitivity to light. . In this case, especially in the TFT which constitutes the peripheral circuit, it is possible to further reduce the mixing of oxygen and to have a higher carrier mobility, facilitate the high frequency operation, and improve the peripheral area of the pixel. The switching TFT can reduce the leak current in the off state.

Oxygen in the coating film formed by these methods is 7 × 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3.
The following existing concentrations are preferable. This is because the degree of crystallization can be promoted when the crystallization is performed under the typical crystallization conditions.

Thus, the amorphous silicon film 50 is formed.
After making to a thickness of 0 to 3000Å, for example 1500Å, 450 to 70
Heat treatment was performed at a medium temperature for 12 to 70 hours at a temperature of 0 ° C. in a non-oxide atmosphere. For example, the temperature was kept at 600 ° C. in a nitrogen or hydrogen atmosphere. Since the amorphous silicon oxide film is formed on the surface of the substrate under the silicon film, no specific nuclei are present in this heat treatment and the whole is uniformly annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein. With this anneal,
The silicon film shifts from an amorphous structure to a highly ordered state, and a part thereof exhibits a crystalline state. In particular, a region having a relatively high degree of order during the film formation of silicon is particularly crystallized and tends to be in a crystalline state. However, since silicon existing between these regions is bonded to each other, the silicon members pull each other. When the crystal is also measured by laser Raman spectroscopy, a peak shifted to a low frequency side from the peak 522 cm ^-1 of silicon of a single crystal is observed. The apparent grain size is 50 to 500 Å when calculated from the half-width, and it looks like a microcrystal, but in reality, there are many regions with high crystallinity and they have a cluster structure. Was able to form a film of semi-amorphous structure in which silicon was bonded to each other (anchoring).
As a result, the coating is substantially grain boundary (G
It can be said that there is no (B). Since the carriers can easily move between the clusters through the anchored portions, the carrier mobility is higher than that of polycrystalline silicon in which so-called GB is clearly present. That is, hoo
Mobility (μh) = 10 to ²⁰⁰ cm ² / Vsec, electron mobility (μ
e) = 15 to 300 cm ² / Vsec is obtained.

On the other hand, when the film is polycrystallized by high temperature annealing at a temperature of 900 to 1200 ° C. instead of annealing at a medium temperature as described above, the segregation of impurities in the film due to solid phase growth from the nucleus. As a result, impurities such as oxygen, carbon, and nitrogen increase in GB, and the mobility in the crystal is large, but it creates a barrier in GB and hinders the movement of carriers there. As a result, it is difficult to obtain a mobility of 10 cm ² / Vsec or more.

That is, the embodiment of the present invention uses a silicon semiconductor having a semi-amorphous or semi-crystal structure as described above. Further, a silicon oxide film is used as a gate insulating film 420 and the thickness is 500 to 2000Å, for example, 1000.
Å formed. This is the same condition as the production of the silicon oxide film 51 as the blocking layer. A small amount of fluorine may be added during this film formation. Further thereafter, a metal coating made of aluminum was formed on the upper side. This was patterned using a photomask to form gate electrodes 413 and 416. For example, a channel length of 10 μm and a thickness of 0.3 μm were formed to obtain the shape of FIG. 5 (B). The extended portion of this gate electrode simultaneously forms the electrode wirings 43 and 44 in the Y direction in the top view of FIG.

Although aluminum is used as the gate electrode, other metal materials such as molybdenum, chromium, and a doped silicon film can be used. When aluminum is used as the gate electrode as in this embodiment, the periphery of the gate electrode is anodized, and the oxide film can be used to form contact holes of the source and drain region electrodes in a self-aligning manner. The feeding point can be provided near the channel region, and the influence of the resistance component in the source and drain regions can be reduced.

Next, in FIG. 5C, a photoresist is formed using a photomask, a mask is formed on the NTFT region, and a PTFT is manufactured first.

For PTFT, boron is added to the source / drain regions 410, 412, 415 at 1 × 10 ¹⁵ cm ^-3.
The doped amount was formed by self-alignment using the gate electrode as a mask by the ion implantation method.

In the case of producing an NTFT, the source and drain for the NTFT can be formed by adding phosphorus as an impurity in an amount of 1 × 10 ¹⁵ cm ⁻³ by an ion implantation method. In this embodiment, the PTFT 41 and the NTFT 40 are arranged in parallel as shown in FIG.
The FT region may be masked with photoresist or the like.

This ion implantation is performed by the gate insulating film 42.
I went through 0. However, in FIG. 5B, the silicon oxide on the silicon film may be removed using the gate electrodes 413 and 416 as a mask, and then boron and phosphorus may be directly ion-implanted into the silicon film.

Next, heating anneal was performed again at 600 ° C. for 10 to 50 hours. Then, the impurity region drains 400, 402 and 405 of the NTFT and the impurity region 4 of the PTFT of FIG.
N ⁺ , P ⁺ by activating the impurities of 10, 412, 415
Was prepared as. Further, channel forming regions 411 and 401 are formed below the gate electrode 413, and channel forming regions 414 and 404 are formed below the gate electrode 416 as semi-amorphous semiconductors.

In this way, the C / TFT shown in FIG. 4 can be manufactured without applying any temperature above 700 ° C. even though it is a self-aligned method. for that reason,
An expensive substrate such as quartz does not have to be used as the substrate material, and the process is extremely suitable for the liquid crystal electro-optical device of the present invention having large pixels.

Thermal annealing was performed twice in FIGS. 5 (A) and 5 (C).
However, the anneal of Fig. 5 (A) is omitted depending on the desired characteristics,
It is also possible to reduce the manufacturing time by using both of them as the anneal of FIG. 5 (C).

Before or after the annealing step of FIG. 5C, the surfaces of the gate electrodes 413 and 416 are anodized to form the aluminum oxide insulating film 53. Next, in FIG. 5D, an inter-layer insulator 418 was formed on its upper surface as a silicon oxide film by the above-mentioned sputtering method. The silicon oxide film may be formed by using the LPCVD method or the photo CVD method. For example, it is formed to a thickness of 0.2 to 0.4 μm. After that, a window 54 for an electrode was formed using a photomask. A photomask is used to form this window. At that time, a contact hole is formed by aligning the end of the aluminum oxide film 53 with that of the aluminum oxide film 53, and the distance between the feeding point to the impurity region and the channel formation region is formed. Can be shortened.

Further, aluminum was formed on all of them by a sputtering method, and a lead 45 was formed by using a photomask. Further, as shown in FIG. 4 (A), four TFTs are of a complementary type, and output terminals 405 and 415 of the TFTs are connected to the transparent electrodes 6 which are one pixel electrode of the liquid crystal device.
In order to connect to the ITO (indium
Tin oxide film) was formed. It was etched with a photomask to form the pixel electrode 6. This ITO was deposited at room temperature to 150 ° C and was accomplished by oxygen at 200-400 ° C or anneal in air.

Thus, the two PTFTs 41 and 2 are
One NTFT 40 and the transparent conductive film electrode 6 were formed on the same glass substrate 50. The characteristics of such a TFT are summarized in Table 1 below.

[0049]

[Table 1]

By using such a semiconductor, it was possible to provide a TFT with a high mobility, which was generally impossible. Therefore, for the first time, a complementary TFT could be constructed as an active element of the liquid crystal electro-optical device shown in FIG.

In this embodiment, the structure of the TFT is
Although the description has been given using the planar type TFT, the present invention is not particularly limited to this structure, and the effects of the present invention can be realized even with a TFT having another structure.

In FIG. 4, V _DD1 and V _DD2 in the Y-axis direction
In the Y-axis direction (hereinafter also referred to as Y line) 43, 4
4 was formed. In the X-axis direction, V _GG1 and V _GG2 and wirings (hereinafter also referred to as X-rays) 45 and 46 in the X-axis direction were formed.
Although FIG. 4 (A) is a plan view, a vertical sectional view of AA` is shown in FIG.
Shown in (B). A vertical cross-sectional view of BB 'is shown in Fig. 4 (C). Two
One NTFT 40 and two PTFT 41 are provided at the intersection of the Y line V _DD1 and the X line V _GG1 to form a C / TFT. Further, other pixels were also provided with a matrix structure using C / TFTs having the same structure as shown in FIG. 4 (A). NTFT40 and PTFT4 that compose C / TFT
Reference numeral 1 denotes source / drain 405 and 415 connected to the transparent conductive film 6 which is a pixel electrode through the contact 31, and the other source / drain regions 400 and 410 are one signal line having a matrix structure by the contact 30. It is connected to a certain X-ray 45. In addition, NTFT,
All gate electrodes of the PTFT are connected to 43 aluminum wires of the Y line which is one signal line. That is, two PTFTs are connected in series between the pixel electrode and the Y-line signal line 43, and similarly two NTFTs are connected in series between the pixel electrode and the Y-line signal line 43.
C / TFT could be constructed with FT.

Thus, one pixel was constituted by the transparent conductive film 6 and the C / TFT composed of four TFTs while being sandwiched between two X-rays and Y-rays (inside). By repeating this structure horizontally and vertically, 2
One example of a × 2 matrix or an expanded version of it 64
It has become possible to make liquid crystal electro-optical devices with large pixels such as 0 × 480 and 1280 × 960.

FIG. 4 shows the structure of one of the substrates sandwiching the liquid crystal in the liquid crystal electro-optical device. The structure is shown in FIG. 4, an alignment film and an alignment treatment are applied on the transparent conductive film of the liquid crystal driving element provided on the substrate, and a constant gap is provided between this substrate and the substrate having the other pixel electrode. And were arranged by a known method. Then, a liquid crystal material was injected in the meantime to complete the liquid crystal electro-optical device of this embodiment. If TN liquid crystal is used as the liquid crystal material, it is necessary to form the alignment film on both the transparent conductive films by rubbing the space between the substrates to about 10 μm.

When a ferroelectric liquid crystal is used as the liquid crystal material, the operating voltage is ± 20 V, and the cell interval is 1.5 to
The thickness is 3.5 μm, for example 2.3 μm, and the alignment film may be provided only on the counter electrode and the rubbing treatment may be performed.

When the dispersion type liquid crystal or the polymer type liquid crystal is used, the alignment film is not necessary and the switching speed is increased. Therefore, the operating voltage is set to ± 10 to ± 15 V, and the cell interval (a pair of liquid crystal sandwiching the liquid crystal is sandwiched). The distance between the substrates was reduced to 1 to 10 μm. In particular, when a dispersion type liquid crystal is used, since a polarizing plate is not necessary, it is possible to increase the amount of light both as a reflection type and a transmission type. Since the liquid crystal does not have a threshold, a large contrast can be obtained by using a driving element (C / TFT) which defines the clear threshold voltage, which is a feature of the C / TFT of the present invention, and crosstalk ( It was possible to eliminate the bad interference with the adjacent pixel).

In the present embodiment, semi-amorphous or semi-crystal is used as the semiconductor of the device. However, it goes without saying that a semiconductor having another crystal structure may be used for the same purpose.

In the present embodiment, a liquid crystal display device is used as an example of the liquid crystal electro-optical device, but a voltage is applied to the pixel electrode, and thereby a pixel in the display device which intends to perform some display operation is driven. It goes without saying that the C / TFT of the present invention can be used for the element to be formed.

A feature of the present invention is that one pixel has a plurality of TFs.
T is provided in a complementary configuration, and the electrode 6 constitutes the liquid crystal potential V _LC , which is either PTFT on and NTFT off or PTFT off and N.
That is, the TFT is fixed at either the on level or the on level.

The C / TFT of this embodiment will be described below with reference to FIG.
The operating principle of is explained. By applying a signal voltage to the pair of signal lines V _DD1 , V _DD2 , V _GG1 and V _GG2 shown in FIG. 3, a voltage is applied to the pixel portion and a liquid crystal electro-optical effect is exhibited. FIG. 6 shows the drive waveforms of the signal voltage applied to these four signal lines and the counter electrode on the other substrate in order to apply the voltage to the liquid crystal existing at the point A (the pixel located at the intersection of V _DD1 and V _GG1 ). A chart is shown. As can be seen from FIG. 6, what is shown in FIG. 3 is a 2 × 2 matrix, so one frame is divided into two. The voltage actually applied to the liquid crystal 3 in this case is shown as a block A voltage. Although only the ON and OFF states are shown in FIG. 6, in order to perform gradation display, the signal voltage waveform applied to V _DD1 or V _DD2 should be changed according to its strength. Good. For example, in the case of FIG. 3, if it is desired to increase the transmittance of the liquid crystal at the point A, a high voltage signal voltage may be applied according to the transmittance of the liquid crystal of V _DD1 in FIG. If a low rate is desired, a low voltage signal voltage may be applied. (That is, gradation display can be performed by the applied voltages of V _DD1 and V _DD2 .)

[0061] On the other hand, the signal voltage applied to the V _GG1, V _GG2 must be greater than the threshold voltage V _th of the _{C / TFT (V GG »V th} ). Further, as shown in FIG. 6, applying a V _OFFSET voltage, which can be called a threshold voltage, which is a voltage at which the liquid crystal reacts to the applied voltage, to the counter electrode at a negative potential is the transmittance of the liquid crystal and the voltage applied to the liquid crystal. This is useful when gradation display is performed using the relationship of.

In such driving, when one of the two TFTs constituting the PTFT 41 or the NTFT 40 becomes defective due to a short circuit or a leak, the applied voltage of V _DD1 or V _DD2 is normally V _GG1 or V _DD1.
Regardless of the selection signal of _GG2 , it is added to the liquid crystal pixel portion as it is, and it is always in the ON state (or OFF state). V _DD1 or V as in the present invention
By providing two PTFT and NTFT in series between _DD2 and the pixel electrode, even if the source and drain of one TFT are short-circuited, the other TFT can control the selection / non-selection. It was possible to improve the yield of the liquid crystal electro-optical device.

At the same time, the total of these four TFTs is C / T.
With the FT structure, the instability of the liquid crystal potential, which was a conventional problem, can be removed, the liquid crystal potential can be fixed, and a stable liquid crystal electro-optical effect can be exhibited.

[Embodiment 2] In this embodiment, FIG. 7 (A) is a plan view thereof, FIG. 7 (B) is a sectional view taken along line AA ^, and FIG. 7 (C) is taken along line BB ^. It is a liquid crystal electro-optical device having a configuration showing a cross-sectional view.

The equivalent circuit of this embodiment is as shown in FIG. 1, and the switching element portion is composed of four TFTs, and one PTFT and NTFT are C / TFT configured,
This C / TFT is provided in series between two sets of V _DD1 and V _DD2 and the pixel electrode 6.

In this embodiment, the transparent conductive film 6 which is the pixel electrode is manufactured lastly in the first embodiment, but the transparent conductive film 6 is first formed and patterned to form the pixel electrode 6. I will get it. At this time, at the same time, an electrode portion 703 for connecting one set of C / TFT and the other C / TFT was also provided.

By doing so, when the transparent conductive film such as ITO is patterned, the lower element is destroyed,
The configuration of the present invention can be obtained by a process that does not cause disconnection of wiring.

In the case of this embodiment, two PTFTs 7 are used.
The positions of the 1 and 72 and the two NTFTs 73 and 74 are electrically equivalent at any position, and the same effect as that of the first embodiment is exhibited, and at the same time, the TFTs are arranged at arbitrary positions depending on the degree required in the TFT manufacturing process. be able to.

Further, the structure of the element is an inverted stagger type TF.
As T, in the PTFTs 71, 72, the gate electrodes 75, 76 and the source / drain regions 700, 702, 7
04 and 706 are provided on the gate insulating films 708 and 709.

In this embodiment, as these semiconductor layers, P
The silicon semiconductor layer produced by the CVD method was subjected to thermal annealing treatment, and the semiconductor layer whose crystallization was promoted was used.

Further, although the NTFT is not shown, the PT
Although it has the same structure as the FT and is provided beside the PTFT, the positional relationship is not particularly limited, and the PTFT and the NTFT can be arranged in an arbitrary positional relationship.

Since other manufacturing steps are the same as those in the first embodiment, description thereof will be omitted.

In the present invention, the TFTs are arranged in series because it is assumed that the defective mode of the TFT is a short circuit between the source and the drain and a leak, but in the case of the defective mode due to the breakdown of the gate insulating film, In order to guarantee the operation, it is necessary to electrically disconnect the gate electrode of the defective TFT from the signal line. Therefore, when the gate electrode is disconnected in series, all the TFTs operating with the gate electrode cannot operate. Not compatible, in this case multiple C /
By providing the TFTs in parallel, when a malfunctioning TFT occurs, the gate electrode of the malfunctioning TFT can be easily electrically separated from the signal line.

However, in this case, it is necessary to supply the power supply line to the source and drain regions independently, and it is necessary to devise the layout pattern.

[0075]

EFFECT OF THE INVENTION By adopting such a configuration, P
ON / OFF of C / TFT consisting of TFT and NTFT
It is possible to obtain a display device in which the potential of the pixel portion 3 at that time is sufficiently and stably fixed to "1" and "0" and the level thereof does not drift during one frame.

Further, in the present invention, such a C / TFT
A plurality of TFTs are provided in series, and even if some of the four TFTs malfunction (specifically, a short circuit or leak between the source and drain), the other TFTs can compensate the operation. It is. That is, since the C / TFT is provided in series with the pixel, even if a part of the pixel is always in the conductive state, the remaining TFT turns on and off the pixel.
This is because the FF can be controlled.

Since they are arranged in series, they are turned off.
The minute current leak in the state is less likely to occur due to the double resistance of a normal TFT, and the potential of the pixel portion 3 can be fixed to "1" and "0" sufficiently stably. Became.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a case where the configuration of the present invention is assembled in a 2 × 2 matrix.

FIG. 2 shows a conventional example without using the present invention.

FIG. 3 shows an example of an embodiment of the present invention.

FIG. 4 shows a top view and a sectional view of the first embodiment.

FIG. 5 shows an example of a manufacturing process diagram of a TFT.

FIG. 6 shows an example of a signal for driving a C / TFT.

FIG. 7 shows a top view and a sectional view of the second embodiment.

[Explanation of symbols]

6 Pixel electrode part 40 P-channel thin film transistor (PTFT) 41 N-channel thin film transistor (NTFT) 400, 402, 405 Source and drain electrodes 410, 412, 415 Source and drain electrodes 413, 416 Gate electrode

Continuation of the front page (56) Reference JP-A-2-85826 (JP, A) JP-A-3-58019 (JP, A) JP-A-60-66288 (JP, A) JP-A-64-32235 (JP , A) JP 64-50028 (JP, A) JP 59-105617 (JP, A) JP 58-71663 (JP, A) JP 63-119268 (JP, A) JP 2-28315 (JP, A) JP-A-2-46721 (JP, A) JP-A-53-27483 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/1368 G09F 9/30 338 H01L 21/336 H01L 27/08 331 H01L 29/786

Claims (6)

(57) [Claims] 1. A active matrix device having a switching element connected to the pixel electrode, the switching element has two P-channel connected to the thin film transistor in series with two N-channel type connected in series Type N-channel type thin film transistors connected in series.
The two P-channel type thin film transistors connected in series with the transistor are connected to the pixel electrode in one of the source and drain regions, connected to the first signal line in the other of the source and drain regions, and connected in series. Two N-channel thin film transistors connected
The gate electrodes of the two P-channel type thin film transistors connected in series with the transistor are respectively connected to the second signal line intersecting with the first signal line, and the two N-channel type thin film transistors connected in series are connected. And a channel forming region of the two P-channel type thin film transistors connected in series each include crystalline silicon. 2. The active matrix device according to claim 1, wherein the gate electrode is made of aluminum, molybdenum, or chromium. 3. The active matrix device according to claim 1, wherein the channel formation region has a peak observed by Raman spectroscopy shifted to a lower wave number side than 522 cm ⁻¹ . 4. A active matrix device having a switching element connected to the pixel electrode, the switching element has two P-channel connected to the thin film transistor in series with two N-channel type connected in series Type N-channel type thin film transistors connected in series.
The two P-channel type thin film transistors connected in series with the transistor are provided at the intersection of the first signal line and the second signal line, and are connected between the first signal line and the pixel electrode. And two N-channel type thin film transistors connected in series.
The gate electrodes of the two P-channel type thin film transistors connected in series with the transistor are respectively connected to the second signal line, and are connected in series with the two N channel type thin film transistors connected in series. two P-channel thin film transistor is respectively, a crystalline semiconductor film containing silicon above the substrate was active matrix device characterized by having a gate electrode, a gate insulating film. 5. The active matrix device according to claim 4 , wherein the gate electrode is made of aluminum, molybdenum, or chromium. 6. The method according to claim 4 or 5, wherein the crystalline semiconductor film, an active matrix device characterized by peaks observed by Raman spectroscopy is shifted to a lower wavenumber side than 522cm ^-1.