JP3422781B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating gate type field effect transistor (hereinafter referred to as TFT) having a thin film structure used for an active type liquid crystal display device or an image sensor, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, an active type liquid crystal display device using a TFT has been known. In this case, the TFT uses a polycrystalline semiconductor having an amorphous or crystal grain boundary,
A TFT having only one of the P type and the N type conductivity type is used for one pixel. That is, generally N-channel TFT (NTFT
That is) is connected in series to the pixel.

However, a semiconductor having an amorphous structure has a low carrier mobility, and in particular, the carrier mobility of a hole is 0.
Small as 1 cm ² / Vsec or less. In addition, the semiconductor of polycrystalline structure,
Due to impurities such as oxygen segregated at the crystal grain boundaries and dangling bonds, the drain breakdown voltage cannot be made sufficiently large, and it is difficult to form a P-channel TFT. Furthermore, these have photosensitivity (called photosensitivity PS),
It has a defect that Vg- _ID (gate voltage-drain current) characteristics and the like are greatly changed by light irradiation.

Therefore, it has been an important step to form a light shielding layer so that the channel formation region is not irradiated with light.

[0005]

In FIG. 3, the liquid crystal (1
2), which is connected in series to it to provide NTFT (11), which are arranged in a matrix. Generally 640
It is often set to x480 or 1260x960, but in this drawing, a 2x2 matrix arrangement is simply used with the same meaning. Voltages were applied to the respective pixels from the peripheral circuits (16) and (17) to selectively turn on predetermined pixels and turn off other pixels. Then, if the on / off characteristics of the TFT are generally good, a liquid crystal display device with high contrast can be manufactured. However, when actually manufacturing such a liquid crystal display device, the voltage V _LC (10) of the output of the TFT, that is, the input (referred to as liquid crystal potential) to the liquid crystal is often "1" (High) when it should be "1" (High). In some cases, "(High)" does not occur, and conversely, "0" (Low) does not occur when "0" (Low) should occur. The liquid crystal (12) is essentially insulating in its operation, and when the TFT is off, the liquid crystal potential (V _LC ) is in a floating state. Since this liquid crystal (12) is equivalently a capacitor, _VLC is determined by the charge accumulated therein. This charge is photo-sensitive in conventional TFTs, so current is leaked through the TFT channel when there is insufficient shading.
(15), and as a result, the level of V _LC fluctuates. Furthermore, the liquid crystal has a relatively small resistance at R _LC ,
When the black (14) occurs, V _LC becomes halfway. Therefore, a high yield cannot be achieved in a liquid crystal display device having 200,000 to 5 million pixels in one panel.

[0006]

SUMMARY OF THE INVENTION The present invention is a thin film type insulated gate field effect transistor which is made non-photosensitive. In addition, the source and drain should be more P ⁺ or N ⁺
It is for that. In the active type liquid crystal display device as its application, the liquid crystal potential is set to one frame.
The TFT is improved to keep the same level as the initial value for a certain period and keep the level from drifting.

According to the present invention, the semiconductor material of the channel forming region of the TFT is a material which is non-photosensitive to light.
Silicon in which an impurity such as oxygen, carbon, or nitrogen is selectively added to a T 2 channel forming region is used, and the region is made crystalline but has no photosensitivity. The ionization rate of impurities showing P or N type conductivity is improved by not adding or reducing the amount of impurities in the source and the drain forming the pair of impurity regions.

Further, the total amount of O, C, and N impurities is selectively added to the channel formation region by an ion implantation method or the like in a range of 1 × 10 ²⁰ cm ^{−3 to} 20.
Atomic%, preferably 3 × 10 ²⁰ cm ^{-3 to} 5 atomic% makes it non-photosensitive, but 500 to 750
It is crystallized by heat treatment at ℃, and the carrier mobility is set to 5 cm ² / Vsec or more, so grain boundaries are substantially eliminated,
In addition, it is a semiconductor material having crystallinity.

This material is non-photosensitive, that is, the change in current in the ON state is 10% or less, and in the OFF state (subthreshold state), the dark current is 10 ^-9 A and the order is 10. ^-7
A power increase below the order of A, that is, the degree of change within 2 digits 20
It was accomplished by irradiating 00 candela with visible light.

When the present invention is applied to a liquid crystal display device, each pixel (transparent conductive film and TF
The output terminal of the complementary TFT was connected to one transparent conductive film (pixel) electrode (combined with T). That is, all the pixels arranged in a matrix have P-channel TFTs.
A pixel is formed by connecting (hereinafter referred to as PTFT) and NTFT as a complementary type (hereinafter referred to as C / TFT).

A typical example thereof is shown as a circuit in FIG. An example of an actual pattern layout (arrangement diagram) is shown in FIG.

That is, in the example of the 2 × 2 matrix shown in FIG. 4, PTFT and NTFT gates are connected to each other, and Y
It was connected to the axial line V _GG (22), or V _{GG '} (23). Also, the common output of C / TFT is connected to the liquid crystal (12). The PTFT input (Vss side) is connected to the X-axis direction lines V _DD (18) and V _{DD '} (18'), and the NTFT input (V _SS side) is connected to Vss (19). Then, when V _DD (18) and V _GG (22) are "1", the liquid crystal potential (1
0) becomes "0", and V _DD (18) is "1" and V _GG (22) is "0".
At, the liquid crystal potential (10) becomes "1". That is, V _GG and V _LC are in “reverse phase”.

The liquid crystal potential (10) is fixed to either V _DD (18) or the ground or V _SS (19).
It never becomes a ting.

In FIG. 4, if NTFT and PTFT are arranged in reverse, V _GG and V _LC can be “in phase”.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on Examples.

[0016]

EXAMPLES Example 1 In this example, the present invention will be described with reference to FIGS. 1 and 2. The manufacturing process when a C / TFT is not manufactured on a glass substrate is shown based on Figs.

In FIG. 1, AN glass and Pyrex
A glass (1) that can withstand a heat treatment of about 600 ° C. (registered trademark) glass, etc., is coated with a silicon oxide film as a blocking layer (38) by a magnetron RF (radio frequency) sputtering method at a thickness of 1000 to 30
It was made to a thickness of 00Å.

The process conditions are 100% oxygen atmosphere and film forming temperature.
The temperature was 150 ° C, the output was 400 to 800W, and the pressure was 0.5Pa. The deposition rate using quartz or single crystal silicon for the target is 30Å
/ Min.

On top of this, the total amount of oxygen, carbon or nitrogen
7 x 10¹⁹cm^-3Preferably 1 × 10¹⁹cm ^-3Add only the following
Undeposited silicon film by LPCVD (low pressure vapor phase) method, sputtering method
Alternatively, it is formed by the plasma CVD method. Decompression gas phase method
If formed, 450 to 100 ° C below the crystallization temperature 450
Disilane (Si at ~ 550 ° C, for example 530 ° C₂H₆) Or bird
Silane (Si₃H₈) Was supplied to the CVD device to form a film. Reactor
The internal pressure was 30 to 300 Pa. Deposition rate is 30-100 Å / min
Met. Threshold voltage (Vt
In order to control h) to be approximately the same, boron is used with diborane.
1 x 10¹⁵~ 5 x 10¹⁷cm^-3Added during film formation as the concentration of
You may.

When the sputtering method is used, the back pressure before sputtering is set to 1 × 10 ^-5 Pa or less, single crystal silicon is used as a target, and argon is mixed with hydrogen in an amount of 50 to 80% by volume. For example, argon was 20% by volume and hydrogen was about 80% by volume. The film forming temperature was 150 ° C., the frequency was 13.56 MHz, and the sputter output was 400 to 800 W. The pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a reactive gas. these
The film was introduced into a PCVD device, and high-frequency power of 13.56 MHz was applied to form a film.

The coating formed by these methods is
Oxygen contained only 7 × 10 ¹⁹ cm ^-3, preferably 1 × 10 ¹⁹ cm ^-3 or less. Then, this coating film has photosensitivity, but has the feature that it is more easily crystallized than in the case where no oxidation or the like is added.

In this embodiment, as shown in FIG.
With the photomask of, the semiconductor film (2), (2 ')
And other parts were removed. Further, using the second photomask, the photoresist (35) was selectively removed. The removed regions (36) and (35) cover the channel formation regions of the PTFT and NTFT, respectively. C, N or O, for example O, is added to the openings (35) and (36) in an amount of 5 × 10 ^{14 to} 5 × 10 ¹⁶ cm.
^{A -2} dose impurity was added by ion implantation. The applied voltage was 30 to 50 KeV, for example 35 KeV.

As a result, the pair of impurity regions, that is, the source and drain regions, had very few impurities such as oxygen, and crystallization proceeded more strongly. Further, a part thereof is provided in a later process to a depth of 0 to 5 .mu.m in the lateral direction in a certain region of the source and drain. That is, although 0 is ideally preferable, it is preferable to provide 0 in the range of about 5 μm in the lateral direction in consideration of process problems.

That is, C, O, N may be added to impart non-photosensitivity, but if the amount is too large, it becomes difficult to crystallize even in the subsequent heat treatment, and the carrier mobility is 5 cm ² / Vsec or more, preferably 10 cm ² / Vsec or more. This is because it is not possible to obtain ~ 100 cm ² / Vsec.

Thus, the amorphous silicon film 50 is formed.
0 ~ 10000 Å (1μm), for example, after making a thickness of 2000 Å,
It was heat-treated in a non-oxide atmosphere for 12 to 70 hours at a medium temperature of 500 to 750 ° C. at which the crystal growth did not occur. For example, the temperature was kept at 600 ° C. in a nitrogen or hydrogen atmosphere.

Since a silicon oxide film having an amorphous structure is formed on the surface of the substrate below the semiconductor film, no specific nuclei are present in this heat treatment, and the whole is uniformly heated and annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

Due to this annealing, the semiconductor film in the channel forming region shifts from the amorphous structure to a highly ordered state, and a part thereof exhibits a crystalline state. In particular, a region having a relatively high degree of order during the film formation of silicon is particularly crystallized and tends to be in a crystalline state. However, since silicon existing between these regions forms a bond with each other, the silicon members pull each other. As a crystal, the peak of the single crystal silicon (111) crystal orientation was measured by laser Raman spectroscopy.
A (111) crystal peak with lattice strain shifted to the lower frequency side than cm ^-1 is observed. The apparent grain size is 50 to 500 Å, which is similar to that of microcrystals, when calculated from the half-width, but in reality, there are many regions with high crystallinity, which have a cluster structure. Was able to form a film of semi-amorphous structure in which silicon was bonded to each other (anchoring).

For example, when the distribution in the depth direction is measured by SIMS (Secondary Ion Mass Spectroscopy), the lowest region as an additive (impurity) (the surface or a position apart from the surface (inside))
In the above, oxygen was 3.4 × 10 ²⁰ cm ^-3 and nitrogen was 4 × 10 ¹⁷ cm ^-3 . Hydrogen is 4 × 10 ²⁰ cm ^-3 , and silicon is 4 × 10 ²² cm ^-3.
Was 1 atom%.

This crystallization has an oxygen concentration of, for example, 1.5 × 10 ²⁰
At cm ^-3, it is possible to perform heat treatment at 600 ℃ (48 hours) with a film thickness of 1000Å. When this is set to 5 × 10 ²⁰ cm ^-3 , the film thickness becomes 0.
Crystallization by annealing at 600 ° C. was possible if the thickness was increased to 3 to 0.5 μm, but heat treatment at 650 ° C. was necessary for crystallization at a thickness of 0.1 μm. That is, the thicker the film thickness and the lower the concentration of impurities such as oxygen, the easier the crystallization was.

As a result, this coating exhibits a state in which it may be said that it is substantially free of grain boundary (referred to as GB). Since the carriers can easily move between the clusters through the anchored portions, the carrier mobility is higher than that of polycrystalline silicon in which so-called GB is clearly present. That is, the hole mobility (μh) = 10 to 50 cm ² / Vsec and the electron mobility (μe) = 15 to 100 cm ² / Vsec can be obtained.

Further photo sensitivity is, Vg as TFT (gate voltage) -I _D (drain current) light of 2000 lux from the glass side while obtaining a characteristic at least Cha
Irradiation on the channel formation region, I _D only fluctuates less than 10% in the ON-state region (no drift), or I _D only increases by 2 digits or less (drift) in the sub-threshold voltage region. It was measured as a condition (condition in which the off-state current is sufficiently small). Then, if the oxygen concentration in the channel formation region is a low concentration such as 8 × 10 ¹⁹ cm ^-3 , there is a drift, but if it is 1 × 10 ²⁰ cm ^-3 or more, preferably 3 × 10 ²⁰ cm ^-3 or more No drift was seen in either PTFT or NTFT.

On the other hand, when the film is polycrystallized by a high temperature anneal at 900 to 1200 ° C. instead of the anneal at a medium temperature as described above, segregation of impurities such as oxygen in the film due to solid phase growth from nuclei. As a result, impurities such as oxygen, carbon, and nitrogen increase in GB, and the mobility in the crystal is large, but it creates a barrier in GB and hinders the movement of carriers there. As a result, only a mobility of 5 cm ² / Vsec or less can be obtained, and the breakdown voltage is actually lowered due to drain leakage at the crystal grain boundaries.

That is, in the embodiment of the present invention, as described above, a silicon semiconductor having a semi-amorphous or semi-crystal structure having no photosensitivity and having crystallinity is used.

Further, a silicon oxide film was formed thereon as a gate insulating film with a thickness of 500 to 2000Å, for example 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. A small amount of fluorine may be added during this film formation.

In order to improve the interface characteristics between the silicon oxide and the underlying semiconductor film and remove the interface level, it is preferable to apply ultraviolet light at the same time to perform ozone oxidation. That is, when the sputter method and the photo CVD method were used in combination under the same conditions as when the blocking layer (38) was formed, the interface level could be reduced.

After this, phosphorus is added to the upper side in an amount of 1 to 5 ×.
A silicon film with a concentration of 10 ²⁰ cm ^-3 or this silicon film and molybdenum (Mo), tungsten (W), MoSi _{2 on it.}
Alternatively, a multilayer film with WSi ₂ was formed. This was patterned with a third photomask. Then, a gate electrode (4) for PTFT and a gate electrode (4 ') for NTFT were formed. For example, the channel length is 10 μm, and the gate electrode is made of phosphorus-doped silicon.
2 μm, and molybdenum was formed thereon to a thickness of 0.3 μm.

In FIG. 1C, the photoresist (31 ')
Is formed using a photomask, and the source (5) for PTFT,
A dose of 1 to 2 × 10 ¹⁵ cm ^-2 of boron was added by an ion implantation method to a region which becomes a drain (6) and has a low oxygen concentration.

Next, as shown in FIG. 1D, a photoresist (31)
Was formed using a photomask. And NTFT software
− 1 × 10 phosphorus is added to the region that becomes the drain (5 ′) and drain (6 ′).
¹⁵cm ^-2Was added by the ion implantation method.

These are performed through the gate insulating film (3). However, in FIG. 1B, the silicon oxide on the silicon film is removed by using the gate electrodes (4) and (4 ′) as masks, and then,
Boron or phosphorus may be directly ion-implanted into the silicon film.

Next, after removing these photoresists (31), heating anneal was performed again at 630 ° C. for 10 to 50 hours. And PTFT source (5), drain (6), NTFT source
The (5 ') and drain (6') were prepared as P ⁺ and N ⁺ regions by activating impurities.

Since oxygen and the like are small in this region, the crystallinity is further advanced even at the same temperature. As a result, the ionization rate (the number of acceptors or donors / the amount of implanted impurities) of impurities giving a conductivity type such as boron or phosphorus could be varied up to 50 to 90%.

Channel forming regions (7) and (7 ') are formed as semi-amorphous semiconductors under the gate electrodes (4) and (4').

An end portion (4) of a region to which impurities such as oxygen are added
By extending (2) from the end (41) of the impurity region to the impurity region, the ionization rate of boron or phosphorus here is reduced, but at the same time, crystals are formed on the surface where N ⁺ -I and P ⁺ -I exist. Grain boundaries are less likely to exist, and as a result, the drain breakdown voltage can be increased.

By doing so, the C / TFT can be manufactured without applying a temperature of 700 ° C. or higher in all steps even though it is a self-aligned method. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and the process is extremely suitable for the large-pixel liquid crystal display device of the present invention.

Thermal annealing was performed twice in FIGS. 1 (A) and 1 (D).
However, the anneal in Fig. 1 (A) is omitted depending on the desired characteristics,
Both may be combined by the thermal anneal of FIG. 1 (D) to reduce the manufacturing time. In Fig. 2 (A), interlayer insulation
(8) was performed by forming the silicon oxide film by the above-mentioned sputtering method. The silicon oxide film may be formed by using the LPCVD method or the photo CVD method. For example, it is formed to a thickness of 0.2 to 1.0 μm. Then, as shown in FIG. 2 (A), a window (32) for an electrode was formed using a photomask.

Further, the total amount of aluminum is 0.5 to
The lead (9), which has a thickness of 1 μm, is formed by the sputtering method.
(9 ') and contacts (29) and (29') were prepared as shown in FIG. 2 (B) using a photomask.

The characteristics of such a TFT will be abbreviated. Mobility (
μ), threshold voltage, drain breakdown voltage (V _BDV ), and photosensitivity (PS) are shown in Table 1.

[0049]

[Table 1]

The above is a channel length of 10 μm and a channel width of 30 μ.
The case of m is shown. By using such a semiconductor, it was possible to obtain a large mobility in a TFT, which was generally considered impossible, and in addition, there was no photosensitivity, and a drain breakdown voltage was obtained at a large level. Therefore, the NTFT or C / TFT for the liquid crystal display device shown in FIGS. 3 and 4 could be constructed for the first time.

This embodiment is an example of a liquid crystal display device, and further, in order to connect the output of this C / TFT to a pixel, FIG.
In (B), an organic resin (34) such as polyimide was formed. Then, the window was opened again using a photomask. In order to connect the output terminals of the two TFTs to one transparent electrode of the liquid crystal device, ITO (indium tin oxide film) was formed by sputtering. It was etched with a photomask to form a transparent electrode (33). This ITO was deposited at room temperature to 150 ° C, and it was accomplished by oxygen at 200-300 ° C or anneal in air.

In this way, the PTFT (21), the NTFT (11) and the electrode (33) of the transparent conductive film were formed on the same glass substrate (1).

[Embodiment 2] FIG. 5 (A) shows an example corresponding to FIG.
An example is shown. V in the X-axis direction_DD(18), V_SS(19), V _DD'(1
Form the wiring in the X-axis direction (hereinafter also referred to as X-ray) having 8 ')
I made it. Note that the Y-axis direction is V_GG(22), V_GG'(23) and Y axis
The wiring (hereinafter also referred to as the Y line) is formed. Drawing (A)
Although it is a plan view, a vertical cross-sectional view of AA 'is shown in FIG. 5 (B).
You A vertical cross-sectional view of BB 'is shown in Fig. 5 (C).

In addition, the PTFT (21) is connected to the X-ray V_DD(18) and Y line V_GG(2
Provided at the intersection with 2), V_DD(18) and V _GG'(23) intersection
Also, PTFTs (21 ') for other pixels are similarly provided.
Also, NTFT (11) is V_SS(19) and V_GGProvided at the intersection with (22)
Has been. V_SS(19) and V_GGOthers on the lower side of the intersection with (22)
An NTFT (11 ') is provided for each pixel. With C / TFT
It has a matrix structure. Those PTFTs are source
(5) is X-ray V through contact (32)_DDConnected to (18)
And the gate (4) is a Y-line V in which multiple layers are formed._GGConnected to (22)
It is tied. Drain (6) via contact (29)
It is connected to the electrode (33) of the transparent conductive film.

Channel forming regions of these NTFT and PTFT
Oxygen was intentionally added to (7) and (7 '), but not added to the source and drain.

On the other hand, in NTFT, the source (5 ') makes contact (3
2 ') is connected to X-ray V _SS (19), and gate (4') is Y
To the line V _GG (22), the drain (6 ') is connected to the transparent conductive film (33) via the contact (29'). Thus two X-rays
One pixel was constituted by the transparent conductive film (33) and the C / TFTs (21) and (11) between the pixels (18) and (19) (inside). By repeating such a structure horizontally and vertically, one example of a 2 × 2 matrix or an enlarged liquid crystal display device with a large screen of 640 × 480 or 1280 × 960 can be manufactured.

The feature here is that two TFTs are provided for one pixel.
Are provided in a complementary configuration, and the electrode (33) constitutes the liquid crystal potential V _LC , which means that the PTFT is on.
NTFT is off, or PTFT is off and NTFT is on,
It is to be fixed at any level.

Even if light is irradiated from the glass substrate side, not only the C / TFT has a source and a drain, but especially the channel forming region is non-photosensitive to light, so that it is not only a reflective type but also a transparent type. Even an optical type liquid crystal display device could be operated without providing a shielding means.

As is apparent from FIG. 5, even if Vss of the control element is newly increased, the aperture ratio (total area (34)
On the other hand, the ratio of the effective liquid crystal display area (33) to be actually displayed is no different from the conventional case where a TFT having only one conductivity type is connected to each pixel in FIG. 1 and there is no disadvantage.

In FIG. 5, an alignment film and an alignment treatment are applied to the transparent conductive films, and a fixed space is provided between this substrate and the substrate having the other liquid crystal electrode (FIG. 5 (34)). They are arranged on each other by a known method. Then, liquid crystal was injected in the meantime to complete a liquid crystal display device.

If TN liquid crystal is used as the liquid crystal material, it is necessary to form the alignment film on both the transparent conductive films by rubbing it with an interval of about 10 μm.

When FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is ± 20 V, and the cell spacing is
1.5 to 3.5 μm, eg 2.3 μm, opposite electrode (Fig. 5)
An alignment film may be provided only on (34) and a rubbing treatment may be performed.

When the dispersion type liquid crystal or the polymer liquid crystal is used, the alignment film is unnecessary and the operating voltage is ± 10 to ± 15 V and the cell interval is 1 in order to increase the switching speed.
Thinned to ~ 10μm.

In particular, when a dispersion type liquid crystal or a polymer liquid crystal is used, a polarizing plate is not necessary, so that the light amount can be increased both as a reflection type and a transmission type. Since the liquid crystal has no threshold hold, the C / TFT of the present invention is
As shown in Fig. 3, by using the C / TFT type in which a clear threshold voltage is specified, it was possible to realize a large contrast and to eliminate crosstalk (bad interference with adjacent pixels).

In the second embodiment, the C / TFT is connected to the V _DD side.
PTFT and NTFT were formed on the Vss side. Then the output is V
_You can determine a definite level to make _DD or Vss. However, for V _GG , V _LC becomes an inverter (reverse phase).

The 2Tr / cell method (C / TFT method) in the case where V _GG and V _LC are in phase (voltage in the same direction) is shown in the following embodiment.

[Embodiment 3] In this embodiment, in FIG. 4 and FIG. 5, the NTFT (11) is reversely connected to the V _DD side and the PTFT (2
It has a C / TFT configuration that connects 1). Then, (the output of the positive voltage when the V _GG positive voltage, the output of the negative voltage when the negative voltage) V _LC is V _GG phase with its output becomes, the output potential V _GG -Vthp and V _GG - It is given by Vthn. Vthp
When Vthn and Vthn are different, it is preferable to add an offset bias to the other terminal (13) of the liquid crystal shown in FIG.
Thus, although there is a drawback in that V _GG needs to be larger than V _DD, it has the feature that even if there is some leakage between the gate electrode and V _LC , it does not matter so much.

In such a case, the PTFT is similarly performed in FIG.
The NTFT and NTFT may be provided in reverse. Therefore, the manufacturing process and the aperture ratio in Example 2 and FIG. 5 can have exactly the same values. Others are the same as those in the second embodiment.

[Embodiment 4] In this embodiment, each pixel shown in FIG. 3 is provided with 1T in which only NTFT is connected to each pixel or the like.
r / cell method. Then, the level of V _LC becomes floating and varies, but the TFT shown in the present invention
Since it is non-photosensitive, it is not necessary to provide a light-shielding means for preventing the TFT from being irradiated with light in actual use, and an active type liquid crystal display device can be manufactured more easily than before.
Others are the same as in the first and third embodiments.

[0070]

INDUSTRIAL APPLICABILITY The present invention makes the non-photosensitive semi-amorphous semiconductor by adding impurities such as oxygen to the channel forming region by making it non-photosensitive to NTFT and PTFT, and at the same time, the source and the drain. In order to improve the ionization rate of the donor or acceptor without adding these impurities, the light shielding means became unnecessary. Further TF
By connecting to each pixel that is matrixed as T, especially C / TFT, 1) it is possible to make a liquid crystal display device that does not require a shielding means. 2) reduction of the sheet resistance of the source and drain. 3) It has many features that the drain breakdown voltage has been improved by 3 to 10V by making oxygen spread over the source and drain side rather than PI and NI.

The present invention shows an example in which a non-photosensitive TFT is manufactured and its application is applied to a liquid crystal display device. However, it can also be used as a load or a three-dimensional element in other semiconductor devices, for example, an image sensor, a monolithic integrated circuit.

In the present invention, for the C / TFT, a non-photosensitive material having a semi-amorphous or semi-crystalline silicon as a main component is used as a semiconductor. However, other crystalline semiconductors may be used if possible for the same purpose. In addition, high-speed processing was performed by using a self-aligned C / TFT. However, it goes without saying that the TFT may be made by a non-self-aligned method without using the ion implantation method.

[Brief description of drawings]

FIG. 1 shows a P-channel type and an N-channel type of the present invention.
6A to 6C are diagrams showing a manufacturing method of a TFT.

FIG. 2 shows P-channel type and N-channel type of the present invention.
6A to 6C are diagrams showing a manufacturing method of a TFT.

FIG. 3 is a diagram showing a liquid crystal display device using a 1Tr / cell type active TFT.

FIG. 4 is a circuit diagram of a 2Tr / cell type active liquid crystal device using the complementary TFT of the present invention.

5 is a plan view (A), vertical sectional views (B), (C) of one substrate of the liquid crystal display device corresponding to FIG.

[Explanation of symbols]

(1) ・ ・ ・ ・ Glass substrate (2), (2 ') ・ ・ Semiconductor thin film (3) ・ ・ ・ ・ Gate insulating film (4), (4') ・ ・ Gate electrode (5), (5 ' ) ・ Source (6), (6 ') ・ ・ Drain (7), (7') ・ ・ Channel formation region (10) ・ ・ ・ ・ Liquid crystal potential (V _LC ) (11) ・ ・ ・ ・N-channel thin film transistor (NTFT) (12) ··· Liquid crystal (14), (15) · Leakage resistors (16), (17) · Peripheral circuits (18), (18 ′) · Vss ( (One of X-rays) (19), (19 ') ・ V _DD (One of X-rays) (21) ・ ・ ・ ・ P-channel thin film transistor (PTFT) (22), (23) ・ V _GG , V _GG '(Y line) (31), (31') ・ Photoresist (38) ・ ・ ・ ・ Blocking layers (33), (34) ・ Transparent electrode ～ ・ ・ ・ Process using photomask

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/146 H01L 29/78 616V (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21 / 8238 H01L 27/08 331 H01L 27/092 H01L 27/146

Claims (4)

(57) [Claims] 1. An N-channel insulated gate field effect transistor.
Transistor and P-channel insulated gate field effect transistor
Semiconducting transistors using complementary transistors consisting of transistors
A body device, The N-channel insulated gate field effect transistor
And the P-channel insulated gate field effect transistor
Each is Source region and drain region and said source region
Including a channel forming region between the drain region and the drain region
Having a semiconductive semiconductor, Oxygen, nitrogen or carbon is added to the channel forming region.
And oxygen or nitrogen in the channel formation region or
The total amount of carbon is 1 x 10²⁰cm^-3~ 20 atom%, Oxygen, nitrogen, or nitrogen in the source region and the drain region
Or the total amount of carbon is 7 × 10¹⁹cm^-3Is The N-channel insulated gate field effect transistor
Has a mobility of 15 cm²/ Vsec or more, The P-channel type insulated gate field effect transistor
Mobility is 10 cm²/ Vsec or more
Semiconductor device to collect. Wherein said semiconductor device is a semiconductor device according to claim 1, which is a liquid crystal display device. Wherein the semiconductor device includes a semiconductor device according to claim 1, characterized in that the image sensor. Wherein said semiconductor device is a semiconductor device according to claim 1, characterized in that a monolithic integrated circuit.