JPS63100777A - Pattern forming method of transparent electrode - Google Patents

Pattern forming method of transparent electrode

Info

Publication number
JPS63100777A
JPS63100777A JP61246547A JP24654786A JPS63100777A JP S63100777 A JPS63100777 A JP S63100777A JP 61246547 A JP61246547 A JP 61246547A JP 24654786 A JP24654786 A JP 24654786A JP S63100777 A JPS63100777 A JP S63100777A
Authority
JP
Japan
Prior art keywords
film
substrate
transparent electrode
temperature
electrode pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61246547A
Other languages
Japanese (ja)
Inventor
Yasuhiro Nasu
安宏 那須
Satoru Kawai
悟 川井
Kenichi Oki
沖 賢一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61246547A priority Critical patent/JPS63100777A/en
Publication of JPS63100777A publication Critical patent/JPS63100777A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Electric Cables (AREA)

Abstract

PURPOSE:To obtain a transparent electrode pattern, through which breakdown and a defective contact are not generated, by a method wherein a substrate is kept at 200 deg.C or more, the film formation of an InSn oxide is started through an ion plating method, the film of the oxide is formed, while lowering the temperature of the substrate gradually, and a predetermined electrode pattern is shaped through photoetching. CONSTITUTION:An ITO film 2 is formed onto a glass substrate 1 through an ion plating method, while lowering the temperature of the substrate 1 gradually from a temperature of 200 deg.C or more. The ITO film 2 is etched, using a resist pattern 3 as a mask, and the resist pattern 3 is removed. A drain electrode 2-1 and a source electrode 2-2 consisting of the ITO film are shaped, and an a-Si film 4, an SiN film 5 and a gate electrode 6 are formed, thus acquiring a thin-film Tr.

Description

【発明の詳細な説明】 〔概要〕 液晶表示素子を駆動する薄膜トランジスタに用いられる
透明電極のパターン形成法において、電極間の短絡及び
電極の接続不良を防止するために、基板に透明電極とな
るインジウム錫酸化物をイオンプレーティング法にて成
膜する際、当該基板を200℃以上の温度から漸次降下
することにより、テーパーエツジ形状の透明電極パター
ンを形成する。
[Detailed Description of the Invention] [Summary] In a method for forming patterns of transparent electrodes used in thin film transistors that drive liquid crystal display elements, indium, which becomes the transparent electrode, is added to the substrate in order to prevent short circuits between electrodes and poor connections between the electrodes. When forming a tin oxide film by ion plating, the temperature of the substrate is gradually lowered from 200° C. or higher to form a tapered edge-shaped transparent electrode pattern.

〔産業上の利用分野〕[Industrial application field]

この発明は、液晶表示素子を駆動する薄膜トランジスタ
の透明電極のパターン形成法に関するものである。
The present invention relates to a method for forming patterns of transparent electrodes of thin film transistors that drive liquid crystal display elements.

液晶表示素子の薄膜トランジスタは、マトリックス配列
された液晶表示素子を駆動している。従って、薄膜トラ
ンジスタの透明電極は基板上にて多数交叉している。若
しこの交叉点の1箇所でも短絡すると、交叉点を通過す
る配線が線欠陥状態となる。又透明電極と動作半導体と
の接続(コンタクト)が悪いと点欠陥となる。
The thin film transistor of the liquid crystal display element drives the liquid crystal display element arranged in a matrix. Therefore, the transparent electrodes of the thin film transistor intersect in large numbers on the substrate. If even one of these intersection points is short-circuited, the wiring passing through the intersection becomes line defective. In addition, if the connection (contact) between the transparent electrode and the active semiconductor is poor, a point defect occurs.

従って、線欠陥及び点欠陥の発生のない透明電極のパタ
ーン形成法が要望されている。
Therefore, there is a need for a transparent electrode pattern forming method that does not generate line defects or point defects.

〔従来の技術〕[Conventional technology]

第4図は従来の透明電極のパターン形成工程図である。 FIG. 4 is a diagram showing a conventional transparent electrode pattern forming process.

第4図(alの工程では、ガラス基鈑lを例えば、25
0℃に保って、インジウム錫酸化物膜(以1i1TO膜
と記す)20を形成する。
Figure 4 (In the step of al, the glass substrate l is
While maintaining the temperature at 0° C., an indium tin oxide film (hereinafter referred to as 1i1TO film) 20 is formed.

次の第4図(′b)の工程で、ドレインとソース電極を
形成するために、レジストパターン3をITOIl!2
0上に形成する。この後に第4図(C1の工程でITO
膜20をレジストパターン3に基づきエツチングしてド
レイン電極20−1とソース電極20−2を形成し、レ
ジストパターン3を剥離する。
In the next step shown in FIG. 4('b), the resist pattern 3 is ITOIl! to form the drain and source electrodes. 2
Formed on 0. After this, as shown in Figure 4 (in step C1)
The film 20 is etched based on the resist pattern 3 to form a drain electrode 20-1 and a source electrode 20-2, and the resist pattern 3 is peeled off.

次の第4図(dlの工程で、それら電極上にアモルファ
スシリコン(a−3i)よりなる動作半導体層4と、窒
化シリコン(SiN)よりなるゲート絶縁層5と、ゲー
ト電極6とを順次形成する。この際ソース電極20−2
は、表示電極に接続されている。
In the next step of FIG. 4 (dl), an active semiconductor layer 4 made of amorphous silicon (a-3i), a gate insulating layer 5 made of silicon nitride (SiN), and a gate electrode 6 are sequentially formed on these electrodes. At this time, the source electrode 20-2
is connected to the display electrode.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記したように薄膜トランジスタは形成されているが、
ITO膜からなる電極、即ちドレイン電極20−1とソ
ース電極20−2を低抵抗にするために、この膜厚を2
000人程度以上の厚膜にする必要があり、この厚膜の
ために、a−Siffi4形成時にこのa−SiJ’i
jが異常成長をして、ITO膜パターンエツジでの絶縁
破壊、即ちゲート電極6とソース電極2o−2或いはド
レイン電極20−1との短絡及びa−5i層4とITO
膜の接続(コンタクト)不良を発生するという問題があ
った。
Although thin film transistors are formed as described above,
In order to make the electrodes made of ITO film, that is, the drain electrode 20-1 and the source electrode 20-2, have low resistance, the film thickness is set to 2.
It is necessary to make the film as thick as 000 or more, and due to this thick film, this a-SiJ'i
j grows abnormally, resulting in dielectric breakdown at the ITO film pattern edge, that is, a short circuit between the gate electrode 6 and the source electrode 2o-2 or the drain electrode 20-1, and a-5i layer 4 and the ITO layer.
There was a problem in that poor film connection (contact) occurred.

この発明は、上記した従来の状況から絶縁破壊及ヒコン
タクト不良を発生しない透明電極のパターン形成法を提
供することを目的とするものである。
The object of the present invention is to provide a transparent electrode pattern forming method that does not cause dielectric breakdown or poor contact in view of the above-mentioned conventional situation.

〔問題点を解決するための手段〕[Means for solving problems]

基板上にイオンプレーティング法でITOy!を形成す
る際に、基板を200℃以上に保って成膜を開始し成膜
進行とともに、徐々に基板温度をzoo ’c以下にし
て成膜を行う。
ITOy on the substrate using ion plating method! When forming the film, film formation is started while keeping the substrate at 200° C. or higher, and as the film formation progresses, the substrate temperature is gradually lowered to below zoo'c.

〔作用〕[Effect]

ITOの成膜は、漸次温度を降下しながら行われるので
、次の該ITOIIをエツチングにてパターン形成法す
る際にエツチングレートが変化してエツチングされたI
TO[9)パターンのエツジはテーパー形状となり、こ
の結果次のa−Si層形成時にエツジ付近にて異常成長
することがなく、絶縁破壊とコンタクト不良を防止する
ITO film formation is carried out while gradually lowering the temperature, so when the next ITO II pattern is formed by etching, the etching rate changes and the etched ITO II pattern is formed by etching.
The edges of the TO[9] pattern have a tapered shape, and as a result, abnormal growth does not occur near the edges when forming the next a-Si layer, thereby preventing dielectric breakdown and contact failure.

〔実施例〕〔Example〕

第1図は本発明による薄膜トランジスタの透明電極のパ
ターン形成法を示す工程図である。まず第1図(a)の
工程において、ガラス基Fi1を200 ’C以上の温
度から漸次200℃以下の温度状態にしながら、該基板
上にITO膜2をイオンプレーティング法にて形成する
。この成膜に要する時間と基板温度との関係は、第2図
に示すようになる。
FIG. 1 is a process diagram showing a method for forming a pattern of a transparent electrode of a thin film transistor according to the present invention. First, in the step shown in FIG. 1(a), the ITO film 2 is formed on the substrate by the ion plating method while the glass substrate Fi1 is gradually heated from a temperature of 200'C or higher to a temperature of 200C or lower. The relationship between the time required for film formation and the substrate temperature is shown in FIG.

次の第1図(′b)の工程は従来と同じであり、ITO
膜2をレジストパターン3をマスクとしてエツチングし
た後、レジストパターン3を除去するとI↑0模2は第
1図(C1のような断面形状となる。この際にITO膜
の膜厚方向にエツチングレートが変化しており、ITO
膜2のエツジは、表面部が開いたテーパー状にエツチン
グされる。
The following process in Figure 1 ('b) is the same as the conventional process, and the ITO
After etching the film 2 using the resist pattern 3 as a mask, when the resist pattern 3 is removed, I↑0 model 2 has a cross-sectional shape as shown in Figure 1 (C1).At this time, the etching rate is is changing, and ITO
The edges of the film 2 are etched into a tapered shape with an open surface.

これは、第3図に示す基板温度或いはアニール温度とエ
ツチングレートの実験データによる。実線は弗酸系のエ
ツチング液を用いた場合であり、一点鎖線は塩化第2鉄
と塩酸の混合液を用いた場合である。
This is based on the experimental data of substrate temperature or annealing temperature and etching rate shown in FIG. The solid line shows the case where a hydrofluoric acid-based etching solution is used, and the dashed line shows the case where a mixed solution of ferric chloride and hydrochloric acid is used.

本実施例のエツチング液は、塩化第2鉄と塩酸の交合液
を用いて、エツチングを行った。成模後A点にあるエラ
チングレー) 1)00n/分を有するITO膜は、基
板温度を200℃以下に低下させることによって、エツ
チングレートは500n+*/分以上に増加する。この
実験結果に着目し、基板温度を順次低下させている。
The etching solution used in this example was a mixed solution of ferric chloride and hydrochloric acid. Erasing gray at point A after patterning) 1) For an ITO film having an etching rate of 00 n/min, the etching rate increases to 500 n++/min or more by lowering the substrate temperature to 200° C. or less. Taking note of this experimental result, we are gradually lowering the substrate temperature.

即ち、第2図の成膜時間中の最初に形成されたITO膜
はエツチングレートが低いのでサイドエツチングも少な
く、後で形成されたrTO膜は、例えばB点のものとな
りエツチングレートが大きいのでサイドエツチングも大
きい。従って、所望のテーパ形状が得られる。
That is, the ITO film formed first during the film forming time shown in FIG. 2 has a low etching rate, so there is little side etching, and the rTO film formed later is, for example, at point B, and has a high etching rate, so side etching is small. The etching is also large. Therefore, a desired tapered shape can be obtained.

此のITO膜よりなる透明電極すなわちドレイン電12
−1 とソース電極2−2とのパターンを形成した後、
第1図+d)の工程で従来のようにa−5i層4とSi
N層5とゲート電極6を順次形成する。
A transparent electrode, that is, a drain electrode 12 made of this ITO film
After forming a pattern of -1 and source electrode 2-2,
In the process of Fig. 1+d), the a-5i layer 4 and Si
N layer 5 and gate electrode 6 are formed in sequence.

〔効果〕〔effect〕

以上の説明から明らかなように、この発明によれば、テ
ーパー形状を持つパターニングされたITOll1j!
をソースとドレイン電極とすることができ、短絡防止が
図れるとともにコンタクト状態が向上し高品質の1模ト
ランジスタを作製する上で効果を発揮する。
As is clear from the above description, according to the present invention, patterned ITOll1j! having a tapered shape!
can be used as the source and drain electrodes, preventing short circuits and improving the contact condition, which is effective in producing a high-quality one-mock transistor.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による透明電極のパターン形成法を示す
工程図、 第2図は本発明のITO成膜時の基板温度状態図、第3
図はイオンプレーティング法で作製したITO膜のエツ
チングレートと温度の関係図、第4図は従来の透明電極
のパターン形成の工程図である。 図において1はガラス基板、2はITO膜、3はレジス
トパターンを示す。 A(李こ明l二島ΩへB月電不Qnツマターン引ぞへケ
ムEホう工j璽〔D亮 1 図 第2図 イ才>fL−ラ1−゛、五て一イ下;ジレT;1丁Oめ
工・ノナ二)JAめh球第33
Fig. 1 is a process diagram showing the transparent electrode pattern forming method according to the present invention, Fig. 2 is a substrate temperature state diagram during ITO film formation of the present invention, and Fig. 3
The figure is a diagram showing the relationship between the etching rate and temperature of an ITO film produced by the ion plating method, and FIG. 4 is a process diagram of conventional transparent electrode pattern formation. In the figure, 1 is a glass substrate, 2 is an ITO film, and 3 is a resist pattern. A (Li Koming l two islands Ω to B month electric failure Qn Tsuma turn pull to Kem E Hou j 〔D light 1 Fig. 2 I>fL-ra 1-゛, 5-te-1-i bottom; Gilet T; 1-cho Omeko/Nonani) JAmeh ball No. 33

Claims (3)

【特許請求の範囲】[Claims] (1)基板上にインジウム錫酸化物の電極パターンを形
成するに際し、前記基板を200℃以上に保ちイオンプ
レーティング法にて前記インジウム錫酸化物の成膜を開
始し漸次該基板の温度を降下しながら成膜を行い、その
後に前記インジウム錫酸化物膜をフォトエッチングによ
って所定の電極パターンに形成することを特徴とする透
明電極のパターン形成法。
(1) When forming an electrode pattern of indium tin oxide on a substrate, keep the substrate at 200°C or higher and start forming the indium tin oxide film using the ion plating method, and gradually lower the temperature of the substrate. 1. A transparent electrode pattern forming method, characterized in that the indium tin oxide film is formed into a predetermined electrode pattern by photo-etching.
(2)前記電極パターンを形成した基板を200℃以上
で熱処理することを特徴とする特許請求の範囲第1項記
載の透明電極のパターン形成法。
(2) The transparent electrode pattern forming method according to claim 1, wherein the substrate on which the electrode pattern is formed is heat-treated at 200° C. or higher.
(3)前記インジウム錫酸化物の電極が薄膜トランジス
タのソース・ドレイン電極であることを特徴とする特許
請求の範囲第1項及び第2項記載の透明電極のパターン
形成法。
(3) The method for forming a transparent electrode pattern according to claims 1 and 2, wherein the indium tin oxide electrode is a source/drain electrode of a thin film transistor.
JP61246547A 1986-10-16 1986-10-16 Pattern forming method of transparent electrode Pending JPS63100777A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61246547A JPS63100777A (en) 1986-10-16 1986-10-16 Pattern forming method of transparent electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61246547A JPS63100777A (en) 1986-10-16 1986-10-16 Pattern forming method of transparent electrode

Publications (1)

Publication Number Publication Date
JPS63100777A true JPS63100777A (en) 1988-05-02

Family

ID=17150034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61246547A Pending JPS63100777A (en) 1986-10-16 1986-10-16 Pattern forming method of transparent electrode

Country Status (1)

Country Link
JP (1) JPS63100777A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04190330A (en) * 1990-11-26 1992-07-08 Semiconductor Energy Lab Co Ltd Driving method for display device
US5905555A (en) * 1990-11-26 1999-05-18 Semiconductor Energy Laboratory Co., Ltd. Active matrix type electro-optical device having leveling film
US5933205A (en) * 1991-03-26 1999-08-03 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for driving the same
US5956105A (en) * 1991-06-14 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6013928A (en) * 1991-08-23 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interlayer insulating film and method for forming the same
US6242758B1 (en) 1994-12-27 2001-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device employing resinous material, method of fabricating the same and electrooptical device
US6778231B1 (en) 1991-06-14 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical display device
US6975296B1 (en) 1991-06-14 2005-12-13 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US7154147B1 (en) 1990-11-26 2006-12-26 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04190330A (en) * 1990-11-26 1992-07-08 Semiconductor Energy Lab Co Ltd Driving method for display device
US5905555A (en) * 1990-11-26 1999-05-18 Semiconductor Energy Laboratory Co., Ltd. Active matrix type electro-optical device having leveling film
US7154147B1 (en) 1990-11-26 2006-12-26 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US5933205A (en) * 1991-03-26 1999-08-03 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for driving the same
US5963278A (en) * 1991-03-26 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for driving the same
US5956105A (en) * 1991-06-14 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6778231B1 (en) 1991-06-14 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical display device
US6975296B1 (en) 1991-06-14 2005-12-13 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6013928A (en) * 1991-08-23 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interlayer insulating film and method for forming the same
US6242758B1 (en) 1994-12-27 2001-06-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device employing resinous material, method of fabricating the same and electrooptical device
US6429053B1 (en) 1994-12-27 2002-08-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device method of fabricating same, and, electrooptical device

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