CN107247376B - Manufacturing method of TFT substrate and manufacturing method of liquid crystal display device - Google Patents
Manufacturing method of TFT substrate and manufacturing method of liquid crystal display device Download PDFInfo
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- CN107247376B CN107247376B CN201710496731.3A CN201710496731A CN107247376B CN 107247376 B CN107247376 B CN 107247376B CN 201710496731 A CN201710496731 A CN 201710496731A CN 107247376 B CN107247376 B CN 107247376B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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Abstract
The invention provides a manufacturing method of a TFT substrate and a manufacturing method of a liquid crystal display device. The manufacturing method of the TFT substrate comprises the steps of patterning a light resistance layer on a passivation layer by using a halftone photomask to form a first light resistance area and a second light resistance area which are mutually spaced, carrying out dry etching on the passivation layer and a grid insulation layer to form a groove on the grid insulation layer, carrying out ashing treatment on the first light resistance area and the second light resistance area to reserve a part of the first light resistance area and a part of the second light resistance area, wherein the part of the second light resistance area comprises a first subregion and a second subregion which are mutually spaced, continuing carrying out dry etching on the passivation layer and the grid insulation layer to form a first via hole and a second via hole which respectively expose a first metal layer and a second metal layer, effectively preventing the second metal layer from being prematurely exposed in the dry etching process and being bombarded by plasma to form a metal compound on the surface of the second metal layer, and improving the connection effect of the second metal layer and, the quality of the product is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of a TFT substrate and a manufacturing method of a liquid crystal display device.
Background
A Liquid Crystal Display (LCD) is one of the most widely used flat panel displays, and the LCD panel is a core component of the LCD. The Liquid Crystal panel is generally composed of a Color Filter Substrate (CF Substrate), a Thin film transistor Array Substrate (TFT Array Substrate), and a Liquid Crystal Layer (Liquid Crystal Layer) disposed between the two substrates. Generally, the array substrate and the color filter substrate are respectively provided with a pixel electrode and a common electrode. When voltages are applied to the pixel electrodes and the common electrode, an electric field is generated in the liquid crystal layer, which determines the orientation of liquid crystal molecules, thereby adjusting the polarization of light incident to the liquid crystal layer, and displaying images on the liquid crystal panel.
Among flat panel displays, liquid crystal display devices have gradually taken a leading position in the display field due to their low power consumption, excellent picture quality, and high production yield. In the prior art, in the process of manufacturing a TFT substrate of a liquid crystal display device, a plurality of metal layers are required to be disposed to form a data line, a gate line, and a gate electrode, a source electrode, and a drain electrode of a TFT device in the TFT substrate, and in order to connect the metal layers to an external circuit, a via hole is often required to be formed on an insulating layer above the metal layers to expose a portion of the metal layers for the external circuit to be connected thereto.
Specifically, referring to fig. 1 and 2, when a conventional TFT substrate is manufactured, first, a first metal layer 200 ', a gate insulating layer 300' covering the first metal layer 200 ', a second metal layer 400' on the gate insulating layer 300 ', and a passivation layer 500' covering the second metal layer 400 'are sequentially manufactured on a substrate 100', a photoresist layer 600 'is coated on the passivation layer 500', and the photoresist layer 600 'is patterned by using a mask (mask) to form a first photoresist region 610', a second photoresist region 620 ', and a third photoresist region 630' which are spaced apart from each other; then, the passivation layer 500 'and the gate insulating layer 300' are dry etched by an etching process to remove the passivation layer 500 'and the gate insulating layer 300' that are not covered by the first, second, and third photoresist regions 610 ', 620', and 630 ', thereby forming a first via 510' and a second via 520 ', the first via 510' penetrating through the passivation layer 500 'and the gate insulating layer 300' to expose the first metal layer 200 ', and the second via 520' penetrating through the passivation layer 500 'to expose the second metal layer 400'. Since the first via hole 510 ' and the second via hole 520 ' are formed by the same etching process, after the second via hole 520 ' exposing the second metal layer 400 ' is formed, the etching process is not stopped, but the passivation layer 500 ' and the gate insulating layer 300 ' are continuously etched until the first via hole 510 ' exposing the first metal layer 200 ' is formed, in this process, the exposed portion of the second metal layer 400 ' is bombarded by plasma (plasma) in the etching process to form a metal compound on the surface thereof (for example, the second metal layer 400 ' is made of copper, and a copper compound is formed after the second metal layer 400 ' is bombarded by the plasma), so that the second metal layer 400 ' is damaged (damage), and the connection effect between the second metal layer 400 ' and an external circuit is affected.
Disclosure of Invention
The invention aims to provide a manufacturing method of a TFT substrate, which can avoid the formation of a metal compound due to the early exposure of a second metal layer in the process of forming via holes on a first metal layer and the second metal layer, and improve the connection effect of the second metal layer and an external circuit.
Another objective of the present invention is to provide a method for fabricating a liquid crystal display device, which can prevent a second metal layer from being exposed too early to form a metal compound during a process of forming via holes on a first metal layer and the second metal layer, thereby improving a connection effect between the second metal layer and an external circuit.
In order to achieve the above object, the present invention first provides a method for manufacturing a TFT substrate, comprising the steps of:
step S1, providing a substrate, and sequentially forming a first metal layer, a gate insulating layer covering the first metal layer, a second metal layer on the gate insulating layer, and a passivation layer covering the second metal layer on the substrate;
step S2, forming a photoresist layer on the passivation layer, and patterning the photoresist layer by using a halftone mask to form a first photoresist region and a second photoresist region which are spaced from each other;
step S3, dry etching the passivation layer and the gate insulating layer through an etching process, removing the passivation layer and part of the gate insulating layer which are not covered by the first photoresist region and the second photoresist region, and forming a groove on the gate insulating layer, wherein the bottom surface of the groove is positioned in the gate insulating layer;
step S4, performing ashing treatment on the first photoresist region and the second photoresist region, and reserving a part of the first photoresist region and a part of the second photoresist region, wherein the part of the second photoresist region comprises a first sub-region and a second sub-region which are mutually spaced;
step S5, dry-etching the passivation layer and the gate insulating layer through an etching process, and removing the passivation layer and the gate insulating layer which are not covered by the portion of the first photoresist region and the portion of the second photoresist region to form a first via hole and a second via hole, wherein the first via hole penetrates through the passivation layer and the gate insulating layer to expose the first metal layer, and the second via hole penetrates through the passivation layer to expose the second metal layer.
The second light resistance area comprises a middle part and side parts positioned on two sides of the middle part, the thickness of the middle part is smaller than that of the side parts, and the thickness of the first light resistance area is equal to that of the side parts;
the ashing process in step S4 includes: removing the middle part of the second photoresist region and reducing the thickness of the two side parts to form a first sub-region and a second sub-region; the thickness of the first photoresist region is reduced to form a portion of the first photoresist region.
The method for manufacturing the TFT substrate further includes step S6, removing a portion of the first photoresist region and a portion of the second photoresist region.
The distance between the bottom surface of the groove and the upper surface of the first metal layer satisfies the following conditions:
D＝H×S；
wherein D is the distance between the bottom surface of the groove and the upper surface of the first metal layer, H is the thickness of the passivation layer above the second metal layer, and S is the ratio of the etching rate of the gate insulating layer to the etching rate of the passivation layer.
The first metal layer is made of one or more of molybdenum, titanium, aluminum, silver and copper.
The second metal layer is made of one or more of molybdenum, titanium, aluminum, silver and copper.
The second metal layer is made of copper.
The substrate base plate material is glass or a flexible material.
The material of the gate insulating layer and the passivation layer comprises at least one of silicon oxide and silicon nitride.
The invention also provides a manufacturing method of the liquid crystal display device, and the TFT substrate is manufactured by adopting the manufacturing method of the TFT substrate.
The invention has the beneficial effects that: the invention provides a method for manufacturing a TFT substrate, which comprises the steps of patterning a photoresist layer on a passivation layer by using a halftone photomask to form a first photoresist region and a second photoresist region which are mutually spaced, carrying out dry etching on the passivation layer and a grid insulation layer to form a groove on the grid insulation layer, carrying out ashing treatment on the first photoresist region and the second photoresist region to reserve part of the first photoresist region and part of the second photoresist region, wherein the part of the second photoresist region comprises a first subregion and a second subregion which are mutually spaced, continuously carrying out dry etching on the passivation layer and the grid insulation layer to form a first via hole and a second via hole which respectively expose a first metal layer and a second metal layer, and compared with the prior art, the method can effectively avoid the second metal layer from being prematurely exposed in the dry etching process and being bombarded by plasma to form metal compounds on the surface of the second metal layer, the connection effect of the second metal layer and an external circuit is improved, and the quality of the product is improved. The manufacturing method of the liquid crystal display device can avoid the formation of metal compounds due to the early exposure of the second metal layer in the process of forming the through holes on the first metal layer and the second metal layer, and improve the connection effect of the second metal layer and an external circuit.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
fig. 1 and 2 are schematic diagrams illustrating a conventional method for manufacturing a TFT substrate;
FIG. 3 is a flow chart of a method of fabricating a TFT substrate according to the present invention;
FIG. 4 is a schematic diagram of steps S1 and S2 of the method for fabricating a TFT substrate according to the present invention;
FIG. 5 is a schematic view of step S3 of the method for fabricating a TFT substrate according to the present invention;
FIG. 6 is a schematic view of step S4 of the method for fabricating a TFT substrate according to the present invention;
fig. 7 is a schematic diagram of step S5 of the method for manufacturing a TFT substrate according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 3, the present invention provides a method for manufacturing a TFT substrate, including the following steps:
step S1, please refer to fig. 4, providing a substrate 100, and sequentially forming a first metal layer 200, a gate insulating layer 300 covering the first metal layer 200, a second metal layer 400 on the gate insulating layer 300, and a passivation layer 500 covering the second metal layer 400 on the substrate 100.
Specifically, the substrate 100 may be made of glass, and correspondingly, the TFT substrate is applied to a rigid liquid crystal display device; alternatively, the substrate 100 may be made of a flexible material, such as Polyimide (PI), and the TFT substrate may be applied to a flexible display device.
Specifically, the material of the first metal layer 200 is one or more of molybdenum, titanium, aluminum, silver, and copper. Specifically, the first metal layer 200 includes, but is not limited to, a gate electrode, a gate line, and the like.
Specifically, the material of the gate insulating layer 300 includes silicon oxide (SiNx) and silicon nitride (SiO)2) At least one of (1).
Specifically, the material of the second metal layer 400 may also be a combination of one or more of molybdenum, titanium, aluminum, silver, and copper. In order to reduce the impedance of the traces, the material of the second metal layer 400 is preferably copper. Specifically, the second metal layer 400 includes, but is not limited to, a source, a drain, a data line, and the like.
Specifically, the material of the passivation layer 500 includes at least one of silicon oxide and silicon nitride.
In step S2, referring to fig. 4, a photoresist layer 600 is formed on the passivation layer 500, and the photoresist layer 600 is patterned by using a Half-tone (Half-tone) mask to form a first photoresist region 610 and a second photoresist region 620 spaced apart from each other.
Specifically, the second photoresist region 620 includes a middle portion 621 and side portions 622 located on both sides of the middle portion 621, the thickness of the middle portion 621 is smaller than that of the side portions 622, and the thickness of the first photoresist region 610 is equal to that of the side portions 622.
Specifically, the photoresist 600 is made of a positive photoresist or a negative photoresist. Further, when the material of the photoresist layer 600 is a positive photoresist, the halftone mask has opaque regions corresponding to two side portions 622 of the first photoresist region 610 and the second photoresist region 620, a semi-opaque region corresponding to a middle portion 621 of the second photoresist region 620, and a fully-opaque region corresponding to a region between the first photoresist region 610 and the second photoresist region 620; when the photoresist layer 600 is made of a negative photoresist, the halftone mask has a completely transparent region corresponding to two side portions 622 of the first photoresist region 610 and the second photoresist region 620, a semi-transparent region corresponding to the middle portion 621 of the second photoresist region 620, and an opaque region corresponding to a region between the first photoresist region 610 and the second photoresist region 620.
Step S3, referring to fig. 5, dry-etching the passivation layer 500 and the gate insulating layer 300 by an etching process to remove the passivation layer 500 and a portion of the gate insulating layer 300 not covered by the first photoresist region 610 and the second photoresist region 620, and form a groove 310 on the gate insulating layer 300; by controlling the dry etching process parameters, the bottom surface of the recess 310 is located in the gate insulating layer 300, that is, in the step S3, the first metal layer 200 is not exposed, and a certain thickness of the gate insulating layer 300 remains above the recess.
In step S4, please refer to fig. 6, the first photoresist region 610 and the second photoresist region 620 are ashed to leave a portion of the first photoresist region 630 and a portion of the second photoresist region 640, where the portion of the second photoresist region 640 includes a first sub-region 641 and a second sub-region 642 which are spaced apart from each other.
Specifically, the ashing process in step S4 includes: removing the middle portion 621 of the second photoresist region 620 and reducing the thickness of the two side portions 622 to form a first sub-region 641 and a second sub-region 642; the thickness of the first photoresist region 610 is reduced to form a portion of the first photoresist region 630.
In step S5, referring to fig. 7, the passivation layer 500 and the gate insulating layer 300 are dry etched by an etching process to remove the passivation layer 500 and the gate insulating layer 300 that are not covered by the portion of the first photoresist region 630 and the portion of the second photoresist region 640, so as to form a first via 510 and a second via 520, where the first via 510 penetrates through the passivation layer 500 and the gate insulating layer 300 to expose the first metal layer 200, and the second via 520 penetrates through the passivation layer 500 to expose the second metal layer 400.
It should be noted that, in the present invention, a half-tone mask is used to pattern the photoresist layer 600 to form a first photoresist region 610 and a second photoresist region 620 which are spaced from each other, after dry etching is performed on the passivation layer 500 and the gate insulating layer 300 through an etching process, a groove 310 is formed on the gate insulating layer 300 corresponding to an area not covered by the first photoresist region 610 and the second photoresist region 620, then ashing is performed on the first photoresist region 610 and the second photoresist region 620 to leave a portion of the first photoresist region 630 and a portion of the second photoresist region 640, a first sub-area 641 and a second sub-area 642 of the portion of the second photoresist region 640 which are spaced from each other expose the passivation layer 500 on the second metal layer 400, and then dry etching is performed on the passivation layer 500 and the gate insulating layer 300 through an etching process, during which the remaining portion of the gate insulating layer 300 corresponding to the groove 310 is etched away, and the passivation layer 500 on the second metal layer 400 is etched away, thereby forming the first via hole 510 and the second via hole 520 exposing the first metal layer 200 and the second metal layer 400, respectively, compared with the prior art in which the via holes exposing the second metal layer are formed and then the dry etching is continued for a period of time to form the via holes exposing the first metal layer, the present invention can shorten the exposure time of the second metal layer 400 in the dry etching process, effectively prevent the second metal layer 400 from being exposed too early in the dry etching process and being bombarded by plasma to form metal compounds on the surface thereof, improve the connection effect of the second metal layer 400 and external circuits, and improve the quality of products.
Further, in the step S3, the distance between the bottom surface of the groove 310 and the upper surface of the first metal layer 200, that is, the thickness of the gate insulating layer 300 remaining above the first metal layer 200, is made to satisfy:
D＝H×S；
wherein D is the distance between the bottom of the groove 310 and the upper surface of the first metal layer 200, H is the thickness of the passivation layer 500 above the second metal layer 400, and S is the ratio of the etching rate of the gate insulating layer 300 to the etching rate of the passivation layer 500, i.e., the etching selection ratio of the gate insulating layer 300 to the passivation layer 500, so that when the gate insulating layer 300 and the passivation layer 500 are dry etched by the etching process in step S5, the gate insulating layer 300 remaining above the first metal layer 200 and the passivation layer 500 above the second metal layer 400 can be etched away at the same time, the first metal layer 200 and the second metal layer 400 are exposed at the same time, i.e., the first via hole 510 and the second via hole 520 are fabricated at the same time, further, the second metal layer is prevented from being exposed too early during the dry etching process and being bombarded on the surface thereof by plasma, thereby improving the connection effect of the second metal layer and, the quality of the product is improved.
Specifically, the method for manufacturing the TFT substrate further includes step S6, removing the portion of the first photoresist region 630 and the portion of the second photoresist region 640.
Based on the same inventive concept, the invention also provides a manufacturing method of the liquid crystal display device, the TFT substrate is manufactured by adopting the manufacturing method of the TFT substrate, the formation of metal compounds caused by the premature exposure of the second metal layer in the process of forming the via holes on the first metal layer and the second metal layer can be avoided, and the connection effect of the second metal layer and an external circuit is improved. The method for fabricating the TFT substrate will not be described repeatedly.
In summary, the method for fabricating a TFT substrate of the present invention utilizes a halftone mask to pattern a photoresist layer on a passivation layer to form a first photoresist region and a second photoresist region spaced apart from each other, and dry etches the passivation layer and a gate insulating layer to form a trench on the gate insulating layer, and then performs an ashing process on the first photoresist region and the second photoresist region to retain a portion of the first photoresist region and a portion of the second photoresist region, where the portion of the second photoresist region includes the first sub-region and the second sub-region spaced apart from each other, and continues to dry etch the passivation layer and the gate insulating layer to form a first via hole and a second via hole respectively exposing a first metal layer and a second metal layer, compared with the prior art, the method can effectively prevent the second metal layer from being exposed too early during the dry etching process and being bombarded by plasma to form metal compounds on the surface thereof, the connection effect of the second metal layer and an external circuit is improved, and the quality of the product is improved. The manufacturing method of the liquid crystal display device can avoid the formation of metal compounds due to the premature exposure of the second metal layer in the process of forming the through holes on the first metal layer and the second metal layer, and improve the connection effect of the second metal layer and an external circuit.
As described above, it will be apparent to those skilled in the art that various other changes and modifications can be made based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.
Claims (10)
1. A manufacturing method of a TFT substrate comprises the following steps:
step S1, providing a substrate (100), and sequentially forming a first metal layer (200), a gate insulating layer (300) covering the first metal layer (200), a second metal layer (400) on the gate insulating layer (300), and a passivation layer (500) covering the second metal layer (400) on the substrate (100);
step S2, forming a photoresist layer (600) on the passivation layer (500), and patterning the photoresist layer (600) by using a halftone mask to form a first photoresist region (610) and a second photoresist region (620) which are spaced from each other;
it is characterized by also comprising the following steps:
step S3, dry-etching the passivation layer (500) and the gate insulating layer (300) by an etching process, removing the passivation layer (500) and a portion of the gate insulating layer (300) not covered by the first photoresist region (610) and the second photoresist region (620), and forming a groove (310) on the gate insulating layer (300), wherein a bottom surface of the groove (310) is located in the gate insulating layer (300);
step S4, performing ashing treatment on the first photoresist region (610) and the second photoresist region (620) to reserve a part of the first photoresist region (630) and a part of the second photoresist region (640), wherein the part of the second photoresist region (640) comprises a first sub-region (641) and a second sub-region (642) which are spaced from each other;
step S5, dry-etching the passivation layer (500) and the gate insulating layer (300) by an etching process, removing the passivation layer (500) and the gate insulating layer (300) not covered by the portions of the first photoresist region (630) and the second photoresist region (640), and forming a first via hole (510) and a second via hole (520), wherein the first via hole (510) penetrates through the passivation layer (500) and the gate insulating layer (300) to expose the first metal layer (200), and the second via hole (520) penetrates through the passivation layer (500) to expose the second metal layer (400).
2. The method of fabricating the TFT substrate according to claim 1, wherein the second photoresist region (620) includes a middle portion (621) and side portions (622) located at both sides of the middle portion (621), the thickness of the middle portion (621) is smaller than the thickness of the side portions (622), and the thickness of the first photoresist region (610) is equal to the thickness of the side portions (622);
the ashing process in step S4 includes: removing the middle part (621) of the second photoresist region (620) and reducing the thickness of the two side parts (622) to form a first sub-region (641) and a second sub-region (642); the thickness of the first photoresist region 610 is reduced to form a portion of the first photoresist region 630.
3. The method of fabricating the TFT substrate according to claim 1 or 2, further comprising step S6 of removing the portions of the first photoresist region (630) and the second photoresist region (640).
4. The method of claim 3, wherein a distance between a bottom surface of the recess (310) and an upper surface of the first metal layer (200) satisfies:
D＝H×S；
wherein D is a distance between the bottom surface of the groove (310) and the upper surface of the first metal layer (200), H is a thickness of the passivation layer (500) above the second metal layer (400), and S is a ratio of an etching rate of the gate insulating layer (300) to an etching rate of the passivation layer (500).
5. The method of fabricating a TFT substrate as claimed in claim 1, wherein the first metal layer (200) is made of one or more of mo, ti, al, ag, and cu.
6. The method of fabricating a TFT substrate according to claim 1 or 4, wherein the second metal layer (400) is made of a material selected from one or more of molybdenum, titanium, aluminum, silver, and copper.
7. The method of fabricating a TFT substrate as claimed in claim 6, wherein the second metal layer (400) is made of copper.
8. The method of fabricating the TFT substrate of claim 1, wherein the substrate (100) material is glass or a flexible material.
9. The method of claim 1, wherein the gate insulating layer (300) and the passivation layer (500) comprise at least one of silicon oxide and silicon nitride.
10. A method of manufacturing a liquid crystal display device, characterized in that the TFT substrate is manufactured by the method of manufacturing a TFT substrate according to any one of claims 1 to 9.
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| CN111725135B (en) * | 2020-06-30 | 2023-08-29 | 昆山龙腾光电股份有限公司 | Manufacturing method of array substrate and array substrate |
| CN111897168A (en) * | 2020-08-21 | 2020-11-06 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0212838A (en) * | 1988-06-29 | 1990-01-17 | Nec Corp | Manufacture of semiconductor device |
| CN1383214A (en) * | 2001-04-26 | 2002-12-04 | 三星电子株式会社 | Polysilicon film transistor of liquid crystal display device and its mfg. method |
| CN101510529A (en) * | 2009-02-17 | 2009-08-19 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| CN102651316A (en) * | 2011-05-09 | 2012-08-29 | 京东方科技集团股份有限公司 | Through hole etching method, array base plate, liquid crystal panel and display equipment |
| CN106229294A (en) * | 2016-08-31 | 2016-12-14 | 深圳市华星光电技术有限公司 | A kind of manufacture method of TFT substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468231B (en) * | 2010-11-10 | 2014-03-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, and active display |
-
2017
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0212838A (en) * | 1988-06-29 | 1990-01-17 | Nec Corp | Manufacture of semiconductor device |
| CN1383214A (en) * | 2001-04-26 | 2002-12-04 | 三星电子株式会社 | Polysilicon film transistor of liquid crystal display device and its mfg. method |
| CN101510529A (en) * | 2009-02-17 | 2009-08-19 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| CN102651316A (en) * | 2011-05-09 | 2012-08-29 | 京东方科技集团股份有限公司 | Through hole etching method, array base plate, liquid crystal panel and display equipment |
| CN106229294A (en) * | 2016-08-31 | 2016-12-14 | 深圳市华星光电技术有限公司 | A kind of manufacture method of TFT substrate |
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