JP2001337619A - Method for manufacturing array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize lowering the cost of an array substrate by reducing its manufacturing processes, manufacturing time and number of components, and, eventually, provide a liquid crystal display unit of high density, high capacity, high fineness and high brightness with a low price. SOLUTION: A semiconductor film 39a, a low resistance semiconductor film 40, a source electrode 48, a drain electrode 49 and a signal line are formed collectively (not shown in a figure), onto which a picture element electrode 35 consisting of ITO films is formed after removing the first gate insulated film 28, the second gate insulated film 29, a semiconductor coating 41 and a low resistance semiconductor coating 44, and forming contact holes 45 and 46, by patterning a laminating film 47. Further, a top layer film 30b of a scanning pad electrode and a top layer film 34b of a signal line pad electrode are formed with hard ITO films, and using these ITO films as a mask pattern, oxidization protection films 50 and 51 on the surface of the source electrode 48 and the drain electrode 49.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an array substrate used for a flat display device represented by a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, as electronic devices have been reduced in size, weight and power consumption, in the field of displays, liquid crystal display devices using an array substrate having semiconductor thin film transistors as switching elements have been receiving attention. .

Conventionally, as shown in FIG. 4, over a gate electrode 2 connected to a scanning line on a glass substrate 1, a semiconductor layer 5 via a gate insulating film 4, furthermore, a semiconductor layer 5 and an etching thereover. Low resistance semiconductor layer 7 covering a part of stopper 6, source electrode 10 connecting low resistance semiconductor layer 7 and pixel electrode 8, low resistance semiconductor layer 7 and signal line (not shown)
And an array substrate 16 using a thin film transistor (hereinafter abbreviated as TFT) 15 having a protective layer 13 as a switching element, requires a manufacturing process shown in FIG. 5 and FIG. Was.

That is, as shown in FIG. 5A, a TFT region and a scanning line pad region of an array substrate are first formed on a glass substrate 1 by using a mask pattern (not shown).
Then, the scanning line 3 including the scanning line pad region at the end and electrically connected to the gate electrode 2 is patterned. Next, FIG.
As shown in (b), after forming a gate insulating film 4, a semiconductor layer 5 made of amorphous silicon (hereinafter abbreviated as a-Si) or the like is formed, and then an insulating film is formed and then a mask is formed. The etching stopper 6 is formed by patterning the insulating film using a pattern (not shown).

Next, as shown in FIG. 5C, after forming a low-resistance semiconductor layer 7 such as low-resistance amorphous silicon (hereinafter abbreviated as n ⁺ a-Si: H), a mask pattern is formed. The semiconductor layer 5 and the low-resistance semiconductor layer 7 are patterned in an island shape (not shown). Next, as shown in FIG. 5D, a transparent conductive film such as indium tin oxide (hereinafter abbreviated as ITO) is formed and then patterned using a mask pattern (not shown) to form the pixel electrode 8. Form. Next, FIG.
As shown in FIG. 1A, a contact hole 9 is formed in a gate insulating film 4 on a pad region of a scanning line 3 using a mask pattern (not shown). Next, as shown in FIG. 6B, after a metal film made of aluminum (Al) or the like is formed, a source electrode 10, a drain electrode 11, and a pad electrode 12 are formed using a mask pattern (not shown). Next, as shown in FIG. 6C, after forming an insulating film, a protective film 13 is formed in a region other than the pixel electrode 8 and the pad region by using a mask pattern (not shown), and an array substrate 16 is formed.
To complete.

[0006]

However, in the above-mentioned conventional array substrate manufacturing process, patterning for performing exposure and development using a photoresist is required at least seven times, and the material cost for the patterning process is high. ,
In addition, there is a problem that the manufacturing time becomes longer and the manufacturing cost becomes higher.

Accordingly, the present invention has been made to solve the above-mentioned problems, and it is intended to reduce the number of patterning steps required for manufacturing an array substrate, thereby reducing the number of manufacturing steps, thereby improving productivity, and thereby reducing the manufacturing cost. It is an object of the present invention to provide a method of manufacturing an array substrate that can realize a low-cost apparatus.

[0008]

According to the present invention, as a means for solving the above-mentioned problems, a scanning line which is arranged on an insulating substrate and includes a gate electrode and a connection terminal, and a gate electrode and a connection terminal are provided via an insulating film. A semiconductor film to be disposed, a source electrode electrically connected to the semiconductor film, a signal line including a drain electrode and a connection terminal electrically connected to the semiconductor film, and a signal line disposed on the source electrode In a method for manufacturing an array substrate including a pixel electrode and a protective layer disposed on a connection terminal of the signal line, a step of patterning a conductive film to form the pixel electrode and the protective film; and And modifying at least the surface of the source and drain electrodes exposed from the pixel electrode as a mask.

With this configuration, the present invention aims to improve the productivity by reducing the number of manufacturing steps when manufacturing an array substrate, and to reduce the manufacturing cost to lower the price of the apparatus. is there.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a liquid crystal display device using a method of manufacturing an array substrate according to the present invention will be described below with reference to FIGS. FIG. 1 shows a liquid crystal display device 20.
FIG. 2 is a partial schematic cross-sectional view of FIG. 1. An array substrate 21 and an opposing substrate 22 are opposed to each other while maintaining a constant gap by a spacer (not shown), and a liquid crystal layer 23 is disposed in the formed gap via an alignment film 24. It is enclosed.

A TFT 200 is provided as a switching element near an intersection of a plurality of scanning lines (not shown) and signal lines (not shown) formed on the glass substrate 100 of the array substrate 21 which cross each other. Pixel electrodes 35 made of a transparent conductive film such as ITO are arranged in a matrix in a region surrounded by scanning lines and signal lines (not shown).

The TFT 200 has a scanning line (not shown) made of, for example, a molybdenum-tungsten (MoW) alloy and having a thickness of about 250 nm on a glass substrate 100 and a gate electrode 26 integral with the scanning line. Is a silicon oxide film (SiO ₂ ) having a thickness of about 300 nm.
A semiconductor film 39 of amorphous silicon (a-Si: H) of about 50 nm is formed via a first gate insulating film 28 and a second gate insulating film 29 of about 50 nm thick silicon nitride film (SiN _x ). .

On the semiconductor film 39, a channel protective film 43 made of a silicon nitride film (SiN _x ) having a thickness of about 200 nm,
A semiconductor film 3 made of about 30 nm thick n ⁺ type amorphous silicon (n ⁺ a-Si: H) containing phosphorus as an impurity;
9 and a low-resistance semiconductor film 40 covering a part of the channel protective film 42.
A molybdenum (Mo) layer having a thickness of 5 nm, an aluminum (Al) layer having a thickness of about 350 nm, and a molybdenum (Mo) layer having a thickness of about 300 nm are stacked, and a source electrode 48 and a signal line (see FIG. (Not shown) are provided.
50 and 51 are the source electrode 48 and the drain electrode 4
9 is an oxidation protective film having a thickness of about 150 nm which covers exposed regions of the source electrode 48 and the drain electrode 49 so as to prevent the surface from being oxidized. An alignment film 24 is formed on these.

On the other hand, in the counter substrate 22, a light shielding film 36 made of, for example, chromium (Cr) is formed on the glass substrate 101.
In addition, a color filter 37 composed of red (R), green (G), and blue (B) coloring layers is formed, and a counter electrode 38 made of ITO is formed on the entire surface thereof, and the alignment film 24 is formed thereon. Is formed. Reference numeral 25 denotes a polarizing plate.

Next, a manufacturing process of the array substrate 21 will be described with reference to FIGS. As shown in FIG. 2A, for example, a molybdenum-tungsten (MoW) alloy is formed on a glass substrate 100 to a thickness of about 250 nm by sputtering or the like.
After forming, applying and drying a resist thereon, exposure and development are performed using the first mask pattern 71, which is a gate electrode 26 integrated with a scanning line (not shown) and an electrode terminal portion of the scanning line. A scanning line pad 61 and a signal line pad 62 which is an electrode terminal of a signal line are formed.

Next, as shown in FIG. 2B, a first gate insulating film 28 made of a silicon oxide film (SiO ₂ ) having a thickness of about 300 nm,
A second gate insulating film 29 made of an m-thick silicon nitride film (SiN _x ) and an amorphous silicon (a-
Si: H) semiconductor coating 41 and about 200 n
A channel protective film 42 made of an m-thick silicon nitride film (SiN _x ) is continuously formed without being exposed to the air.

Next, as shown in FIG. 2C, after a resist is applied on the channel protective film 42 and dried, the glass substrate 1 is masked using a scanning line (not shown) and the gate electrode 26 as a mask.
In addition, exposure is performed from the back surface, and exposure and development are performed using a second mask pattern (not shown) to pattern the channel protection film 42 to form an island-shaped pattern of the channel protection film 43 along the gate electrode 26. Form.

Next, as shown in FIG. 2D, the exposed surface of the semiconductor film 41 is treated with hydrofluoric acid (HF) so as to obtain a good ohmic contact, and is subjected to a low pressure plasma CVD method. About 30 nm thick n ⁺ -type amorphous silicon (n ⁺ a-S) containing phosphorus (P) as an impurity
i: H), a low-resistance semiconductor film 44 is deposited.

Next, as shown in FIG. 3A, after applying and drying a resist on the low-resistance semiconductor film 44, exposure and development are performed using a third master pattern 73, and the scanning line pads 61 and First of the region corresponding to the signal line pad 62
And the second gate insulating films 28 and 29 and the semiconductor film 41
And the low resistance semiconductor film 44 are removed to form contact holes 45 and 46. At this time, the semiconductor film 41
And CDE to remove the low resistance semiconductor film 44.
(Chemical Dry Etching) or P
After performing dry etching such as E (Presma Etching), the first and second gate insulating films 28 and 29 are formed.
Is removed by wet etching such as BHF (buffered hydrofluoric acid). As described above, by using both dry etching and wet etching, the contact holes 45 and 46 are formed in a favorable tapered shape.

Next, as shown in FIG.
A laminated film 47 including a m-thick molybdenum (Mo) layer, an aluminum (Al) layer having a thickness of about 350 nm, and a molybdenum (Mo) layer having a thickness of about 300 nm is formed by a sputtering method.

Next, as shown in FIG. 3C, Mo / A
A resist is applied and dried on the l / Mo laminated film 47, and the fourth
Exposure and development are performed using the mask pattern 74 of phosphoric acid (PO ₃ ), nitric acid (NO ₃ ), acetic acid (CH ₃ CO ₃ ).
O) and a mixed acid of water and Mo / Al / Mo laminated film 4
7 is etched. Further, a silicon nitride film (Si
By controlling the etching selectivity between the second gate insulating film 29 made of N _x ) and the channel protective film 43, the low-resistance semiconductor film 44 and the semiconductor film 41 are collectively patterned by the plasma etching method. This gives T
A semiconductor film 39 forming an active layer of the FT 200; a low-resistance semiconductor film 40 for obtaining a good ohmic contact;
The source electrode 48, the signal line (not shown), the drain electrode 49 formed integrally with the signal line, the scanning line pad electrode 30a, and the signal line pad electrode 34a are collectively formed.

Next, as shown in FIG. 3D, an argon gas (Ar) atmosphere to which water (H ₂ O), hydrogen gas (H ₂ ) or oxygen gas (O ₂ ) is added on the upper surface of the glass substrate 100. Among them, for example, argon gas (A) added with water (H ₂ O)
r) An amorphous ITO film having a thickness of about 40 nm is deposited by sputtering in an atmosphere, and is exposed and developed using the fifth mask pattern 75. As an etchant for the ITO film, a solution that does not etch aluminum (Al), for example, an oxalic acid aqueous solution is used. Thereby, the pixel electrode 35 made of ITO and the scanning line pad electrode uppermost layer film 30 are formed.
b and the signal line pad electrode uppermost layer film 34b are formed.

Next, as shown in FIG.
35, scanning line pad electrode uppermost layer film 30b and signal line pad
Phosphoric acid using the upper electrode layer 34b as a mask pattern.
(PO ₃), Nitric acid (NO₃), Acetic acid (CH₃COO) Oh
Source and drain electrodes 4 and 4 using a mixed acid of water and water.
9 was selected as the upper layer of molybdenum (Mo)
After selective etching, pure water was heated to 80 ° C.
Immerse the array substrate 21 in water for about 3 minutes and treat with warm pure water.
The source electrode 48 and the drain electrode 49
Oxide protective films 50 and 51 about 150 nm thick are formed on the surface of
Thus, the array substrate 21 is completed.

Thereafter, an alignment film 24 made of polyimide and having a thickness of about 50 nm after drying is applied to the array substrate 21 and subjected to rubbing treatment.
After the application, a rubbing treatment is performed. Then, the array substrate 21 and the opposing substrate 22 are opposed to each other with a predetermined gap therebetween via a sealing material (not shown), and the liquid crystal layer 2 is disposed between the substrates 21 and 22.
3 is injected and sealed. Further, the liquid crystal display device 20 is obtained by arranging the polarizing plates 25 on the outer surfaces of both substrates 21 and 22 respectively.

With this structure, after the contact holes 45 and 46 are formed, the Mo / Al / Mo laminated film 47 is formed and then patterned to form the semiconductor film 39, the low-resistance semiconductor film 40, the source electrode 48, and the drain electrode. 49 and a signal line (not shown) are collectively formed, and then the pixel electrode 35 is formed on the upper surface thereof. Therefore, as compared with the conventional manufacturing process, the number of patterning steps performed by using a mask pattern is reduced. Can be reduced from seven sheets to five sheets, and the time required for the manufacture can be shortened, the cost of manufacturing materials used can be reduced, and the cost of the apparatus can be reduced.

The source electrode 48 and the drain electrode 49
After the formation of the signal lines (not shown) and the scanning lines (not shown), the pixel electrodes 35 are arranged on the upper surface of the array substrate 21, so that the positional deviation margin between the pixel electrodes 35 and each wiring layer is reduced. There is no need to take this into consideration. For example, when used in a liquid crystal display device, the aperture ratio can be improved, and a large-capacity, high-definition, high-luminance display can be obtained.

Further, since the uppermost layer film 30b of the scanning line pad electrode and the uppermost layer film 34b of the signal line pad electrode are formed of the ITO film which is the same material as the pixel electrode 35, it is made of a normal metal such as aluminum (Al). Since it is harder than formed, even if the material is undesirably scratched at the time of connection with an external circuit, short-circuit failure between adjacent pads is unlikely to occur, and the production yield can be improved. Further, using the ITO film as a mask pattern, molybdenum (Mo) in the upper layer of the source electrode 48 and the drain electrode 49 is selectively removed by etching, and then the surface of the source electrode 48 and the drain electrode 49 is subjected to hot pure water treatment to form an oxide protective film 50, 51. By forming, short-circuiting between the source electrode 48 and the drain electrode 49 due to undesired conductive particles such as molybdenum (Mo) oxide is reduced, and the production yield can be improved. In addition, it is not necessary to manufacture a passivation film for a protective film on the uppermost surface of the array substrate, and it is possible to directly arrange an alignment film, whereby the number of manufacturing steps can be further reduced and cost can be further reduced.

The present invention is not limited to the above embodiment, but can be modified without departing from the spirit of the invention. For example, the pixel electrode layer may be formed above the scanning lines and the signal lines. If so, the layer structure of the TFT 200 and the thickness of each layer are arbitrary. Further, the structure of the laminated film constituting the source electrode, the drain electrode or the scanning line pad electrode and the signal line pad electrode is also arbitrary, and the metal of the uppermost layer is molybdenum (M
The material is not limited to o) and may be tungsten (W) or the like as long as it is a high melting point metal.

[0029]

As described above, according to the present invention, by forming a pixel electrode on an upper layer of an array substrate, a source electrode, a drain electrode and a semiconductor film formed thereunder can be formed in the same master pattern. The patterning used enables batch formation and the number of master patterns required for the array substrate manufacturing process can be reduced as compared with the conventional method. Cost reduction can be realized. In addition, an oxidation protection film is formed on the surface layers of the source electrode and the drain electrode of the thin film transistor by using the transparent conductive film constituting the uppermost film of the pixel electrode, the electrode terminal of the signal line and the uppermost film of the electrode terminal of the scanning line as a mask pattern. Is formed, the risk of short circuit between the source electrode and the drain electrode can be reduced, the production yield can be improved, and the passivation film for the protective film on the uppermost surface of the array substrate can be eliminated. The production cost can be further reduced.

Therefore, by using such an array substrate for a liquid crystal display device, it is possible to reduce the number of manufacturing steps and, consequently, to provide a low-cost, high-density, large-capacity, high-definition, high-brightness liquid crystal display device. Can be put to practical use.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view showing a liquid crystal display device according to an embodiment of the present invention.

FIGS. 2A and 2B show a manufacturing process of an array substrate according to an embodiment of the present invention, wherein FIG. 2A shows a process of forming a gate electrode, a scanning line pad and a signal line pad, and FIG. 2B shows first and second gate insulating films. FIG. 3C is a schematic explanatory view showing a state in which a semiconductor film and a channel protective film are formed, FIG. 3C shows a state in which the channel protective film is formed, and FIG.

3A and 3B show a manufacturing process of an array substrate according to an embodiment of the present invention, wherein FIG. 3A shows a process of forming a contact hole, FIG. 3B shows a process of forming a laminated film, and FIG. When the semiconductor film, the source electrode, the signal line, the drain electrode, the scanning line pad electrode and the signal line pad electrode are collectively formed, (d) shows the formation of the pixel electrode, the scanning line pad electrode top layer film and the signal line pad electrode top layer film. FIG. 4E is a schematic explanatory view showing a state in which an oxide protective film is formed on the surface of the source electrode and the drain electrode.

FIG. 4 is a schematic partial cross-sectional view showing a conventional liquid crystal display device.

5A and 5B show a conventional manufacturing process of an array substrate, in which FIG. 5A shows the formation of the gate electrode and the scanning line, FIG. 5B shows the formation of the etching stopper, and FIG. 5C shows the formation of the semiconductor layer and the low-resistance semiconductor layer. FIG. 4D is a schematic explanatory view showing the pixel electrode when it is formed.

6A and 6B show a conventional manufacturing process of an array substrate, in which FIG. 6A shows a process of forming a contact hole, FIG. 6B shows a process of forming a source electrode, a drain electrode and a pad electrode, and FIG. FIG.

[Explanation of symbols]

 Reference Signs List 20 liquid crystal display device 21 array substrate 22 counter substrate 23 liquid crystal layer 24 alignment film 25 polarizing plate 26 gate electrode 28 first gate insulating film 29 second gate insulating film 30a scanning pad electrode 30b ... Scanning line pad electrode uppermost layer film 34a. Signal line pad electrode 34b. Signal line pad electrode uppermost layer film 35. Pixel electrode 36. Light shielding film 37. Color filter 38. Counter electrode 39. Semiconductor film 40. Low resistance semiconductor film 41. ... Semiconductor film 42 ... Channel protective film 43 ... Channel protective film 44 ... Low resistance semiconductor film 45,46 ... Contact hole 47 ... Laminated film 48 ... Source electrode 49 ... Drain electrode 50,51 ... Oxidation protective film 100,101 ... Glass substrate 200 ... TFT

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/146 H01L 27/14 A 5G435 29/786 29/78 612D 21/336 (72) Inventor Kaneko et al. F-term (reference) 2H092 JA26 JA29 JA33 JA35 JA36 JA38 JA39 JA42 JA43 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB52 JB57 JB63 JB69 KA05 MA16 KA08 MA16 MA13 MA17 MA27 MA35 MA37 MA41 NA25 NA27 4M118 AA10 BA14 FB03 FB13 5C094 AA05 AA10 AA43 AA44 BA03 BA43 CA19 CA24 DA14 DA15 DB04 EA04 EA07 EB02 ED03 ED14 ED15 FB12 FB14 FB15 GB10 H19 H18 EJ17 H18 H18 H19 H18 H19 H18 GG04 KK20 MM08 PP15 QQ08 QQ19 QQ89 RR03 RR04 RR06 SS26 VV15 XX31 XX33 XX34 5F110 AA16 AA26 BB01 CC07 DD02 EE06 EE44 FF02 FF03 FF32 GG02 GG15 GG25 GG35 GG47 HK09 HK16 HK25 HK35 HK37 HL03 HL04 HL12 HL23 HL27 HM17 HM19 NN12 NN24 NN35 NN72 NN80 QQ03 5G435 AA00 AA03 AA17 BB12 EE33 FF05 FF13 HH12 HKK13 HH14

Claims (7)

[Claims] A scanning line provided on an insulating substrate and including a gate electrode and a connection terminal; a semiconductor film provided on the gate electrode via an insulating film; and electrically connected to the semiconductor film. A source electrode, a signal line including a drain electrode and a connection terminal electrically connected to the semiconductor film, a pixel electrode disposed on the source electrode, and a protection layer disposed on a connection terminal of the signal line Patterning a conductive film to form the pixel electrode and the protective film; and modifying at least the source and drain electrode surfaces exposed from the pixel electrode using the pixel electrode as a mask. A method for manufacturing an array substrate, comprising: 2. The method for manufacturing an array substrate according to claim 1, wherein in the altering step, the surface of the source and drain electrodes exposed from the pixel electrode is treated with hot water. 3. The method according to claim 1, wherein the source and drain electrodes include a first conductive layer and a refractory metal layer on the first conductive layer. 4. The method according to claim 1, wherein the altering step includes a step of peeling off the refractory metal layer exposed from the pixel electrode, and a step of altering the surface of the first conductive layer exposed from the pixel electrode. The method for manufacturing an array substrate according to claim 3. 5. The method according to claim 4, wherein the altering step includes a step of oxidizing a surface of the first conductive layer exposed from the pixel electrode. 6. The method according to claim 5, wherein the oxidation treatment is a hot water treatment. 7. The array substrate according to claim 3, wherein the first conductive layers of the source and drain electrodes include at least aluminum or chromium, and the refractory metal layer includes molybdenum, titanium, or tungsten. Production method.