JPS62183433A - Production of active matrix liquid crystal display panel - Google Patents

Production of active matrix liquid crystal display panel

Info

Publication number
JPS62183433A
JPS62183433A JP61025003A JP2500386A JPS62183433A JP S62183433 A JPS62183433 A JP S62183433A JP 61025003 A JP61025003 A JP 61025003A JP 2500386 A JP2500386 A JP 2500386A JP S62183433 A JPS62183433 A JP S62183433A
Authority
JP
Japan
Prior art keywords
liquid crystal
insulating film
electrode
gate
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61025003A
Other languages
Japanese (ja)
Inventor
Yasuhiro Nasu
安宏 那須
Satoru Kawai
悟 川井
Tomotaka Matsumoto
友孝 松本
Koichi Tatsuoka
浩一 立岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61025003A priority Critical patent/JPS62183433A/en
Publication of JPS62183433A publication Critical patent/JPS62183433A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a TFT-LCD panel free from a short-circuit defect with high yield without executing time-requiring complex work such as destatization in a panel forming process by removing a gate insulating film on a gate bus line end part after the end of a liquid crystal sealing process. CONSTITUTION:A gate electrode 2-1 is formed on a glass substrate 1 and an insulating film 3 and a semiconductor active layer 4 are formed on the electrode 2-1. Then, a TFT matrix board consisting of a drain electrode 5, a source electrode 6, a TFT protection film 7 such as polyimido, a drain bus line 8, a light shielding film 9, a contact metal 10, a display electrode 11, an orientation film 12-1, etc., is formed. But the etching of the gate insulating film 3 is not executed. Then, an opposite board 15 on which a color filter 14, a transparent electrode 13, an orientation film 12-2, etc., are formed is adhered to the TFT board 13 by a sealing material 13 and then liquid crystal 14 is sealed. Then, polarizing plates 16-1, 16-2 are adhered and finally the gate insulating film 3 on a gate bus line terminal part 2-2 is etched and removed.

Description

【発明の詳細な説明】 〔概要〕 本発明は薄膜トランジスタを用いたアクティブマトリッ
クス液晶表示パネルの製造方法において、ゲートバスラ
インとドレインパスライン間のゲート絶縁膜の静電破壊
による短絡欠陥発生を除去するため、表示パネル化工程
の最終工程までゲート電極が完全に基板とゲート絶縁膜
の間に埋め込まれるようにして製造工程途中でゲート絶
縁膜に電界が印加されにくくなるようにゲート絶縁膜の
破壊を防止したものである。
[Detailed Description of the Invention] [Summary] The present invention eliminates short-circuit defects caused by electrostatic breakdown of a gate insulating film between a gate bus line and a drain pass line in a method of manufacturing an active matrix liquid crystal display panel using thin film transistors. Therefore, the gate electrode is completely buried between the substrate and the gate insulating film until the final step of the display panel fabrication process, and the breakdown of the gate insulating film is prevented so that an electric field is less likely to be applied to the gate insulating film during the manufacturing process. This was prevented.

〔産業上の利用分野〕[Industrial application field]

本発明は薄膜トランジスタ(T P T)を用いたアク
ティブマトリックス液晶表示パネル(L CD)の製造
方法に関する。
The present invention relates to a method for manufacturing an active matrix liquid crystal display panel (LCD) using thin film transistors (TPT).

TPT−LCDはカラー化、階yA表示を可能とするフ
ラットパネルディスプレーとして有効な方式の表示パネ
ルであるが、微細パターニングプロセスを多用するため
低歩留りによる高コマト化が問題となる。このため、重
要な欠陥の1つであるパスライン間短絡欠陥のi率を低
減させる製造方法が必要とされる。
TPT-LCD is a display panel that is effective as a flat panel display that enables color and gradation display, but since it uses many fine patterning processes, it has a problem of high frame rate due to low yield. Therefore, there is a need for a manufacturing method that reduces the i-rate of short-circuit defects between pass lines, which is one of the important defects.

〔従来の技術〕[Conventional technology]

第4図は従来のTI’T−LCDパネルの製造工程を示
す図である。次に製造工程について説明する。
FIG. 4 is a diagram showing the manufacturing process of a conventional TI'T-LCD panel. Next, the manufacturing process will be explained.

ガラス基板1上にゲート′M[2−1を形成し、その上
に呈化シリコン(SiN)や酸化シリコン<5lotJ
等の絶h&膜3と、水素化アモルファスシリコン(a−
8i:H)やポリシリコン等の半導体活性Nl14を成
膜する。なお2−2はゲートバスラインの端末部であり
、このゲートバスラインにゲート電極2−1が接続され
ている。(al欠にドレイン電極L極5、ソース電極6
、ポリイミド等のTPT保護[7,ドレインパスライン
8、M光M9、コンタクトメタル10、表示電極11、
ポリイミド%PVAの配向yx2−1等から成るTFT
マトリ・シクス基板を作製する。
A gate 'M[2-1] is formed on a glass substrate 1, and a silicon oxide (SiN) or silicon oxide <5lotJ is formed on it.
etc., and hydrogenated amorphous silicon (a-
8i:H) or polysilicon or the like is formed into a film. Note that 2-2 is a terminal portion of a gate bus line, and a gate electrode 2-1 is connected to this gate bus line. (Al is missing the drain electrode L pole 5, the source electrode 6
, TPT protection such as polyimide [7, drain pass line 8, M light M9, contact metal 10, display electrode 11,
TFT consisting of polyimide% PVA orientation yx2-1 etc.
Fabricate a Matri-Six substrate.

この工程の途中でゲートバスライン端末部2−2上のゲ
ート絶縁IM3を除去する。 (blカラーフィルタ1
4、透明電極13、配向膜12−2等の作り付けられた
対向基板15をシール材13を用いてTPT基板13に
はり合せ、液晶14を封入する。その後偏光板16−1
.16−2を張り付ける。(c) 〔発明が解決しようとする問題点〕 従来の製造方法では、TFT基板1上にTFTマトリ9
クスを作製するプロセス中にゲートバスライ/端末部2
−2を露出させ、その後に液晶封入吟のプロセスを行な
っていた。
During this step, the gate insulator IM3 on the gate bus line terminal portion 2-2 is removed. (bl color filter 1
4. The counter substrate 15 on which the transparent electrode 13, the alignment film 12-2, etc. are attached is attached to the TPT substrate 13 using the sealing material 13, and the liquid crystal 14 is sealed. After that, polarizing plate 16-1
.. Attach 16-2. (c) [Problems to be solved by the invention] In the conventional manufacturing method, the TFT matrix 9 is placed on the TFT substrate 1.
gate bus lie/terminal part 2 during the process of manufacturing
-2 was exposed, and then the liquid crystal encapsulation process was performed.

これらプロセス中には以下のように静電気を発生する作
業が長当存在する。つまりTPTマトリックス作製プロ
セス中にはEB蒸着やプラズマエツチング、液晶封入プ
ロセス中には2ビツグによる液晶配向処理や対向基板張
り合せや偏光板張り付は工程である。
During these processes, there have long been operations that generate static electricity, as described below. That is, EB evaporation and plasma etching are steps during the TPT matrix fabrication process, and liquid crystal alignment treatment using 2 bits, counter substrate bonding, and polarizing plate bonding are steps during the liquid crystal filling process.

従来、このような工程中の静電気によ゛るゲート絶縁膜
ari&壊を防止するため、工程途中でパスライン間を
ショートさせ最後に切り離す。又は静電気を各工程でモ
ニタしなから除電を行いながら作業する0というよう・
な方法が必要であった。
Conventionally, in order to prevent damage to the gate insulating film due to static electricity during such a process, pass lines are short-circuited during the process and then separated at the end. Or, you can work while removing static electricity without monitoring static electricity in each process.
A new method was needed.

しかしながらこのような静電気対策は作業性が非常く悪
く、また十分な効果の得られないことがあった0 〔問題点を解決するための手段〕 本発明は上記従来の問題点を解決することな目的として
おり、この目的は本発明によれば#膜トランジスタマト
リックスアレイな用いたアクティブff ) IJフッ
クス晶表示パネルの製造方法において、ゲートバスライ
ン端部上のゲート絶縁膜を液晶封入プロセスの終了した
後に除去することを特徴とするアクティブマトリックス
液晶表示パネルの製造方法により達成される。
However, such static electricity countermeasures have very poor workability and may not be sufficiently effective. [Means for Solving the Problems] The present invention does not solve the above-mentioned conventional problems. According to the present invention, in the method for manufacturing an IJ Fuchs crystal display panel, the gate insulating film on the end of the gate bus line is removed after the liquid crystal encapsulation process is completed. This is achieved by a method for manufacturing an active matrix liquid crystal display panel, which is characterized in that it is subsequently removed.

〔作用〕[Effect]

本発明では最終工程までゲートバスライン端末部が埋め
込まれているためゲート絶縁膜には帯電の不拘−分以上
に電圧が印加されることがないので、静電破壊による短
絡点の発生がない。
In the present invention, since the terminal portion of the gate bus line is buried until the final step, a voltage exceeding the unrestricted charge is not applied to the gate insulating film, so that short circuits due to electrostatic breakdown do not occur.

また、端末部を露出する工程ではすでにTFT部は高純
度の液晶に囲われており水から守られているのでゲート
絶縁膜に電圧が印加されても破壊に至ることは少ない。
Further, in the step of exposing the terminal portion, the TFT portion is already surrounded by high-purity liquid crystal and protected from water, so even if a voltage is applied to the gate insulating film, it is unlikely to be destroyed.

〔実施例〕〔Example〕

第3図は本発明の実施例によるT P T −L CD
パネルの製造工程を示す図である。次(C製造工程を説
明する。
FIG. 3 shows a T P T -L CD according to an embodiment of the present invention.
It is a figure which shows the manufacturing process of a panel. Next (C manufacturing process will be explained.

ガラス基板l上にゲート電極2−1を形成し、その上に
窒化シリコy(SiN)や酸化シリコン(Stot3等
の絶縁膜3と、水素化アモルファスシリコン(a−8i
:H)やポリシリコン等の半導体活性層4を成膜する。
A gate electrode 2-1 is formed on a glass substrate l, and an insulating film 3 such as silicon nitride (SiN) or silicon oxide (Stot3) and hydrogenated amorphous silicon (a-8i) are formed on it.
A semiconductor active layer 4 made of polysilicon or the like is formed.

なお2−2はゲートバスライ/の端末部であり、このゲ
ートバスライ/ICゲート電極2−1が接続されている
。(a)次にドレイン電極5、ソース電極6.゛ポリイ
ミド等のTPT保護yX7、ドレインパスライン8.3
11光m 9 、フンタクトメタル10.表示′1を極
11、ポリイミド、PVAの配向膜12−1等から成る
TPTマトリックス基板を作製する口 ただしゲート絶縁膜3のエツチングは行わない。
Note that 2-2 is a terminal portion of the gate bus line/, to which this gate bus line/IC gate electrode 2-1 is connected. (a) Next, the drain electrode 5, the source electrode 6.゛TPT protection such as polyimide yX7, drain pass line 8.3
11 light m 9, funtact metal 10. The gate insulating film 3 is not etched as shown in FIG. 1 to form a TPT matrix substrate consisting of a pole 11, an alignment film 12-1 of polyimide, PVA, etc.

(bl カラーフィルタ14、透明電極13、配向膜12−2等
の作り付けられた対向基板15をシール材13を用いて
TPT基板13にはり合せ、液晶14を封入する口その
後偏光板16−1.16−2を張り付ける。(c) ゲートバスライン端末部2−2上のゲート絶縁膜3をエ
ツチング除去し、ゲート端末部2−2を露出させる。(
d) 第1図は本発明の製造方法により作製されたTPTマト
リックス基叛上におけるラビング工程中の帯電の様子を
示す図、第2図はゲート絶縁膜に対する帝[電荷の影響
を説明する原理図である。
(bl) The counter substrate 15 on which the color filter 14, the transparent electrode 13, the alignment film 12-2, etc. have been assembled is pasted on the TPT substrate 13 using the sealant 13, and after the opening in which the liquid crystal 14 is sealed, the polarizing plate 16-1. 16-2. (c) Etch and remove the gate insulating film 3 on the gate bus line terminal section 2-2 to expose the gate terminal section 2-2. (
d) Figure 1 is a diagram showing the charging state during the rubbing process on the TPT matrix substrate manufactured by the manufacturing method of the present invention, and Figure 2 is a principle diagram explaining the influence of electrical charge on the gate insulating film. It is.

第2図(bl K示す如〈従来はゲートバスライ/端末
部2−2がシッートされ例えばアース電位となっており
、このため第1図に示すTPT2の帯電型1frが直接
ゲート絶縁膜に影響する。しがしながら第2図(a)に
示す如く本発明ではゲート電極は浮いた状態でありゲー
ト絶縁°膜にはTFT部と端末部の帯電の差分が容量C
IとC,に分割されて印加されるのみで小さな値となる
ので静電気発生工程中であっても静電破壊がない。
As shown in Fig. 2 (bl K), conventionally, the gate bus line/terminal section 2-2 is seated and has, for example, a ground potential, so that the charged type 1fr of the TPT 2 shown in Fig. 1 directly affects the gate insulating film. However, as shown in FIG. 2(a), in the present invention, the gate electrode is in a floating state, and the difference in charge between the TFT part and the terminal part of the gate insulating film has a capacitance C.
Since the voltage is applied only by dividing it into I and C, it becomes a small value, so there is no electrostatic damage even during the process of generating static electricity.

またゲートバスライン端末部2−2を露出する工程では
すでにTFT部は高純度の液晶に囲われていて水から護
られているのでゲート絶縁膜に電圧がかかつても破壊に
至ることは少なくなる。
In addition, in the process of exposing the gate bus line terminal section 2-2, the TFT section is already surrounded by high-purity liquid crystal and protected from water, so even if voltage is applied to the gate insulating film, it is less likely to be destroyed. .

〔発明の効果〕〔Effect of the invention〕

本発明によれば、パネル作製工程中の除′lば等2時間
のかかる作業と行うことなく短絡欠陥のないTPT−L
CDパネルを鍋い歩留りで製造できるのでパネルの低コ
スト化が図れる。
According to the present invention, TPT-L without short-circuit defects can be produced without having to perform operations such as removal during the panel manufacturing process that take two hours.
Since CD panels can be manufactured at a low yield, the cost of the panels can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の製造方法により作製されたTPTマト
リックス基板上におけるラビング工程中の帯電の様子を
示す図、 第2図はゲート絶縁膜に対する帯電を荷の影響を説明す
るM埋図、 第3図は本発明の実施例によるTPT−LCDパネルの
製造工程を示す図、 第4図は従来のTPT−LCDパネルの製造工程を示す
図である。 図において1はガラス基板、2−1はゲート電極、2−
2はゲートパスライ/端末部、3はゲー杢Ni1月の輩
方5夫1−より作殻距tこTF丁マトリフヌtlakの
帯電の様子15 1  図 (と”                      
           (bンケート連珠膜への帯電電
荷の彰iを説明する図第 2 図 ンー2 本薙明の宴施忰1によ8説這工程をホす邑第 3 図
FIG. 1 is a diagram showing the state of charging during the rubbing process on a TPT matrix substrate manufactured by the manufacturing method of the present invention; FIG. 2 is a diagram showing the influence of charge on the gate insulating film; FIG. 3 is a diagram showing a manufacturing process of a TPT-LCD panel according to an embodiment of the present invention, and FIG. 4 is a diagram showing a manufacturing process of a conventional TPT-LCD panel. In the figure, 1 is a glass substrate, 2-1 is a gate electrode, 2-
2 is the gate pass line/terminal section, 3 is the charge state of the TF matryfunu tlak from the game 1 month's senior 5 husband 1- Figure 15
(Fig. 2 to explain the change of electrical charge to the cassette membrane) Fig. 3

Claims (1)

【特許請求の範囲】[Claims] 薄膜トランジスタマトリックスアレイを用いたアクティ
ブマトリックス液晶表示パネルの製造方法において、ゲ
ートバスライン端部(2−2)上のゲート絶縁膜(3)
を液晶封入プロセスの終了した後に除去することを特徴
とするアクティブマトリックス液晶表示パネルの製造方
法。
In a method for manufacturing an active matrix liquid crystal display panel using a thin film transistor matrix array, a gate insulating film (3) on an end portion (2-2) of a gate bus line;
A method for manufacturing an active matrix liquid crystal display panel, characterized in that the liquid crystal is removed after the liquid crystal encapsulation process is completed.
JP61025003A 1986-02-07 1986-02-07 Production of active matrix liquid crystal display panel Pending JPS62183433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61025003A JPS62183433A (en) 1986-02-07 1986-02-07 Production of active matrix liquid crystal display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61025003A JPS62183433A (en) 1986-02-07 1986-02-07 Production of active matrix liquid crystal display panel

Publications (1)

Publication Number Publication Date
JPS62183433A true JPS62183433A (en) 1987-08-11

Family

ID=12153776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61025003A Pending JPS62183433A (en) 1986-02-07 1986-02-07 Production of active matrix liquid crystal display panel

Country Status (1)

Country Link
JP (1) JPS62183433A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01136125A (en) * 1987-11-24 1989-05-29 Fujitsu Ltd Active matrix type liquid crystal display device
JPH01270026A (en) * 1988-04-22 1989-10-27 Seiko Epson Corp Formation of thin-film pattern
JPH02250037A (en) * 1989-03-23 1990-10-05 Matsushita Electric Ind Co Ltd Production of active matrix substrate and production of display device
KR100537020B1 (en) * 1997-03-03 2006-03-03 삼성전자주식회사 Manufacturing Method of Liquid Crystal Display Device for IPS Mode Thin Film Transistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01136125A (en) * 1987-11-24 1989-05-29 Fujitsu Ltd Active matrix type liquid crystal display device
JPH0758373B2 (en) * 1987-11-24 1995-06-21 富士通株式会社 Active matrix liquid crystal display device
JPH01270026A (en) * 1988-04-22 1989-10-27 Seiko Epson Corp Formation of thin-film pattern
JPH02250037A (en) * 1989-03-23 1990-10-05 Matsushita Electric Ind Co Ltd Production of active matrix substrate and production of display device
KR100537020B1 (en) * 1997-03-03 2006-03-03 삼성전자주식회사 Manufacturing Method of Liquid Crystal Display Device for IPS Mode Thin Film Transistor

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