JPH0691103B2 - Method for manufacturing insulating gate type transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a thin film field effect transistor using a thin film semiconductor as an active region.

Structure of conventional example and its problems Amorphous silicon formed by containing several% of hydrogen in its composition to compensate for imperfections of atomic bond pair can be formed at low temperature, and has a large area. It is attracting attention as a low-priced solar cell because it is easy to manufacture. However, the mobility of free electrons is 0.1 compared to single crystal silicon.
It is smaller than 3 cm or more by 1 cm ² / V · sec, and it is impossible to obtain a semiconductor device with performance suitable for integration. Still, it is possible to obtain a switching array of MIS transistors that constitute an image display device by combining with a liquid crystal cell, for example, which does not require high-speed operation or large current.

1 and 2 are a plan view and a process sectional view taken along the line AA 'of an amorphous silicon MIS transistor developed to achieve the above object. First, as shown in FIG. 2A, a first metal layer 2 to be a gate electrode is selectively deposited on an insulating substrate such as a glass plate 1. Next, a gate insulating layer 3, an amorphous silicon layer 4 containing no impurities, and an amorphous silicon layer 5 containing impurities are deposited on the entire surface. In these deposition methods, plasma deposition by glow discharge of a silane-based gas is simple, and ammonia is used to obtain silicon nitride in the gate insulating layer 3 and amorphous silicon containing impurities is used to obtain silicon nitride in the gate insulating layer 3. For example, diborane or phosphine may be added.

After that, as shown in FIG. 2B, the amorphous silicon layers 4 and 5 are selectively removed to form island-shaped amorphous silicon layers 4'and 5 '. Although not shown in FIG. 2, an opening 6 (shown in FIG. 1) is formed in the gate insulating layer 3 on the first metal layer 2 to partially expose the first metal layer 2 and As shown in FIG. 7c, a pair of source / drain wirings 7 and 8 made of a second metal layer partially overlapping the first metal layer 2 are selectively deposited so as not to form an offset gate structure. . Of course, at this time, the gate wiring 9 made of the second metal layer is also formed on the gate insulating layer 3 including the opening 6. Finally, as shown in FIG. 2d, the impurity-containing amorphous silicon layer 5'on the impurity-free amorphous silicon layer 4'is removed by using the source / drain wirings 7 and 8 as a mask. Amorphous silicon MIS transistor is completed.

The amorphous silicon layers 10 and 11 containing impurities interposed between the source / drain wirings 7 and 8 and the amorphous silicon layer 4 ′ are necessary for forming a good ohmic contact and are amorphous. It is possible to operate as a MIS transistor without the presence of the silicon layers 10 and 11, but the tendency of higher operating voltage is unavoidable. In that case, the material of the source / drain wiring 7 and 8 and the deposition The method needs attention. In the case where the amorphous silicon layers 10 and 11 containing impurities are interposed, the source / drain wirings 7 and 8 are made of general aluminum.

Now, as shown in FIG. 2c, the amorphous silicon layer 5'containing impurities is selectively removed using the source / drain wirings 7 and 8 as a mask, but if the removal is insufficient. It has been found that the source-drain 10 and 11 are electrically connected by the remaining amorphous silicon layer containing impurities, thereby increasing the leak current between the source and drain. However, there is no etching material having a large selection ratio between the amorphous silicon containing impurities and the amorphous silicon not containing impurities, in other words, a large difference in etching speed, and hydrofluoric acid: nitric acid = 1: 1. Even if an appropriate amount of acetic acid is added to the 30th solution, the selection ratio is at most about 5. That is, it is extremely difficult to selectively remove only the amorphous silicon layer containing impurities.

Therefore, normally, as shown in FIG. 2d, when the amorphous silicon layer 5'containing impurities is removed, the amorphous silicon layer 4'containing no impurities is also partially removed by over-etching to form a concave shape.
It is generally set to 12. As a result, although the increase of the leak current can be suppressed, the film thickness of the amorphous silicon layer 4'which does not contain the impurity and becomes the channel of the MIS type transistor surely decreases. In a specific combination, molybdenum is used for the gate metal layer 2, amorphous silicon layer 5 containing phosphorus as an impurity, aluminum is used for the source / drain wirings 7 and 8, and a hydrofluoric acid: nitric acid = 1: 30 solution is used as an etching solution. When it is used, the etching speed of the amorphous silicon layer is multiplied by 5 to 10 times, and the amorphous silicon layer 4'containing no 5000 liters of impurities is only 4 to 4 times.
It disappears in 5 seconds.

If the channel portion becomes too thin, the MIS transistor's o
It is not uncommon for the n-current to decrease remarkably and be less than 1/10 of the case of proper etching. To complicate matters, the conventional structure example, in which the opposite side of the channel is exposed to the outside air in FIG. 2d, it is easy to adsorb moisture in the atmosphere. Since the OH ^- group in the adsorbed water turns the channel part into p-type, n
The threshold voltage of the channel operation MIS transistor increases with time. That is, if the operating voltage is constant, the on-current between the source and drain decreases with time. However, it was found that the moisture adsorbed by heating in a dry nitrogen gas at about 150 ° C. was lost, and the characteristics immediately after production were restored.

As described above, in the conventional MIS transistor of amorphous silicon according to the structural example, it is unavoidable that the characteristic nonuniformity due to the film slip of the channel portion is inevitable, and the reliability is extremely uncertain.

SUMMARY OF THE INVENTION In view of such conventional problems, it is an object of the present invention to prevent film slippage in the channel portion, to reliably form ohmic contact between the source and drain electrodes, and to secure an operating current in the on state. Another object of the present invention is to provide a highly reliable MOS transistor.

According to the present invention, an n-type amorphous silicon is continuously formed on the entire surface without exposing to a contaminating atmosphere after vapor phase etching by forming an insulating layer that shields the channel portion from the outside air and forming an opening in the insulating layer. By forming the layer, the ohmic contact failure is improved.

Description of Embodiments Embodiments of the present invention will be described below with reference to FIG. It should be noted that each part having the same function is denoted by the same reference numeral as in FIGS.

First, as shown in FIG. 3A, a first metal layer 2 to be a gate is selectively deposited on the insulating substrate 1. Then, the first insulating layer 3, the amorphous silicon layer 4 containing no impurities, and the second insulating layer 13 are sequentially deposited on the entire surface. The deposition is preferably performed in the same chamber or in a plurality of chambers with a vacuum transfer path so that each deposition is not exposed to the atmosphere. For this purpose, a deposition method by glow discharge decomposition of a silane-based gas is simple. Next, as shown in FIG. 3b, a pair of openings partially overlapped with the gate metal layer 2 in the second insulating layer 13.
14 is formed to selectively expose the amorphous silicon layer 4 containing no impurities. Next, the surface is plasma-etched with a source gas containing SiF ₄ , XeF _2, etc. as a main component, and thereafter the surface is continuously exposed to a non-contaminating atmosphere such as air without contamination with impurities as shown in Fig. 3c. Crystalline silicon layer 5 '
To wear.

Thereafter, as shown in FIG. 3d, the amorphous silicon layer 5, the second insulating layer 13, and the amorphous silicon layer 4 are sequentially selectively removed to form an island-shaped amorphous layer including the opening. Quality silicon layer 5 ',
Form 4 '. Although not shown, an amorphous silicon layer containing no impurities is formed by forming an opening 6 for providing a connection to the gate metal layer 2 on the first insulating layer 3 and then depositing a metal layer on the entire surface. Source / drain wirings 7, 8 are formed on the first insulating layer 3 including the amorphous silicon layer containing impurities deposited on the surface 4 ', and the first insulating layer 3 is formed on the first insulating layer 3.
A gate wiring 9 is formed on the insulating layer 3. Finally, using the source / drain wirings 7 and 8 as a mask, the second insulating layer 13 '
The amorphous silicon layer 5'containing the impurities is removed to remove the third
The MIS transistor according to the present invention is completed as shown in FIG.

As is clear from the comparison between FIG. 2d and FIG. 3e, in the step of selectively removing the amorphous silicon layer 5 ′ containing impurities using the source / drain wirings 7 and 8 as masks,
In the present invention, the presence of the second insulating layer 13 does not etch the amorphous silicon layer 4 which does not contain impurities and serves as a channel portion. Therefore, variations in transistor characteristics due to film slippage in the channel portion do not occur. At the same time, the second insulating layer 13 'shields the amorphous silicon layer 4', which does not contain impurities, which constitutes the channel portion, from the atmosphere. For this reason, even if moisture in the air is adsorbed, the channel portion does not reach the p-type through the second insulating layer 13 ', and the operation is stable even for a long time operation. Of course, passivation in the general sense, that is, the same effect can be expected by depositing an appropriate insulating layer on the entire surface in the step after FIG. 2d, but the source / drain wirings 7 and 8 are present. In addition, the passivation insulating layer is apt to be contaminated with metal, and the resistance value of the source / drain wiring layer becomes high due to a chemical reaction between the passivation insulating layer and the source / drain wiring depending on the material. On the other hand, in the present invention, the second insulating layer 13 having the passivation function is formed following the deposition of the amorphous silicon layer 4 containing no impurities, so that the amorphous silicon layer and the second insulating layer are formed. An excellent effect that various characteristics of the MIS transistor did not change by the introduction of the second insulating layer which is also a passivation film, was obtained at the interface with and the second insulating layer itself having a high purity at a semiconductor level.

Regarding ohmic contact between the source / drain wirings 7 and 8 and the semiconductor layer 4 ′ which is the active region of the transistor,
It is fully formed as described below. For example, P (phosphorus) -doped amorphous silicon is deposited as a layer for forming ohmic contact. If only the water washing / drying process is applied as a pretreatment for this deposition, deposition is performed in some parts of the large-area element where ohmic contact is not formed. However, as the present inventors have previously presented, SiF ₄ and XeF ₂
When the interface of the MIS type transistor is etched by, for example, and a semiconductor layer is continuously deposited, a clean interface is obtained from the viewpoint of electrical characteristics and its stability.

Therefore, before depositing the formation layer of the ohmic contact, plasma etching is performed with a source gas that does not contaminate the amorphous silicon layer such as SiX ₄ or XeF ₂ , and the surface is continuously exposed to a contaminating atmosphere such as the atmosphere. By depositing an amorphous silicon layer doped with P, ohmic contact can be formed with high reliability over the entire surface of the semiconductor element.

Effect of the Invention In the MIS transistor shown in FIG. 2D, when polar water molecules are adsorbed on the active region semiconductor layer between the source and drain electrodes, the electrical characteristics of the transistor,
Especially, it has a great influence on the dark current. In order to improve this instability, a second insulating layer which is also a passivation film is introduced, and various characteristics (electrical characteristics, thermal stability, temporal stability) of the MIS transistor can be excellently obtained. .

Further, the instability of the ohmic contact formation due to the structural change according to the present invention, a clean surface is obtained by vapor phase etching the surface which becomes the interface between the semiconductor layer and the ohmic contact formation layer, and the surface is made into a polluted atmosphere. Subsequent deposition of the ohmic contact formation layer without exposure allows for reliable ohmic contact formation over a large area.

As is clear from the above description, the gist of the present invention is applicable to all silicon semiconductors except single crystal silicon, and in addition to the amorphous silicon mentioned in the examples, microcrystalline silicon and polycrystalline silicon are also applicable. There is no problem. Also the first
Needless to say, silicon oxide other than silicon nitride or silicon carbide is also used as appropriate for the second insulating layer.

[Brief description of drawings]

1 and 2 a to d are plan views and process cross-sectional views of a MIS type transistor having a conventional structure, and FIGS. 3 a to 3 e are process cross-sectional views of a MIS type transistor according to an embodiment of the present invention. . 1 ... Insulating substrate, 2 ... Gate metal layer, 3 ... First insulating layer, 4, 4 '... Amorphous silicon layer containing no impurities, 5, 5' ... Amorphous containing impurities Quality silicon layer, 6 ...
Opening, 7,8 ... Source / drain wiring, 9 ... Gate wiring, 10,11 ... Source / drain, 12 ... Concave, 13 ...
… Second insulating layer, 14 …… Opening.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sadakichi Hotta 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Hiroki Saito, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A step of selectively depositing and forming a first metal layer on an insulating substrate, and a first insulating layer, a non-single-crystal silicon layer containing no impurities, and a second insulating layer on the entire surface. A step of sequentially depositing, a step of forming a pair of openings in the second insulating layer overlapping a part of the first metal layer, a step of vapor-phase etching, and a contamination of the main surface after the etching. A step of continuously depositing a non-single-crystal silicon layer containing impurities without exposing to the atmosphere, and a non-single-crystal silicon layer containing impurities and a non-single-crystal silicon layer containing no impurities. A step of forming a single crystal silicon layer in an island shape,
Selectively depositing a second metal layer completely containing the non-single-crystal silicon layer containing impurities on the opening; and using the second metal layer as a mask to remove impurities on the second insulating layer. And a step of removing the non-single crystal silicon layer containing the insulated gate transistor. 2. The first insulating layer, the non-single-crystal silicon layer containing no impurities, and the second insulating layer are continuously deposited without being exposed to the atmosphere. A method of manufacturing an insulated gate transistor according to claim 1.