JPS5919379A - Insulated gate type transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the electrostatic capacity between a gate and source, drain by forming the source and drain by lifting-off with amorphous silicon containing an impurity in such a manner that the ends are not planarly superposed on the same linear line. CONSTITUTION:An amorphous silicon layer 4' which does not contain an impurity, the first insulating layer 3', the first metal layer 2' and a thin aluminum layer 13' are sequentially covered on a glass plate 1. Then, the layer 4' is selectively exposed, an amorphous silicon layer 5' which contains an impurity is covered on the overall surface, and insular layers 4', 5' are formed. After the layer 13' is molten by allowing it to stand for in hot phosphoric acid to expose the layer 2', the second insulating layer 15 is covered on the overall surface, the second metal layer is selectively covered through the holes selectively formed, and source, drain wirings 7, 8 and gate wirings are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to insulated gate (MIS) transistors, particularly amorphous silicon MIS transistors.

Conventional structure and its problems Amorphous silicon, which is formed by containing several atoms of hydrogen or fluorine in its composition to compensate for imperfections in atomic bonding pairs, can be formed at low temperatures. It is attracting attention as a semiconductor material for realizing low-cost solar cells because it can be easily made into a large area. However, compared to single crystal silicon, the free electron mobility is 0.1 to 1 cMV-sa.
c, which is more than 3 orders of magnitude smaller than 9 pages, making it impossible to obtain a semiconductor element with performance worthy of integration in a general sense. Even so, it is possible to obtain a switching array of MIS transistors that does not require high-speed operation or large on-current and constitutes an image display device by combining with, for example, a liquid crystal cell.

FIGS. 1 and 2(a) to (d) are a plan view and a cross-sectional view of an A-A/thin line manufacturing process of an amorphous silicon MIS transistor developed to achieve the above object. First, a first metal layer, such as a molybdenum layer 2, constituting a gate electrode is selectively deposited on an insulating substrate 1 made of, for example, a glass plate. Next, a gate insulating layer 3 made of, for example, silicon nitride, an amorphous silicon layer 4 containing almost no impurity to serve as a donor or acceptor, and an amorphous silicon layer 6 containing the impurity are deposited on the entire surface. Plasma deposition using glow discharge of silane gas is a simple method for depositing these thin films, and if silicon nitride is to be obtained for the gate insulating layer 3, ammonia or amorphous silicon containing impurities must be obtained. If so, it is sufficient to add grain 10 page run or phosphine to the preparation gas.

Thereafter, as shown in FIG. 2(b), the amorphous silicon layers 4 and 6 are selectively removed to form an island-shaped amorphous silicon layer 4'.
, 5'. After forming an opening 6 in the gate insulating layer 3 to expose a part of the gate metal layer 2 as shown in FIG. 2(e), an offset structure is formed as shown in FIG. 2(C). a pair of source/drain wirings 7 made of a second metal layer partially overlapping with the gate metal layer 2;
8 is selectively formed. At the same time, a gate wiring 9 made of a second metal layer is also formed in the gate metal layer 2 through the opening 6. Finally, as shown in FIG. 2(d), the amorphous silicon layer 6' containing impurities on the island-shaped amorphous silicon layer 6' is selectively removed using the source/drain wirings 7 and 8 as a mask. As a result, an amorphous silicon MIS transistor having a conventional structure is completed.

Note that FIG. 2(e) shows the B-B' of the transistor in FIG.
It is a cross-sectional view taken along the twill line.

The impurity-containing amorphous silicon 11 and -gin layers 10 and 11 interposed between the source/drain wirings 7 and 8 and the amorphous silicon layer 4' are necessary to form good ohmic contact. Although it is possible to operate as a MIS transistor even without the amorphous silicon layer 10 and 11, the tendency for the operating voltage to increase is unavoidable. Care must be taken regarding the material and application method. If an amorphous silicon layer 10.11 containing impurities is present, general aluminum is sufficient for the source/drain wiring 7.8.

The MIS transistor described above has the following problems. First, regarding the method of forming the source/drain, in the conventional structure shown in FIG. The planar overlap of the layer 2 and the source/drain 10.11 forms an overlap capacitance with the amorphous silicon 4' containing no impurities and the gate insulating layer 3 as a laminated dielectric. MIS) The transistor channel width 'ii is 100 μm, and the film thickness of the amorphous silicon layer 4' and the gate insulating layer 3 made of silicon nitride is 5000 μm, respectively.
If the overlap between the gate and the source/drain is 5 μm, then the gate/source or gate/drain
The overlap capacitance between drains is only 0.1 pF at most.

However, even a liquid crystal cell with an effective area of 100 to 150 μm square has a capacitance component of only about 0.1 pF, which is almost equal to the above-mentioned overlap capacitance.

At the rise and fall of the gate pulse applied to turn on and off the transistor (MIS) transistor,
The potential of the liquid crystal cell, which is a load connected to the source or drain, fluctuates, making it difficult to display images. If you insert an auxiliary capacitor that is much larger than the overlap capacitance in parallel with the liquid crystal cell and stabilize the potential, then in order to charge to the specified potential, either increase the charging current (i.e., the ON current of the MIS) transistor or increase the writing time. It has to be made longer. However, the former requires a large degree of mobility and is currently technically difficult, and the latter does not allow a large number of scanning lines to be set. For this reason, image display devices that combine liquid crystal and amorphous silicon MIS) transistors have only been available with a large liquid crystal cell size of 1 mm square and a small number of 13 pixel pages of about 10 x 10. is the current situation.

The following problem arises in connection with passivation.

As shown in FIG. 2(d)K, the amorphous silicon layer 5' containing impurities is selectively removed as a mask, but if the removal is insufficient, the source/drain Due to the increase in leakage current between the layers and the lack of an etching method that etches only the amorphous silicon layer containing impurities, the amorphous silicon layer 4' containing impurities is also etched due to overetching. Remove part and make concave 1
Generally, it is set to 2. As a result, the thickness of the impurity-free amorphous silicon layer 4' constituting the channel is reduced. Furthermore, since the opposite side of the channel is exposed to the outside air, moisture in the atmosphere is likely to be adsorbed. O in adsorbed water
Since the H-group forms the channel part'rp shape, the threshold voltage of the n-channel MIS transistor increases with the passage of time. However, it was found that the adsorbed moisture was lost by heating in dry nitrogen gas at about 150'C, and the properties immediately after manufacture were restored. Therefore, stable operation cannot be expected unless the amorphous silicon layer 4' constituting the channel portion is protected from the atmosphere and moisture.

In this way, MIS of amorphous silicon with conventional structure example
) In transistors, first of all, it was possible to avoid unevenness in characteristics due to film burrs in the channel portion, and secondly, reliability was extremely unstable due to exposure of the channel portion. The most fatal drawback is that significant restrictions are placed on pulse operation.

OBJECTS OF THE INVENTION The present invention was made in view of the above circumstances, and an object of the present invention is to provide an MIS transistor having passivation and having small capacitance between the gate and source and between the gate and drain.

Structure of the Invention The main points of the present invention are the introduction of a thin film layer on which an amorphous silicon layer containing impurities can be deposited, and a gate metal layer that does not dissolve when the thin film layer is removed and does not lose its conductivity due to chemical reactions. Embodiments of the present invention will be described below with reference to the drawings. Each part of the 16-page function is given the same number as in FIGS. 1 and 2.

DESCRIPTION OF EMBODIMENTS FIG. 3 is a plan view of a transistor according to an embodiment of the present invention, and FIGS.
It is a sectional view of the manufacturing process along the line. First, as shown in FIG. 4(a), an amorphous silicon layer 42 containing no impurities is formed on a glass plate 1, and a first insulating layer 3 made of silicon nitride, for example.
1. A first metal layer made of, for example, molybdenum; 2. and a thin film layer 13 made of aluminum, for example, is successively applied.

At this time, the first layer is heated without exposing the amorphous silicon layer 4 to the atmosphere.
Deposition of the insulating layer 3 of
This is effective for strengthening the adhesion of the insulating layer 3. As described above, plasma deposition by glow discharge of silane-based gas is convenient for this reservoir, and can be realized within the same chamber or by a combination of a vacuum conveyance path and a plurality of chambers.

Next, as shown in FIG. 4(b), the thin film layer 19', the first
A laminated portion consisting of the metal layer 2' and the first insulating layer 3' is formed, and after selectively exposing the amorphous silicon layer 4, an amorphous silicon layer 5 containing impurities is deposited over the entire surface. Then, as shown in FIG. 4(C), an amorphous silicon layer is formed into island shapes 4' and 5'. Now, the thickness of the thin film layer 13', the first metal layer 2', and the first insulating layer 2' is set to 2000.
If there are 3000 people and 2000 people, then the laminated portion having a step of 7000 people exists between the island-like amorphous silicon layers 4', so the amorphous silicon layer 6' with a film thickness of 1500 or less is A step break occurs at the step portion 14 of the laminated portion.

At this time, if the pattern width of the first insulating layer 3' is narrower than that of the first metal layer 2' due to over-etching, the first metal layer 2' becomes eaves-like and the amorphous silicon layer 6' This not only ensures that the step is separated, but also eliminates the phenomenon that the amorphous silicon layer 5' and the first metal layer 2' come into contact along the side surfaces of the first insulating layer 3'.

Alternatively, as shown in FIG. 4 (fl), the first insulating layer 3'
and a first layer made of molybdenum as a mask for the thin film layer 13'.
The side surface of the metal layer 2' is removed by about 0.1 to 0.2 μm using, for example, hydrogen peroxide as an etching solution, to form a 2" pattern, and the pattern width is made smaller than that of the first insulating layer 3'. This is because the first metal layer 2/, which was in contact with the amorphous silicon layer 6' along the side surface of the first insulating layer 3', is forcibly cut off from contact and becomes 2''. be.

When left in hot phosphoric acid in the state shown in FIG. 4(C) or FIG. 4(f), the thin film layer 13' made of aluminum whose side surface is exposed due to the breakage dissolves, and at the same time, the aluminum layer 13' The upper amorphous silicon layer containing impurities is selectively removed to expose the molybdenum layer 2'. Thereafter, as shown in FIGS. 4(d) and 4(e), a second insulating layer 15 made of silicon nitride, for example, is deposited on the entire surface.
A second metal layer made of, for example, aluminum is selectively deposited through the selectively formed openings to form the source/drain wirings 7, 8 and the gate wiring 9, thereby completing the MIS transistor according to the present invention. It goes without saying that the impurity-containing amorphous silicon layers 10 and 11 formed on the impurity-free amorphous silicon layer function as sources and drains. In addition, the tel in Figure 4 is the third
FIG. 2 is a sectional view taken along the B E' twill line of the transistor shown in the figure.

FIG. 5 +al to fdl are the third
FIG. 2 is a cross-sectional view of the manufacturing process taken along line AA' of the transistor shown in the figure. First, as shown in FIG.
Insulating layer 32 of, for example, first metal layer 2 made of molybdenum
2. After sequentially depositing thin film layers 13 made of, for example, aluminum and selectively forming a laminated portion made of the thin film layer 13' and the first metal layer 2', a third layer made of, for example, silicon nitride is deposited.
An insulating layer 16 is deposited over the entire surface. In this state, anisotropic etching, for example parallel plate type reactive plasma etching, is performed to form the third
When the insulating layer 16 is completely removed, the third insulating layer 16' can be left only on the side surfaces of the laminated portion, as shown in FIG. 6fbl. For example, if this etching process is performed for 4 to 6 minutes when proper etching is performed for 3 minutes, the third insulating layer 16' will be anisotropically etched, although the film will be removed to some extent. There is specificity. Of course, due to over-etching, the thickness of the first insulating layer 3 is reduced by 19 bases.Then, the insulating layer 3 of the cylinder 1 is selectively removed to expose the amorphous silicon layer 4. Since this etching step is performed using a hydrofluoric acid-based etching solution which is isotropic etching, if the first insulating layer 3 is thick, there is a risk that the third insulating layer 16' may also be removed. As described above, the thickness of the first insulating layer 3 is reduced on the over-corrosion side. Therefore, the third insulating layer 16' does not disappear when the first insulating layer 3 is removed, and the thin film layer 13'
Even if the third layer does not remain on the side surface of the first metal layer 2', the third metal layer 2'
The insulating layer 16' can be left behind. And Figure 6 fc
After the amorphous silicon layer 6 containing impurities is deposited on the entire surface as shown in FIG. 1, the amorphous silicon layer is formed into an island shape 4'.

6'. In this state, as mentioned earlier, the thin film layer 13
At the same time as the first metal layer 2' is removed, the impurity-containing amorphous silicon layer on the thin film layer 13' is selectively removed.
is exposed.

Finally, as shown in FIG. 6(di), a second insulating layer 16 is deposited over the entire surface, and source/drain wirings 7.8 and A gate wiring 9 is formed to complete the MIS transistor according to the present invention.

Incidentally, in the three embodiments described above, the plan views are the same and are as shown in FIG. 3. Also, B-B' in Figure 3
Since the cross-sectional views along the line are also almost the same, only FIG. 4 (,) is shown.

The gist of the present invention lies in the introduction of a thin film layer on which amorphous silicon containing impurities can be deposited, and a first metal layer that does not dissolve when this thin film layer is removed and does not lose its conductivity due to chemical reaction, Other embodiments are described below.

If molybdenum is used for the thin film layer, aluminum is used for the first metal layer, and hydrogen peroxide is used to remove the molybdenum, the aluminum will not be oxidized.

Transparent conductive layer on aluminum, for example ITO (Ind
If nitric acid is used to remove molybdenum, the ITO film will only be removed and the aluminum will not be oxidized.

The thin film layer does not have to be metal; if an organic thin film such as polyimide resin is used, the first metal layer is aluminum coated with ITO, and fuming nitric acid is used to remove the polyimide resin. If used, there will be no problem, and there is considerable freedom in the combination of the thin film layer and the first metal layer. Since the first metal layer is exposed to the etching liquid or gas during the process of forming the openings in the second insulating layer, it is preferable that these etchings also be made of a material that does not lose its conductivity through dissolution or chemical reaction. The most suitable material is aluminum coated with molybdenum or ITO.

Effect of the invention The M according to the present invention shown in FIG. 4(d) and FIG. 6(d)
IS) Most transistors are single crystal silicon MO8)
Like a transistor, the source and drain are formed in a self-aligned manner. That is, the gate metal layer 2'
The end of the source/drain 1° and the end of the source/drain 11 are on the same straight line, and there is no planar overlap between these electrodes. This is because the source and drain are made of amorphous silicon containing impurities, and the formation method is lift-off using a gate pattern2.
2. This is because -. In the example of FIG. 4(f) of the present invention, in order to compensate for the imperfection of lift-off, the side surfaces of the gate metal layer 2' are slightly removed so as not to become an offset gate, and also in FIG. In this example, the third insulating layer 16' is deposited on the side surfaces of the gate metal layer 2', so that the insulation between the gate metal layer 2' and the source/drain 10.11 is extremely perfect. Therefore, the capacitance between the gate and the source and between the gate and the drain is reduced to about 10% compared to the conventional example shown in Figure 2(d), and when operating an amorphous silicon MIS transistor in pulse operation, restrictions have been significantly eased. Additionally, reliability has been dramatically improved because the amorphous silicon that makes up the channel does not come into contact with the outside air, unlike in conventional devices. Also, the number of masks required to manufacture MIS) transistors was the same as in the past, only four, and other excellent manufacturing advantages were obtained.

As is clear from the comparison between FIG. 2(e) and FIG. 4(θ), in the present invention, under the gate metal layer 2', there is always a gate insulating layer 3' and a non-containing non-impurity layer. Crystalline Shi237・
... Due to the presence of the silicon layer 4', the gate wiring 9 is likely to break off, but this can be avoided by forming the gate wiring 9 thickly, and this will improve the transistor characteristics, such as mutual conductance and threshold value. Although it cannot be said to be a drawback, it is necessary to be careful because the value does not change.

As is clear from the above description, the gist of the present invention is applicable to semiconductor materials other than single crystal silicon, that is, microcrystalline silicon and polycrystalline silicon, and the gist of the present invention is applicable to Needless to say, in addition to silicon nitride, silicon oxide, silicon carbide, or a mixture thereof may also be used for the insulating layer.

[Brief explanation of the drawing]

Figure 1 is a plan view of a MIS transistor with a conventional structure, and Figures 2 (a) to (d) are A-
The manufacturing process sectional view of the A' line part, Figure 2 (e) is the same (B
- A cross-sectional view of the line B/, FIG. 3 is a plan view of a MIS transistor according to an embodiment of the present invention, and FIGS. 4 (-) to (d)
is a cross-sectional view of the manufacturing process of the transistor in the line A-A' of FIG. 3, FIG. 5(a) to 5(d) are sectional views of the manufacturing process according to the embodiment, taken along the line A-A' according to another embodiment of the present invention. 1... Insulating substrate, 2, 2', 2 years...
Gate metal layer, 3, 3'...Gate insulating layer, 4
, 4'... Amorphous silicon layer containing no impurities, 5, 5'... Amorphous silicon layer containing impurities, 7, 8.9... Gate/drain/source wiring, 1o, 11... Source/drain, 13
, 13', thin film layer, 16... second insulating layer, 16, 16'... third insulating layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Fig. 4' Fig. 2 ta Fig. 2 (C) 1 (t≧() l Fig. 3 4' Fig. 4 ((1) rc Fig. 4 (O) Fig. 5 do a) 13'lb>1.9' Fig. 5 (C) 4 td)

Claims (1)

[Scope of Claims] (1) A first film containing silicon as a main component on an insulating substrate.
A non-single-crystal semiconductor layer is formed in an island shape, a laminated portion consisting of a first insulating layer and a gate metal layer is formed on a part of the first non-single-crystal semiconductor layer, and A second non-single crystal semiconductor layer formed on a region other than the first insulating layer on the single crystal semiconductor layer and containing silicon as a main component and an impurity serving as a donor or acceptor is used as a source/drain,
A gate metal wiring path and a source/drain metal wiring path are formed in the gate metal layer and the source/drain, respectively, through openings formed in a second insulating layer deposited on the entire surface. An insulated gate transistor characterized by: (2) A first non-single crystal semiconductor layer containing silicon as a main component is formed in an island shape on an insulating substrate, and a part of the first non-single crystal semiconductor layer is formed on the first non-single crystal semiconductor layer. A laminated portion is formed of a first insulating layer and a gate metal layer having a second insulating layer deposited on the side surface of the second page, and the first insulating layer on the first non-single crystal semiconductor layer is formed on the second insulating layer. A second layer containing silicon as a main component and an impurity serving as a donor or acceptor is formed on a region other than the
The non-single crystal semiconductor layer is used as a source/drain, and a gate metal wiring path and a source/drain are connected to the gate metal layer and the source/drain through openings formed in a third insulating layer deposited on the entire surface. An insulated gate transistor characterized in that a drain metal wiring path is formed. [3] First layer of silicon-based coating on an insulating substrate.
a step of sequentially forming a non-single-crystal semiconductor layer, a first insulating layer, a first metal layer, and a thin film layer; and selectively forming a laminated portion consisting of the thin film layer, the first metal layer, and the first insulating layer. a step of forming a second non-single crystal semiconductor layer containing silicon as a main component and an impurity serving as a donor or acceptor on the entire surface; 2. A step of forming a non-single crystal semiconductor layer in an island shape; 3. A step of selectively removing a second non-single crystal semiconductor layer on the thin film layer while removing the thin film layer; a second non-single crystal semiconductor layer having an opening on the layer and the second non-single crystal semiconductor layer;
forming an insulating layer over the entire surface, and forming a second insulating layer on the first metal layer and the second non-single crystal semiconductor layer through the opening.
selectively forming a metal layer. (4+ The insulation according to claim 3, wherein the first insulation layer is formed continuously without being exposed to the atmosphere after the formation of the first non-single crystal semiconductor layer. A method for manufacturing a gate type transistor. (6) The method of claim 3, characterized in that molybdenum is used for the first metal layer, aluminum is used for the thin film layer, and hot phosphoric acid is used for removing the aluminum. The method for manufacturing an insulated gate transistor according to item 6. (6) Aluminum is used for the first metal layer, molybdenum is used for the thin film layer, and water peroxide is used for removing the molybdenum. A method for manufacturing an insulated gate transistor according to claim 3. (7) Aluminum coated with a transparent conductive layer is used for the first metal layer, molybdenum is used for the thin film layer, and the first metal layer is made of aluminum coated with a transparent conductive layer. A method for manufacturing an insulated gate transistor according to claim 3, characterized in that a hydrogen peroxide solution or nitric acid is used to remove molybdenum. a step of sequentially forming a first non-single crystal semiconductor layer, a first insulating layer, a first metal layer and a thin film layer; a step of selectively leaving a second non-single crystal semiconductor layer containing silicon as a main component and an impurity serving as a donor or acceptor on the entire surface; a first non-single crystal semiconductor layer including the laminated portion; forming the second non-single crystal semiconductor layer in an island shape; removing a portion of the side surface of the first metal layer; and removing the thin film layer and forming the second non-single crystal semiconductor layer on the thin film layer. a step of selectively removing the semiconductor layer; a step of forming a second insulating layer having an opening over the metal layer of the fifth page 1 and the second non-single crystal semiconductor layer; A method for manufacturing an insulated gate transistor, comprising the step of selectively forming a second metal layer on the first metal layer and the second non-single crystal semiconductor layer through an opening. (9) First In the insulated gate transistor according to claim 8, the insulating layer is formed continuously without being exposed to the atmosphere after the formation of the first non-single crystal semiconductor layer. Manufacturing method: 01 The insulated gate according to claim 8, characterized in that molybdenum is used for the first metal layer, aluminum is used for the thin film layer, and hot phosphoric acid is used to remove the aluminum. (11) The first metal layer is made of aluminum, the thin film layer is made of molybdenum, and hydrogen peroxide is used to remove the molybdenum. 9. A method for manufacturing an insulated gate transistor according to item 8. Page 6 0 The first metal layer is made of aluminum coated with a transparent conductive layer, the thin film layer is made of molybdenum, and the molybdenum is removed using hydrogen peroxide or nitric acid. A method for manufacturing an insulated gate transistor according to claim 8. 03 Step of sequentially forming a first non-single-crystal semiconductor layer containing silicon as a main component, a first insulating layer, a first metal layer, and a thin film layer on an insulating substrate, and forming the thin film layer and the first metal layer in sequence. a step of selectively leaving a laminated portion consisting of layers; a step of forming a second insulating layer on the entire surface; and a step of forming the second insulating layer by anisotropic etching.
a step of removing the insulating layer and selectively leaving a second insulating layer on the side surface of the laminated portion; a step of selectively removing the first insulating layer using the laminated portion as a mask; and a step of selectively removing the first insulating layer using the laminated portion as a mask; forming a second non-single-crystalline semiconductor layer containing impurities that serve as donors or acceptors over the entire surface; a step of selectively removing a seven-purge second non-single crystal semiconductor layer on the thin film layer at the same time as removing the thin film layer; forming a third insulating layer having an opening over the entire surface of the crystalline semiconductor layer; and forming a second metal layer on the first metal layer and the second non-single crystal semiconductor layer through the opening. 1. A method for manufacturing an insulated gate transistor, the method comprising: selectively forming a transistor. 0荀 The insulation according to claim 13, wherein the first insulation layer is formed continuously without being exposed to the atmosphere after the formation of the first non-single crystal semiconductor layer. A method of manufacturing gated transistors. aF9 Manufacture of an insulated gate transistor according to claim 13, characterized in that molybdenum is used for the first metal layer, aluminum is used for the thin film layer, and hot phosphoric acid is used to remove the aluminum. Method. 0:00: Aluminum is used for the first metal layer, molybdenum is used for the thin film layer, and hydrogen peroxide solution is used to remove the molybdenum.
A method for manufacturing an insulated gate transistor according to section 1. αη The first metal layer is made of aluminum coated with a transparent conductive layer, the thin film layer is made of molybdenum, and hydrogen peroxide or nitric acid is used to remove the molybdenum. A method for manufacturing an insulated gate transistor according to Scope 13.