JPH01259565A - Thin film transistor and manufacture of the same - Google Patents
Thin film transistor and manufacture of the sameInfo
- Publication number
- JPH01259565A JPH01259565A JP8713788A JP8713788A JPH01259565A JP H01259565 A JPH01259565 A JP H01259565A JP 8713788 A JP8713788 A JP 8713788A JP 8713788 A JP8713788 A JP 8713788A JP H01259565 A JPH01259565 A JP H01259565A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- impurity
- film
- layer
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 103
- 239000012535 impurity Substances 0.000 claims abstract description 39
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 62
- 238000000151 deposition Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 230000002265 prevention Effects 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 102
- 238000005530 etching Methods 0.000 description 20
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 238000004544 sputter deposition Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 239000000243 solution Substances 0.000 description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 230000007423 decrease Effects 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 6
- KFZMGEQAYNKOFK-UHFFFAOYSA-N isopropyl alcohol Natural products CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- XMPZTFVPEKAKFH-UHFFFAOYSA-P ceric ammonium nitrate Chemical compound [NH4+].[NH4+].[Ce+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O XMPZTFVPEKAKFH-UHFFFAOYSA-P 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910017604 nitric acid Inorganic materials 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 229960000583 acetic acid Drugs 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012362 glacial acetic acid Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- NWZSZGALRFJKBT-KNIFDHDWSA-N (2s)-2,6-diaminohexanoic acid;(2s)-2-hydroxybutanedioic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O.NCCCC[C@H](N)C(O)=O NWZSZGALRFJKBT-KNIFDHDWSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- IKDUDTNKRLTJSI-UHFFFAOYSA-N hydrazine monohydrate Substances O.NN IKDUDTNKRLTJSI-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- QEMXHQIAXOOASZ-UHFFFAOYSA-N tetramethylammonium Chemical compound C[N+](C)(C)C QEMXHQIAXOOASZ-UHFFFAOYSA-N 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜トランジスタに係り、特にデイスプレィ用
に好適な非晶質シリコンを用いた薄膜トランジスタに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor, and particularly to a thin film transistor using amorphous silicon suitable for display use.
従来の非晶シリコン薄膜トランジスタは、特開昭５８−
２１９７６７号に記載のように、ゲート電極の幅よりも
半導体層の幅が広い構造を有していた。その製法につい
ては、不純物含有半導体層（ｎ十層）の不用部分をＨＦ
＋ＨＮＯδ系エツチング液により除去していた。この場
合の薄膜トランジスタ（以下ではＴＰＴと略す）を第２
図に示した。このＴＰＴを、例えば液晶デスプレイに用
いる場合には、画素電極（透明電極）を、第１及び第２
電極の少なくとも一方と電気的に結ぶことにより使用で
きる。Conventional amorphous silicon thin film transistor
As described in No. 219767, the semiconductor layer had a structure in which the width of the semiconductor layer was wider than the width of the gate electrode. Regarding its manufacturing method, the unnecessary part of the impurity-containing semiconductor layer (n10 layers) is
It was removed using +HNOδ etching solution. In this case, the thin film transistor (hereinafter abbreviated as TPT) is
Shown in the figure. When using this TPT for, for example, a liquid crystal display, pixel electrodes (transparent electrodes) are
It can be used by electrically connecting to at least one of the electrodes.
また、従来の他のａ −Ｓ ｉ Ｔ Ｆ Ｔは、基板の
上にゲート電極を形成し、その上に絶縁膜、非晶質シリ
コンを形成する。次に金属膜によりソース。In addition, in another conventional a-S i TFT, a gate electrode is formed on a substrate, and an insulating film and amorphous silicon are formed on the gate electrode. Next, source by metal film.
ドレイン電極を形成する。この構成において、活性層で
ある非晶質シリコンとソース、ドレイン電極の接触は不
純物含有半導体層を介して行なわれる。Form a drain electrode. In this configuration, contact between the amorphous silicon that is the active layer and the source and drain electrodes is made through the impurity-containing semiconductor layer.
上記従来の他のａ −Ｓ ｉ Ｔ Ｆ Ｔの構造断面図
を、第３図に示した。A cross-sectional view of the structure of the other conventional a-S i TFT mentioned above is shown in FIG.
上記従来技術は、外部光によって、オフ特性が劣化（オ
フ抵抗の低下）が生じるという問題があった。この解決
のためには、■半導体層の膜厚を極端に薄くする。■遮
光膜を完全にし、半導体層への光の進入を防ぐ、の二点
が考えられる。前者（１）の対策は、オフ抵抗の低下を
抑えはするが。The above-mentioned conventional technology has a problem in that the off-characteristic deteriorates (the off-resistance decreases) due to external light. To solve this problem, 1) the thickness of the semiconductor layer must be made extremely thin; Two possibilities are possible: 1. Complete the light-shielding film to prevent light from entering the semiconductor layer. Although the former measure (1) suppresses the decrease in off-resistance.
基本的に、光が入ることによる劣化は避けられない。一
方後老（２）の対策では、例えば特開昭６０−１７９６
２のごとく第３図に示した構造となり、上下方向の光を
完全に遮断し、光の進入によるオフ抵抗の低下は抑える
ことができる。しかし、同図の半導体層４と、その上部
の第１及び第２電極間に挿入されている不純物含有半導
体層（５） （ｎ中層）が、一部において不完全であ
る。すなわち、半導体層４の端部においては、半導体層
４と第１（６）及び第２（７）電極とが直接触れている
。このため、このＴＰＴでは、ｎ中層によるホール電流
の阻止が不完全となり、ゲート電圧が負になる程、オフ
抵抗は低下する。Basically, deterioration due to exposure to light is unavoidable. On the other hand, for measures against old age (2), for example,
2, the structure shown in FIG. 3 is obtained, and light in the vertical direction is completely blocked, and a decrease in off-resistance due to the entry of light can be suppressed. However, the semiconductor layer 4 in the same figure and the impurity-containing semiconductor layer (5) (n-middle layer) inserted between the first and second electrodes above it are partially incomplete. That is, at the ends of the semiconductor layer 4, the semiconductor layer 4 and the first (6) and second (7) electrodes are in direct contact. Therefore, in this TPT, blocking of hole current by the n-layer becomes incomplete, and the more negative the gate voltage becomes, the lower the off-resistance becomes.
また、第２図及び第３図の構造を得るには、半導体層（
４）上の不純物含有半導体層（５） （ｎ中層）を一
部、すなわち、第１（６）及び第２（７）画電極で挾持
された部分を除去する必要がある。この際、半導体層（
５）を腐蝕せずに、ｎ中層（５）を除去する必要がある
。そのための手段として、ドライエツチングでは１選択
比が大きく取れないため、無理がある。特に半導体層（
４）の膜厚が小さくなるに従い困難となる。一方、フッ
酸系エツチング液によれば１選択比は充分な大きさとな
り得る。その状況は特開昭５８−２１９７６７号に記載
されている通りである。しかしながら、フッ酸系エツチ
ング液では以下の点で不都合が生じた。■ｎ十中層エツ
チングのために用いるマスク（電極あるいはホトレジス
ト）の近傍で、その他の部分より速くエツチングが進行
し、半導体層（４）を深く腐蝕する。Moreover, in order to obtain the structures shown in FIGS. 2 and 3, a semiconductor layer (
4) It is necessary to remove a part of the upper impurity-containing semiconductor layer (5) (n middle layer), that is, the part held between the first (6) and second (7) picture electrodes. At this time, the semiconductor layer (
It is necessary to remove the n-middle layer (5) without corroding the n-layer (5). As a means for this purpose, dry etching is difficult because it does not allow a large selection ratio. Especially the semiconductor layer (
4) becomes more difficult as the film thickness becomes smaller. On the other hand, if a hydrofluoric acid-based etching solution is used, the selectivity of 1 can be sufficiently large. The situation is as described in JP-A-58-219767. However, the hydrofluoric acid etching solution has the following disadvantages. (2) Etching progresses faster in the vicinity of the mask (electrode or photoresist) used for etching the middle layer than in other parts, deeply corroding the semiconductor layer (4).
■半導体層（４）の一部（例え端部であろうとも）が露
出した状態（第２図、第３図では避けられない）では、
単層膜のｎ中層のエツチング速度が得られない。この理
由は、半導体層−エッチング液−不純物含有半導体層の
系で電池が生じ、ｎ中層表面に（−）の電荷が生じ、Ｆ
イオンの付着が妨げるためと推測された。■When a part of the semiconductor layer (4) (even the edge) is exposed (unavoidable in Figures 2 and 3),
The etching rate of the n-middle layer of a single layer film cannot be obtained. The reason for this is that a battery is generated in the system of semiconductor layer-etching solution-impurity-containing semiconductor layer, and a (-) charge is generated on the surface of the n-layer, and F
It was assumed that this was due to interference with ion adhesion.
本発明の目的は、■外部光によってオフ抵抗の低下しな
いＴＰＴを提供すること。■ホール電流をｎ中層で完全
に阻止したＴＰＴを提供すること、■ｎ十中層エツチン
グ時に、エツチング速度の不均一性を無くし、単層ｎ中
層膜と同等なエツチング速度でｎ中層を除去し、所望の
構造を有したＴＰＴを得ること、および■１−ａ−３ｉ
の側面にホール注入防止層をもうけてホール電流を阻止
するＴＰＴを提供することにある。The object of the present invention is (1) to provide a TPT whose off-resistance does not decrease due to external light. ■Providing a TPT in which the hole current is completely blocked in the n-middle layer; ■Eliminate the non-uniformity of the etching rate when etching the n-middle layer, and remove the n-middle layer at an etching rate equivalent to that of a single-layer n-middle layer film; Obtaining TPT with a desired structure, and ■1-a-3i
The object of the present invention is to provide a TPT which blocks hole current by forming a hole injection prevention layer on the side surface of the TPT.
上記目的は、半導体層を加工後、その端部（加工面）を
も含め、完全に不純物含有半導体（ｎ中層）で被うこと
、あるいは、半導体層の側面にホールを阻止する膜を形
成することと、ゲート電極の幅を半導体層の幅より大き
くすることにより達成される。The above purpose is to completely cover the semiconductor layer, including its edges (processed surface), with an impurity-containing semiconductor (n middle layer) after processing, or to form a film on the side surface of the semiconductor layer to block holes. This is achieved by making the width of the gate electrode larger than the width of the semiconductor layer.
〔作用〕
半導体層の端部も含め、ホール注入防止層あるいは不純
物含有半導体層で被うことにより、半導体層端部からの
ホール注入が阻止できる。また。[Function] Hole injection from the ends of the semiconductor layer can be prevented by covering the semiconductor layer including the ends with a hole injection prevention layer or an impurity-containing semiconductor layer. Also.
ｎ中層で完全に被っているため、電池ができないことか
ら、ｎ中層のエツチングは単層膜の場合と同じ速度でエ
ツチングは速行する。また、ゲートｉｔ電極の幅が、半
導体層の幅より大きいことで２ゲート側からの光に対し
ては、ゲート電極で遮光するため、外部光によるオフ抵
抗の低下が生じるこがない。Since it is completely covered by the n-middle layer, a battery cannot be formed, so the etching of the n-middle layer proceeds at the same rate as in the case of a single layer film. Further, since the width of the gate it electrode is larger than the width of the semiconductor layer, light from the second gate side is blocked by the gate electrode, so that the off-resistance does not decrease due to external light.
実施例１
以下本発明の一実施例を第１図および第４図により説明
する。第４図において、先ず基板（１）であるガラス板
上に、ゲート電極（２）を形成する。Example 1 An example of the present invention will be described below with reference to FIGS. 1 and 4. In FIG. 4, first, a gate electrode (2) is formed on a glass plate, which is a substrate (1).
これは、例えばスパッタ法によりＣｒを０．１μｍ堆積
後、通常のホトエツチング法によって所望の形状に加工
する。次に、ＣＶＤ法によって、ゲート絶ａｌｌＪ（３
）例えばシリコン窒化膜（ＳｉＮと表わす）を０．３μ
ｍ堆積後、続いて半導体層（４）例えば非晶質シリコン
膜を０．１μｍ堆積する。For example, Cr is deposited to a thickness of 0.1 .mu.m by sputtering, and then processed into a desired shape by ordinary photoetching. Next, by the CVD method, gate isolation allJ(3
) For example, a silicon nitride film (denoted as SiN) with a thickness of 0.3μ
After the deposition of 0.1 μm, a semiconductor layer (4) such as an amorphous silicon film is subsequently deposited to a thickness of 0.1 μm.
次に、ゲート電極の幅より小さくなるようにホトレジス
ト（１０１）を被せ、第４図（Ａ）の通りとする。次に
、ホトレジスト（１０１）をマスクとして半導体層（４
）を加工する。この加工にあたっては例えば、ヒドラジ
ン−水和物／イソプロピルアルコール／水＝１００１５
１５ （容量比）溶液を、５０℃とした中で、非晶質シ
リコンを加工する。その後、ＣＶＤ法によって、ＰＨｓ
と５ｉＨａガスを用いて、リンを不純物とした、不純物
含有半導体層（５） （ｎ中層）を膜厚５ ’Ｏｎ
ｍ堆積し、さらに、スパッタ法によって、例えばＣｒを
膜厚０．１μｍ、さらに続いてＡＱを膜厚０．４μｍ堆
積し、それぞれ、第１電極（６）、第２電極（７）を形
成し、これら電極を加工するためのマスクとして、ホト
レジスタ（１０２）を形成し第４図（Ｂ）の構造とする
。次に、ホトレジスト（１０２）をマスクとして、例え
ばリン酸／氷酢酸／硝酸／水＝７５／１５１５１５ （
容量比）溶液によってＡＱを加工後、１０％硝酸第二セ
リウムアンモニウム水溶液でＣｒを加工する。次いで、
フッ酸／硝酸／氷酢酸＝ １．５／６０／３８．５（容
量比）溶液によって不純物含有半導体層をエツチングす
る。ここで、不純物含有半導体層と半導体層とのエツチ
ング速度比は１０以上あり、半導体層はほとんど腐蝕さ
れない。また、不純物含有半導体層を、半導体層（４）
を加工後、堆積しているため、半導体層（４）は完全に
、不純物半導体層で被われており（第４図（Ｂ）におい
て明らかである）、マスク端部における異常反応、およ
び電池作用によるエツチング阻害作用は生じない。Next, a photoresist (101) is covered so that the width is smaller than the width of the gate electrode, as shown in FIG. 4(A). Next, using the photoresist (101) as a mask, the semiconductor layer (4) is
). For this processing, for example, hydrazine hydrate/isopropyl alcohol/water = 10015
15 (Volume ratio) Amorphous silicon is processed in a solution at 50°C. Then, by CVD method, PHs
and 5iHa gas to form an impurity-containing semiconductor layer (5) (n middle layer) with a film thickness of 5'On using phosphorus as an impurity.
Then, by sputtering, for example, Cr is deposited to a thickness of 0.1 μm, and then AQ is deposited to a thickness of 0.4 μm to form a first electrode (6) and a second electrode (7), respectively. A photoresist (102) is formed as a mask for processing these electrodes, resulting in the structure shown in FIG. 4(B). Next, using the photoresist (102) as a mask, for example, phosphoric acid/glacial acetic acid/nitric acid/water = 75/151515 (
Volume ratio) After processing AQ with a solution, Cr is processed with a 10% ceric ammonium nitrate aqueous solution. Then,
The impurity-containing semiconductor layer is etched with a solution of hydrofluoric acid/nitric acid/glacial acetic acid=1.5/60/38.5 (volume ratio). Here, the etching rate ratio between the impurity-containing semiconductor layer and the semiconductor layer is 10 or more, and the semiconductor layer is hardly corroded. Further, the impurity-containing semiconductor layer is formed into a semiconductor layer (4).
After processing, the semiconductor layer (4) is completely covered with the impurity semiconductor layer (as is clear in Fig. 4 (B)), which causes abnormal reactions at the edge of the mask and the battery operation. No etching inhibition effect occurs.
したがって、安定した不純物含有半導体層の加工ができ
る。その後、パッシベーション膜（８）としてＣＶＤ法
によってＳｉＮ膜を膜厚１μｍ堆積後、遮光１１！！
（９）例えばＡＱをスパッタ法によって膜厚０．５μｍ
堆積し、半導体層（４）の幅より広く加工し、第４図（
ｃ）の構造とする。以上の説明でＴＰＴの所望構造と、
その製造法は明らかであるが、このＴ Ｆ’ Ｔを例え
ば、液晶デイスプレィ用に供するには、透明電極による
画素電極を形成する必要がある。このためには、以上説
明した手順の中で、例えば半導体層（４）を加工後、透
明導電膜を堆積、加工する工程を加えることと、この透
明導電膜と第１及び第２電極とを接続することによって
第１図の構造は達成される。透明導電膜の有無に関わら
ず、以上の説明によって、作られたＴＰＴは、下部から
の入射光に対しては、幅の広いゲート電極によって遮光
し、上部からの入射光に対しては遮光膜（９）によって
遮断するため、光の入射により、ＴＰＴのオフ抵抗が低
下するという事は生じない。また、半導体層（４）と電
極（６）（７）との間には、半導体層（４）の端部（加
工端面）をも含め完全に不純物含有半導体層（５）を挿
入した構造としたことから、ホール注入を抑えることが
でき、ゲート電圧を負の大きな値としても、電流は低く
抑えることができる。Therefore, the impurity-containing semiconductor layer can be stably processed. After that, a 1 μm thick SiN film was deposited as a passivation film (8) by CVD method, and then a light shielding film (8) was deposited to a thickness of 1 μm. !
(9) For example, AQ is coated with a film thickness of 0.5 μm by sputtering.
The semiconductor layer (4) is deposited and processed to be wider than the width of the semiconductor layer (4).
The structure is c). In the above explanation, the desired structure of TPT,
Although the manufacturing method is clear, in order to use this T F' T for, for example, a liquid crystal display, it is necessary to form a pixel electrode using a transparent electrode. For this purpose, among the steps explained above, for example, after processing the semiconductor layer (4), a step of depositing and processing a transparent conductive film is added, and this transparent conductive film and the first and second electrodes are connected. By connecting, the structure of FIG. 1 is achieved. Regardless of the presence or absence of a transparent conductive film, the TPT made according to the above explanation blocks light incident from the bottom with a wide gate electrode, and blocks light incident from the top with a light shielding film. Since the light is blocked by (9), the off-resistance of the TPT does not decrease due to the incidence of light. In addition, the impurity-containing semiconductor layer (5) is completely inserted between the semiconductor layer (4) and the electrodes (6) and (7), including the edges (processed end surfaces) of the semiconductor layer (4). Therefore, hole injection can be suppressed, and even if the gate voltage is set to a large negative value, the current can be kept low.
実施例２
本発明による別の実施例を第５図によって説明する。先
ず同図（Ａ）の構造を得る。そのため、基板（１）上に
例えばＣｒを膜厚０．１３μｍＭ！ＶＣ後、加工し、ゲ
ート電極（２）を形成する。次に、ＣＶＤ法によって、
ゲート絶縁［（３） 、半導体層（４）を、例えば、Ｓ
ｉＮを膜厚０．２５μｍ 、非晶質Ｓｉ （ａ Ｓｉ
）を膜厚０．１３μｍＪＧ：積して形成する。さらに、
ａ −Ｓ ｉ膜を、例えば２％テトラメチルアンモニウ
ム水溶液に５％のイソプロピルアルコールを添加した溶
液を６０”Ｃとした中で、ホトレジスト（例えばＯＭＲ
−８３）をマスフとして加工する。次に、ＣＶＤ法によ
って、リンを不純物とした。不純物含有半導体層（５）
を膜厚４０ｎｍ堆積する。この上にホトレジスト（例え
ば０ＦＰＲ−８００）をマスクとして、フッ酸：硝酸：
酢Ｍ：過酸化水素水＝１ ： ６０ ：２９ ： １０
をエツチング液として、不純物含有半導体層（５）
（ｎ中層）を加工する。ここで、ｎ÷層は、ａ −Ｓ
ｉ表面及び端面をも被っているため。Example 2 Another example according to the present invention will be described with reference to FIG. First, the structure shown in FIG. 3(A) is obtained. Therefore, for example, Cr is coated on the substrate (1) with a thickness of 0.13 μm! After VC, processing is performed to form a gate electrode (2). Next, by CVD method,
Gate insulation [(3), semiconductor layer (4), for example, S
iN with a film thickness of 0.25 μm and amorphous Si (a Si
) are stacked to a film thickness of 0.13 μm. moreover,
The a-S i film is coated with a photoresist (e.g. OMR) in a solution prepared by adding 5% isopropyl alcohol to a 2% tetramethylammonium aqueous solution at 60"C.
-83) is processed as a mass. Next, phosphorus was added as an impurity using the CVD method. Impurity-containing semiconductor layer (5)
is deposited to a thickness of 40 nm. On top of this, a photoresist (for example, 0FPR-800) is used as a mask, and hydrofluoric acid: nitric acid:
Vinegar M:Hydrogen peroxide solution=1:60:29:10
as an etching solution, the impurity-containing semiconductor layer (5)
(n middle layer) is processed. Here, n÷ layer is a − S
i Because it also covers the surface and end face.
エツチング液中で電池は生じることがない、また単層膜
によるｎ中層のエツチング速度とａ−５ｉのエツチング
速度の比は２０以上である。したがってこの速度差によ
って、不純物含有半導体層（５）は加工され、また半導
体層（４）はほとんど腐蝕することはない。次に、Ｃｒ
ｆａ−膜厚５０ｎｍ、ＡＩ２を膜厚０．５μｍ それ
ぞれスパッタ法によって堆積する。次にホトレジストを
マスクとしてＡＱを加工し、第２電極（７）を形成後、
ホトレジストを被せ直し、Ｃｒを加工して第１電極（６
）を形成して、第５図（Ａ）の構造を得る。次に、スパ
ッタ法によりＩＴＯ（インジウムとスズの酸化物）を膜
厚０，１μｍ堆積する。次にホトレジストをマスクとし
て、塩酸：硝酸：水＝１：６：３溶液によって、ＩＴＯ
を加工し、画素ｆｉｔ 極（１０）を形成して、第５図
（Ｂ）とする。次に、ＣＶＤ法によって、膜厚１．２μ
ｍのＳｉＮを堆積して、パッシベーション膜（８）を形
成する。次に、スパッタ法によって、ＡＱを膜厚１μｍ
堆積後、加工して、遮光膜（９）を形成し、第５図（Ｃ
）を得る。Cells do not form in the etching solution, and the ratio of the etching rate of the n middle layer of the single layer film to the etching rate of a-5i is 20 or more. Therefore, due to this speed difference, the impurity-containing semiconductor layer (5) is processed, and the semiconductor layer (4) is hardly corroded. Next, Cr
Fa film is deposited to a thickness of 50 nm, and AI2 is deposited to a film thickness of 0.5 μm by sputtering. Next, the AQ is processed using the photoresist as a mask, and after forming the second electrode (7),
Recover the photoresist and process the Cr to make the first electrode (6
) to obtain the structure shown in FIG. 5(A). Next, ITO (indium and tin oxide) is deposited to a thickness of 0.1 μm by sputtering. Next, using a photoresist as a mask, ITO was removed using a solution of hydrochloric acid: nitric acid: water = 1:6:3.
is processed to form a pixel fit pole (10), as shown in FIG. 5(B). Next, a film with a thickness of 1.2μ was formed using the CVD method.
m of SiN is deposited to form a passivation film (8). Next, AQ was applied to a film thickness of 1 μm by sputtering.
After deposition, processing is performed to form a light shielding film (9), as shown in FIG.
).
この例では、実施例１と同じく、ゲート電極（２）上の
半導体層（４）（ゲート電極幅より半導体層の幅は小さ
い）の端部は、不純物含有半導体層（５）で被われてお
り、第１及び第２電極と半導体層との間には、どの部位
においても、不純物含有半導体を挾んだ構造となる。た
だし、この例でのチャネル長は、不純物含有半導体層で
挾持された部分の長さとなる。この構造でも、上下両方
向からの光は、ゲート電極（２）と遮光膜（９）によっ
て半導体層（４）へ入射することはなく、光によるオフ
特性の劣化は生じない。また、半導体層（４）の端部を
も、不純物含有半導体層（５）によって被っているため
、ホール注入を阻止し、良好なオフ特性を有したＴＰＴ
を得ることができる。In this example, as in Example 1, the end of the semiconductor layer (4) on the gate electrode (2) (the width of the semiconductor layer is smaller than the width of the gate electrode) is covered with the impurity-containing semiconductor layer (5). Therefore, the impurity-containing semiconductor is sandwiched between the first and second electrodes and the semiconductor layer at any location. However, the channel length in this example is the length of the portion sandwiched between the impurity-containing semiconductor layers. Even in this structure, light from both the upper and lower directions is prevented from entering the semiconductor layer (4) by the gate electrode (2) and the light shielding film (9), and the off-characteristics are not deteriorated by light. In addition, since the end of the semiconductor layer (4) is also covered with the impurity-containing semiconductor layer (5), hole injection is prevented and the TPT has good off-characteristics.
can be obtained.
実施例３
次なる実施例を第６図によって説明する。基板（１）と
して板ガラス上に、スパッタ法によって、膜厚０．１５
μｍのＣｒを堆積し、これを通常のホトエツチング法に
よって加工して、ゲート電極（２）を形成する。次に、
ＣＶＤ法によって膜厚０．２５μｍのＳｉＮ膜を堆積し
てゲート絶縁膜（３）を形成後、引き続いて、ＣＶＤ法
によって、非品膜５ｉ（ａ−８ｉ）膜を膜厚０．１μｍ
堆積する。これを、ホトレジストをマスクとして、例え
ば、ＳＦｓとＣ（、Ｑａとの混合ガス雰囲気中で、高周
波高電圧を印加する通常のドライエツチング法により、
非晶質Ｓｉを加工して半導体層（４）を形成する。次に
、ＣＶＤ法によって、リンと不純物とした非晶質Ｓｉを
膜厚５０ｎｍ堆積する。次にホトレジストをマスクとし
て、実施例２と同様に不純物含有半導体層（５）を加工
形成する。さらに、スパッタ法により、ＩＴＯを膜厚０
．１μｍ堆積後、通常のホトエツチング法によって加工
し、画素電極（１０）を形成して、第６図（Ａ）とする
。Example 3 The next example will be explained with reference to FIG. A film with a thickness of 0.15 was deposited on a plate glass as a substrate (1) by sputtering.
A gate electrode (2) is formed by depositing Cr with a thickness of .mu.m and processing it by a normal photoetching method. next,
After forming a gate insulating film (3) by depositing a SiN film with a thickness of 0.25 μm using the CVD method, a non-quality film 5i (a-8i) film with a thickness of 0.1 μm is subsequently deposited using the CVD method.
accumulate. Using a photoresist as a mask, this is etched by a normal dry etching method in which a high frequency and high voltage is applied in a mixed gas atmosphere of SFs and C (and Qa).
A semiconductor layer (4) is formed by processing amorphous Si. Next, amorphous Si containing phosphorus and impurities is deposited to a thickness of 50 nm by CVD. Next, using a photoresist as a mask, an impurity-containing semiconductor layer (5) is formed in the same manner as in Example 2. Furthermore, by sputtering, ITO was deposited to a film thickness of 0.
．． After depositing 1 μm, it is processed by a normal photoetching method to form a pixel electrode (10) as shown in FIG. 6(A).
次にスパッタ法によって、膜厚０．１μｍのＣｒを堆積
後、通常のホトエツチング法により加工し、第１電極（
６）を形成する。さらに、同じくスパッタ法によって、
膜厚０．４μｍのＡＱを堆積後、ホトエツチング法によ
って加工し、第２電極（７）を形成して、第６図（Ｂ）
とする。次に、通常のＣＶＤ法によって膜厚０．８μｍ
のＳ ｘ Ｎ膜を堆積してパッシベーション（８）を形
成する。次いでスパッタ法により膜厚０．８μｍのＡｆ
ｌを堆積後、通常のホトエツチング法により加工して、
遮光膜（９）を形成し、第６図（Ｃ）に示した画素電極
を有したＴＰＴを得る。この例でも、半導体層（４）を
ゲート電極（２）の幅より小さく加工した後、企画に、
不純物含有半導体層（５）を被せるため、不純物含有半
導体層の加工は容易であり、この時、半導体層（４）は
ほとんど腐蝕されないという利点がある。さらに、半導
体層（４）がゲート電極（２）より小さいため、半導体
Ｗ（４）のすべてがチャネルどなる。この場合、ホール
チャネルも同様にできるが１本実施例では、第１電極（
６）及び第２電極（７）と半導体層（４）との間に、半
導体層（４）の加工面１表面ともに、不純物含有半導体
層（５）が挿入されている。したがってホールによるオ
フ時の電流増加を抑えることができた。また外部光によ
ってオフ抵抗が低下しない良好な”１” Ｆ Ｔを得る
ことができる。Next, after depositing Cr with a thickness of 0.1 μm by sputtering, it is processed by normal photoetching to form the first electrode (
6) Form. Furthermore, by the same sputtering method,
After depositing AQ with a thickness of 0.4 μm, it is processed by photoetching to form a second electrode (7), as shown in FIG. 6(B).
shall be. Next, a film with a thickness of 0.8 μm was formed using the normal CVD method.
A passivation (8) is formed by depositing an S x N film. Next, a film of Af with a thickness of 0.8 μm was formed by sputtering.
After depositing l, it is processed by the usual photoetching method,
A light shielding film (9) is formed to obtain a TPT having a pixel electrode as shown in FIG. 6(C). In this example as well, after processing the semiconductor layer (4) to be smaller than the width of the gate electrode (2), according to the plan,
Since the impurity-containing semiconductor layer (5) is covered, processing of the impurity-containing semiconductor layer is easy, and at this time, there is an advantage that the semiconductor layer (4) is hardly corroded. Furthermore, since the semiconductor layer (4) is smaller than the gate electrode (2), all of the semiconductor W (4) becomes a channel. In this case, the hole channel can be formed in the same way, but in this embodiment, the first electrode (
6), an impurity-containing semiconductor layer (5) is inserted between the second electrode (7) and the semiconductor layer (4), both on the processed surface 1 of the semiconductor layer (4). Therefore, it was possible to suppress the increase in current during off-time due to holes. Further, it is possible to obtain a good "1" F T whose off-resistance does not decrease due to external light.
実施例４ 本発明の第４の実施例を第７図により説明する。Example 4 A fourth embodiment of the present invention will be described with reference to FIG.
第７図は本発明のプロセス工程を示す図である。FIG. 7 is a diagram showing the process steps of the present invention.
ガラス基板（１）上に例えばＣｒ膜によりゲート電極（
１０）を形成し、その上に、ゲート絶縁膜（３）をＣＶ
Ｄ法によって、ＳｉＮを３００ｎｍ堆積後、引き続いて
、半導体Ｎ（４）を例えば、同じ＜ ＣＶＤ法により膜
厚１１００ｎのａ−ｓｉｗＡを堆積し、さらに、不純物
含有半導体層（５）をＣＶＤ法により、膜厚４０ｎｍで
リンが２％含まれたａ −Ｓ ｉ膜を堆積し、第７図（
Ａ）のごとく形成する。同図ＣＢ）は前記連続形成した
膜上に保護膜（１１）としてＣｒ膜を蒸着又はスパッタ
リングにより形成した状態である。同図（Ｃ）はＣｒを
パターン化後、トライエツチング法等によって不純物含
有半導体層（５）及び半導体層（４）をエツチングし加
工した状態である。使用するガスはＣＦ４．ＳＦｅを主
体としたものである。ＳｉＮ膜とａ−８ｉ膜との選択性
を向上させるためＳ Ｆ ｓ ＋ ＣＣＱ ４の混合ガ
スを使用する事もある。同図（Ｄ）は前記（Ｃ）の状態
で０２プラズ処理を行なった状態である。この時、ｎ中
層の表面はＣｒ膜でカバーされているので表面に酸化膜
が形成されることはない。しかし半導体層（４）及び、
不純物含有半導体層（５）の側面は保護膜（１１）のカ
バーがないので０２イオンにより表面にＳｉの酸化層が
形成され、これが、ホール注入防止層（１２）となる。For example, a gate electrode (
10) is formed, and a gate insulating film (3) is formed on it by CV
After depositing SiN to a thickness of 300 nm by the D method, the semiconductor N (4) is deposited, for example, by the same CVD method to deposit a-siwA with a thickness of 1100 nm, and then the impurity-containing semiconductor layer (5) is deposited by the CVD method. , an a-Si film containing 2% phosphorus was deposited to a thickness of 40 nm, as shown in Fig. 7 (
Form as shown in A). CB) in the same figure shows a state in which a Cr film is formed as a protective film (11) on the continuously formed films by vapor deposition or sputtering. Figure (C) shows a state in which after patterning Cr, the impurity-containing semiconductor layer (5) and the semiconductor layer (4) are etched and processed by a tri-etching method or the like. The gas used is CF4. It is mainly made of SFe. A mixed gas of SF s + CCQ 4 may be used to improve the selectivity between the SiN film and the a-8i film. Figure (D) shows the state in which the 02 plasma treatment was performed in the state of (C). At this time, since the surface of the n-layer is covered with the Cr film, no oxide film is formed on the surface. However, the semiconductor layer (4) and
Since the side surfaces of the impurity-containing semiconductor layer (5) are not covered by the protective film (11), an oxidized layer of Si is formed on the surface by the 02 ions, and this becomes a hole injection prevention layer (12).
この０２プラズマ処理を行なう時は、保護膜（１１）上
のホトレジマスクを除去する方が望ましい。これは０２
プラズマにより、ホトレジストが分解され有機物となっ
て基板上の部分に再付着する事が防ぐためである。０２
プラズマの条件は、ガス圧０．５〜２ 、 ＯＴｏｒｒ
、ＲＦｐｏｗｅｒ ２００ Ｗ、６０秒で行なう。When performing this 02 plasma treatment, it is preferable to remove the photoresist mask on the protective film (11). This is 02
This is to prevent the photoresist from being decomposed by the plasma, turning into organic matter, and re-adhering to the portion on the substrate. 02
The plasma conditions are gas pressure 0.5-2, OTorr.
, RF power 200 W, 60 seconds.
０２プラズマの条件はこの範囲に限定されるものではな
く、強いＳｉの酸化膜が生成できるほど良い６次に同図
（Ｅ）では、まず保護膜（１１）を硝酸第２セリウムア
ンモニウム水溶液でエツチング除去した。これはＯｚプ
ラズマ処理で表面酸化したＣｒは接触抵抗値が大きくな
るので除去するものである。その後第１電極（６）及び
第２電極（７）を、例えば各々、ＣｒとＡＱを蒸着又は
スパッタリングにより堆積し、トランジスタのソース、
及びドレイン電極を形成する。この状態においてチャネ
ル部分に相当する上部の不純物含有半導体層（５）をド
ライエツチング等により除去する。ここでドライエツチ
ングに使用するガスはＣＦ４．ＳＦ６を主体とするガス
で行ない、このガスに０２やＣＣＱ ４ガスを混入して
も良い。このようにして得たＴＰＴは、第８図の実線で
示したごとく、良好なオフ特性を示した。また同図には
、比較のため、従来のＴＰＴでの特性を点線により併記
した。02 The plasma conditions are not limited to this range, but the better the stronger the Si oxide film can be formed, the better. 6 Next, in the same figure (E), the protective film (11) is first etched with a ceric ammonium nitrate aqueous solution. Removed. This is because Cr whose surface is oxidized by the Oz plasma treatment increases the contact resistance value, so it is removed. Thereafter, a first electrode (6) and a second electrode (7) are deposited, for example by evaporation or sputtering, of Cr and AQ, respectively, and the source of the transistor,
and form a drain electrode. In this state, the upper impurity-containing semiconductor layer (5) corresponding to the channel portion is removed by dry etching or the like. The gas used for dry etching here is CF4. This may be carried out using a gas mainly composed of SF6, and 02 or CCQ4 gas may be mixed into this gas. The thus obtained TPT exhibited good off-characteristics, as shown by the solid line in FIG. In addition, in the figure, for comparison, the characteristics of the conventional TPT are also indicated by dotted lines.
この図より１本発明による’Ｉ’ Ｆ Ｔが優れている
ことがよく理解される。From this figure, it is clearly understood that the 'I' F T according to the present invention is superior.
本発明によれば、ホール注入によるオフ電流の増加が抑
えられるとともに、光によるオフ抵抗の低下がないため
、良好なオフ特性を有したＴＰＴを得ることができると
いう効果がある。According to the present invention, an increase in off-state current due to hole injection is suppressed, and there is no decrease in off-resistance due to light, so that a TPT with good off-state characteristics can be obtained.
また、エツチング液中での電池作用による異常なエツチ
ング現象は起らず、半導体層表面の腐蝕はほとんどなく
、不純物含有半導体層を加工することができるという効
果がある。Further, there is no abnormal etching phenomenon due to battery action in the etching solution, there is almost no corrosion on the surface of the semiconductor layer, and there is an effect that impurity-containing semiconductor layers can be processed.
第１図は本発明の第１の実施例のＴＰＴ断面図、第２図
は従来のＴＰＴ断面図、第３図は他の従来のＴＰＴの断
面図、第４図は本発明の第１の実施例のＴＰＴ製造工程
断面図、第５図は本発明の第２の実施例のＴＰＴ製造工
程断面図、第６図は本発明の第３の実施例のＴＰＴ製造
工程断面図、第７図は本発明の第４の実施例のＴＰＴ製
造工程断面図、第８図は本発明の効果を示すＴＰＴの特
性測定例である。
１・・・基板、２・・・ゲート電極、３・・・ゲート絶
縁膜、４・・・半導体層、５・・・不純物含有半導体層
、６・・・第１電！、７・・・第２電極、８・・・パッ
シベーション膜、９・・・遮光膜、１０・・・画素電極
、１０１・・・ホトレジスト、１０２・・・ホトレジス
ト、１１・・・保護膜、１２・・・ホール注入防止層。
と（〜FIG. 1 is a sectional view of a TPT according to the first embodiment of the present invention, FIG. 2 is a sectional view of a conventional TPT, FIG. 3 is a sectional view of another conventional TPT, and FIG. 5 is a sectional view of the TPT manufacturing process of the second embodiment of the present invention, FIG. 6 is a sectional view of the TPT manufacturing process of the third embodiment of the present invention, and FIG. 7 is a sectional view of the TPT manufacturing process of the third embodiment of the present invention. 8 is a sectional view of the TPT manufacturing process according to the fourth embodiment of the present invention, and FIG. 8 is an example of measuring the characteristics of TPT showing the effects of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Gate electrode, 3... Gate insulating film, 4... Semiconductor layer, 5... Impurity-containing semiconductor layer, 6... First electrode! , 7... Second electrode, 8... Passivation film, 9... Light shielding film, 10... Pixel electrode, 101... Photoresist, 102... Photoresist, 11... Protective film, 12 ...Hole injection prevention layer. and(~
Claims (1)
半導体層、および上記半導体層の両側の電極を有する薄
膜トランジスタにおいて、ゲート絶縁膜の幅よりも半導
体層の幅が狭く、半導体層上の両側の電極が、半導体層
の端面及び表面において、不純物含有半導体層を介して
上記半導体層と接続されて成ることを特徴とした薄膜ト
ランジスタ。 ２、基板上に、少なくともゲート電極とゲート絶縁膜、
半導体層、および上記半導体層の両側の電極を有する薄
膜トランジスタにおいて、半導体層を加工後不純物含有
半導体層を堆積した後、この不純物含有半導体層を加工
することを特徴とする薄膜トランジスタの製造方法。 ３、基板上に、少なくともゲート電極、ゲート絶縁膜、
半導体層、および上記半導体層の両側の電極を有する薄
膜トランジスタにおいて、上記半導体層の側面にホール
注入防止層を設けたことを特徴とする薄膜トランジスタ
。 ４、上記ホール注入防止層が、上記半導体層の酸化膜で
あることを特徴とする特許請求の範囲第１項記載の薄膜
トランジスタ。[Claims] 1. On the substrate, at least a gate electrode, a gate insulating film,
In a thin film transistor having a semiconductor layer and electrodes on both sides of the semiconductor layer, the width of the semiconductor layer is narrower than the width of the gate insulating film, and the electrodes on both sides of the semiconductor layer are connected to the impurity-containing semiconductor at the end face and surface of the semiconductor layer. A thin film transistor characterized in that it is connected to the semiconductor layer through a layer. 2. At least a gate electrode and a gate insulating film on the substrate,
A method for manufacturing a thin film transistor comprising a semiconductor layer and electrodes on both sides of the semiconductor layer, which comprises processing the semiconductor layer, depositing an impurity-containing semiconductor layer, and then processing the impurity-containing semiconductor layer. 3. On the substrate, at least a gate electrode, a gate insulating film,
1. A thin film transistor having a semiconductor layer and electrodes on both sides of the semiconductor layer, characterized in that a hole injection prevention layer is provided on a side surface of the semiconductor layer. 4. The thin film transistor according to claim 1, wherein the hole injection prevention layer is an oxide film of the semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8713788A JPH01259565A (en) | 1988-04-11 | 1988-04-11 | Thin film transistor and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8713788A JPH01259565A (en) | 1988-04-11 | 1988-04-11 | Thin film transistor and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01259565A true JPH01259565A (en) | 1989-10-17 |
Family
ID=13906580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8713788A Pending JPH01259565A (en) | 1988-04-11 | 1988-04-11 | Thin film transistor and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01259565A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0243739A (en) * | 1988-08-04 | 1990-02-14 | Sanyo Electric Co Ltd | Thin film transistor |
| US5187551A (en) * | 1988-04-30 | 1993-02-16 | Sharp Kabushiki Kaisha | Thin film semiconductor device and liquid crystal display apparatus thereof for preventing irradiated light from reaching the semiconductor layers |
| US5233211A (en) * | 1990-10-16 | 1993-08-03 | Agency Of Industrial Science And Technology | Semiconductor device for driving a light valve |
| JP2006243344A (en) * | 2005-03-03 | 2006-09-14 | Sharp Corp | Manufacturing method for liquid crystal display device |
| JP2007199188A (en) * | 2006-01-24 | 2007-08-09 | Seiko Epson Corp | Electrooptical apparatus and method for manufacturing the same, and electronic equipment |
| US7413940B2 (en) * | 2006-05-18 | 2008-08-19 | Au Optronics Corp. | Thin-film transistor and fabrication method thereof |
| JP2011155256A (en) * | 2009-12-28 | 2011-08-11 | Semiconductor Energy Lab Co Ltd | Thin-film transistor |
| JP2012094851A (en) * | 2010-10-01 | 2012-05-17 | Semiconductor Energy Lab Co Ltd | Manufacturing method for transistor |
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| JPS56135968A (en) * | 1980-03-27 | 1981-10-23 | Canon Inc | Amorphous silicon thin film transistor and manufacture thereof |
| JPS60206174A (en) * | 1984-03-30 | 1985-10-17 | Seiko Instr & Electronics Ltd | Thin-film transistor |
| JPS61145867A (en) * | 1984-12-20 | 1986-07-03 | Canon Inc | Matrix-type thin film transistor substrate |
| JPS62126677A (en) * | 1985-11-27 | 1987-06-08 | Sharp Corp | Thin film transistor array |
| JPS62131578A (en) * | 1985-12-03 | 1987-06-13 | Seiko Instr & Electronics Ltd | Manufacture of thin film transistor |
| JPH01191479A (en) * | 1988-01-27 | 1989-08-01 | Toshiba Corp | Thin film semiconductor element |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56135968A (en) * | 1980-03-27 | 1981-10-23 | Canon Inc | Amorphous silicon thin film transistor and manufacture thereof |
| JPS60206174A (en) * | 1984-03-30 | 1985-10-17 | Seiko Instr & Electronics Ltd | Thin-film transistor |
| JPS61145867A (en) * | 1984-12-20 | 1986-07-03 | Canon Inc | Matrix-type thin film transistor substrate |
| JPS62126677A (en) * | 1985-11-27 | 1987-06-08 | Sharp Corp | Thin film transistor array |
| JPS62131578A (en) * | 1985-12-03 | 1987-06-13 | Seiko Instr & Electronics Ltd | Manufacture of thin film transistor |
| JPH01191479A (en) * | 1988-01-27 | 1989-08-01 | Toshiba Corp | Thin film semiconductor element |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5187551A (en) * | 1988-04-30 | 1993-02-16 | Sharp Kabushiki Kaisha | Thin film semiconductor device and liquid crystal display apparatus thereof for preventing irradiated light from reaching the semiconductor layers |
| JPH0243739A (en) * | 1988-08-04 | 1990-02-14 | Sanyo Electric Co Ltd | Thin film transistor |
| US5233211A (en) * | 1990-10-16 | 1993-08-03 | Agency Of Industrial Science And Technology | Semiconductor device for driving a light valve |
| US5759878A (en) * | 1990-10-16 | 1998-06-02 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having epitaxially grown semiconductor single crystal film |
| US5926699A (en) * | 1990-10-16 | 1999-07-20 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having stacked layer substrate |
| USRE36836E (en) * | 1990-10-16 | 2000-08-29 | Agency Of Industrial Science And Technology | Semiconductor device for driving a light valve |
| JP2006243344A (en) * | 2005-03-03 | 2006-09-14 | Sharp Corp | Manufacturing method for liquid crystal display device |
| US7727822B2 (en) | 2005-03-03 | 2010-06-01 | Sharp Kabushiki Kaisha | Active matrix substrate and liquid crystal display device, production methods thereof and electronic device |
| JP4579012B2 (en) * | 2005-03-03 | 2010-11-10 | シャープ株式会社 | Manufacturing method of liquid crystal display device |
| JP2007199188A (en) * | 2006-01-24 | 2007-08-09 | Seiko Epson Corp | Electrooptical apparatus and method for manufacturing the same, and electronic equipment |
| US7413940B2 (en) * | 2006-05-18 | 2008-08-19 | Au Optronics Corp. | Thin-film transistor and fabrication method thereof |
| US7679088B2 (en) | 2006-05-18 | 2010-03-16 | Au Optronics Corp. | Thin-film transistor and fabrication method thereof |
| JP2011155256A (en) * | 2009-12-28 | 2011-08-11 | Semiconductor Energy Lab Co Ltd | Thin-film transistor |
| JP2012094851A (en) * | 2010-10-01 | 2012-05-17 | Semiconductor Energy Lab Co Ltd | Manufacturing method for transistor |
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