JPS5948960A - Manufacture of insulated gate type transistor - Google Patents

Abstract

PURPOSE:To prevent the poor ohmic contact of the subject transistor by a method wherein an insulating layer, with which a channel part is shielded from the outside air, is provided and after an aperture has been formed and an etching has been performed in vapor phase, an N type amorphous Si is coated on the above without exposing to a contaminated atmosphere. CONSTITUTION:A gate metal layer 2 is formed on an insulating substrate 1, and an insulating layer 3, an amorphous Si 4 containing no additive and an insulating layer 13 are laminated in the same chamber without exposing to the air. An aperture 14 is provided overlapping on a gate layer 2, and immediately after a plasma etching has been performed on the surface of the amorphous Si 4 using raw gas having SiF4 and the like as a main component, an N type amorphous Si 5' is coated on the above. Then, island-like layers 4' and 5' are formed by selectively removing the layers 4, 5 and 13 successively. After a window has been provided on the layer 3, a metal layer is coated on the whole surface, and a gate wiring 9 is selectively formed on source and drain wirings 7 and 8 and the insulating layer 3. Lastly, the N type amorphous Si 5' located on the insulating layer 13' is removed using the wirings 7 and 8 as a mask, and an MISFET is completed. According to this constitution, no thinning off is generated on the channel part and the source and drain electrode can be completely ohmic contacted, thereby enabling to obtain a highly reliable device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device,
1 concerning a thin film field effect transistor using an I:4 semiconductor as an active region.

The problem with the conventional configuration is I. Amorphous q]1 silicon, which is formed by including several atoms of hydrogen during the &11 formation, is formed at a low temperature y[7 formation. J111 is attracting attention as a low-cost solar streetcar due to the fact that it can be easily made into a large area and can be made into a large area1. However, compared to single crystal silicon, the free electron mobility is 0.1 ~ 'CnVY @S[
Semiconductors that are three orders of magnitude smaller than ICs and have performance worthy of integration.
1p-L+4 not obtained. Even so, it is possible to obtain a switching array of MIS transistors that does not require high-speed operation or large current, and which constitutes an image display device by combining them with, for example, a liquid crystal cell.

Figures 1 and 2 are plan views of an amorphous silicon MIS transistor developed to achieve the above objectives, A-A.
It is a process cross-sectional view on the ' line. First, as shown in FIG. 2a, a first metal layer 2, which will become a gate electrode, is selectively deposited on an insulating substrate, for example, a glass plate 1. As shown in FIG. Next, the entire surface is covered with a goo 1 insulating layer 3. an amorphous silicon layer containing no impurities 4.
Then, an amorphous silicon layer 5 containing impurities is coated. In these deposition methods, plasma deposition using glow discharge of a silane gas is simple, and it is possible to form a silicon layer 5 on the gate insulating layer 3. If this is the case, then ammonia I1 may be added, and if amorphous silicon containing significant impurities is to be obtained, diborane or phosphine may be added.

Thereafter, as shown in FIG. 2, the amorphous silicon layer 4.5 is selectively removed to form an island-shaped amorphous silicon layer 4/,
Form 5/. Further, although not shown in FIG. 2, an opening 6 (shown in FIG. 1) is formed in the gate insulating layer 3 on the first metal layer 2 to partially expose the first metal layer 2. In Fig. 2C, the onset gate is partially overlapped with the first gold strip layer 2 to prevent the structure from collapsing, and a pair of sources and drains made of the second metal layer are formed. Wirings 7 and 8 are selectively deposited. Of course, at this time, the opening 1] section 6
A gate wiring 9 made of a second metal layer is also formed on the gate insulating layer 3. Finally, in Figure 2 d, there is C.
), using the source/drain wirings 7 and 8 as a mask, remove impurity-free crystal III (silicon layer 4'1- impurity-containing amorphous silicon: 17 layer 6', f; (l) With this structure, an amorphous silicon MIS type transistor is completed.

Amorphous Ie "silicon layer 10" containing impurities interposed between source/drain wirings 7 and 8 and amorphous silicon layer 4'
．． 11 is necessary to form a good ohmic contact, and it is possible to operate as an MIS transistor even without the amorphous silicon layer 10 and 11, but the tendency for the operating voltage to be high should be avoided. In that case, care must be taken regarding the material and deposition method of the source/drain wirings 7 and 8. Amorphous silicon layer 10 containing impurities
If ゜11 is present, source/drain wiring 7゜8
common aluminum is sufficient.

Now, as shown in FIG. 2C, the amorphous silicon layer 5' containing impurities is selectively removed using the source/drain wiring 7.8 as a mask, but if the removal is insufficient. This is because the remaining impurity-containing amorphous silicon layer between the source and drain 10° and 11 becomes electrically conductive, increasing the leakage current between the source and drain. However, amorphous crystals containing impurities
(High selectivity between silicon and amorphous silicon that does not contain impurities, in other words, the etching speed) "1" without large etching defects, hydrofluoric acid: nitric acid - 1:30 solution Even if an appropriate amount of acid resistance is added to , the selectivity ratio is only about 5 at most, 1.]. Tsuyoshi!
: selectively remove only the amorphous silicon layer containing 7-
;- is extremely difficult.

Normally, when the amorphous silicon layer 5' containing impurities is removed as shown in FIG. Generally, it is set to 12.

As a result, although the increase in leakage current can be suppressed,
The thickness of the impurity-free amorphous silicon layer 4', which becomes the channel of the MIS transistor, is certainly reduced. A certain combination of molybdenum in the gate metal layer 2, an amorphous silicon layer 5 containing phosphorus as an impurity, and a source Φ drain wiring 7. Aluminum was used for a, and hydrofluoric acid: nitric acid was used for the etching solution.
When using 1=30 liquid, the etching speed of the amorphous silicon layer is 6~
The amorphous silicon layer 4', which is multiplied by about 10 times and does not contain 5000 impurities, disappears in just 4 to 6 seconds.

As the channel becomes thinner, the on-current of the MIS l-transistor decreases considerably7, and it is not uncommon for it to be less than % of the temperature at proper etching.1. Another problem is that in the conventional structure shown in FIG. 2(d), the opposite side of the channel is exposed to the outside air, so it tends to absorb moisture from the atmosphere. The Ol(- group in the adsorbed water makes the channel part p
As a result, the threshold voltage of an n-channel MIS transistor increases with the passage of time. In other words, if the operating voltage is constant, g between the source and drain
The y′ turtle current decreases over time. However, it was found that the adsorbed moisture was lost by heating in dry nitrogen gas at about 150° C., and the properties returned to those immediately after manufacture.

How amorphous silicon MIS with conventional structure example
In conventional transistors, unevenness in characteristics due to film deformation in the channel region cannot be avoided, and reliability is extremely unstable.

OBJECTS OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to prevent film deterioration in the channel portion, to form ohmic contact between the source and drain electrodes reliably, and to secure an operating current in the on state. Another purpose of the present invention is to provide a highly reliable MO
The purpose is to capture and provide an 8-type transistor.

Structure of the Invention The present invention forms an insulating layer that shields the channel portion from the outside air, forms an opening in the insulating layer, and subsequently forms n-type amorphous silicon over the entire surface without being exposed to a contaminating atmosphere after vapor phase etching. By forming a layer, poor ohmic contact can be improved.

Description of examples Add the same postal code as Nochiro.

First, as shown in FIG. 3a, a first metal layer 2, which will become a gate, is selectively formed on an insulating substrate 1. Next, a first insulating layer 3 is applied to the entire surface. Amorphous silicon layer containing no impurities 4. A second insulating layer 13 is applied one after the other. Preferably, it is applied within the same chamber internal dimensions or vacuum conveyance path and within a plurality of chambers so that six coats W1'f #f: are not commonly used. For this purpose, a simple method of deposition is by glow discharge decomposition of a silane gas. Next, as shown in FIG. 3, a pair of open 1'' portions 14 which are partially smaller than the gate metal layer 2 are formed in the second insulating layer 13, and an amorphous silicon layer 4 containing no impurities is formed. selectively exposed.

Next S! The surface is plasma etched with a raw material gas containing F 4+ A layer of silicon 6' is then deposited.

Thereafter, as shown in FIG. 3d, an amorphous silicon layer 6.
Second insulating layer 13. The amorphous silicon layer 4 is sequentially and selectively removed to form an island-shaped amorphous silicon layer 6' including the opening.
, 4'. Further, although not shown, an opening 6 is formed in the first insulating layer 3 to provide a connection to the gate metal layer 2.
After forming the first insulating film, a metal layer is deposited on the entire surface of the amorphous silicon layer containing impurities, and a first insulating film is formed on the amorphous silicon layer containing impurities. Source/drain wirings 7 and 8 are formed in the layer 3'2, and C1 and coolant wirings 9 are formed in the first insulating layer 3-, including the opening 1' in the mano-layer. Finally, the amorphous silicon layer 5' containing impurities of the second insulating layer 13'-)H is removed using the source/drain wirings 7 and 8 as a mask; The MIS) transistor according to the invention is completed.

As is clear from the comparison between FIG. 2 d and FIG. 3 e, the present invention Because of the presence of the second insulating layer 13, the impurity-free amorphous silicon layer 4 that will become the channel portion is never etched. Therefore, variations in transistor characteristics due to film deterioration in the channel portion do not occur. “21
At the same time, the second insulating layer 13' has a channel area of +11
The amorphous silicon layer 4' which does not contain impurities and which forms 1f is shielded from the atmosphere. For this reason, moisture in the air is absorbed
However, the channel portion cannot be made p-type through the second insulating layer 13', and the device operates stably even over a long period of time. Of course, the same effect can be expected by passivation in a general sense, that is, by depositing an appropriate insulating layer over the entire surface in the step after the process shown in FIG. The passivation insulating layer is easily contaminated by metal, and depending on the material, the resistance value of the source/drain wiring layer may be high due to a chemical reaction between the passivation insulating layer and the source/drain wiring. There is a drawback. On the other hand, in the present invention, since the second insulating layer 13 having a passivation function is formed subsequent to the deposition of the amorphous silicon layer 4 containing impurities, the amorphous silicon layer and the second insulating layer 13 are The interface with the MIS transistor and the second insulating layer itself have high purity on a semiconductor level, and the introduction of the second insulating layer, which is also a passivation film, has the excellent effect that various properties of the MIS transistor do not change.

Furthermore, ohmic contact between the source/drain electrodes 7 and 8 and the semiconductor layer 4', which is the active region of the transistor, is completely formed as described below. For example, amorphous silicon doped with P (phosphorus) is deposited as an ohmic contact forming layer. If the pretreatment for this deposition is done through only the washing and drying process, a large area of fti
(Some parts of the element do not form ohmic contact.

However, as previously presented by Inventor Kiyoshi et al., SiF
When the interface of a MIS type transistor is etched with 1-1 layers of 1-1/7'1 of semiconductor layer, a clean interface is obtained in terms of electrical characteristics and stability.

Therefore, before depositing the ohmic contact forming layer, SiX
Alternatively, perform plasma etching with a raw material gas such as X e F 2 that does not contaminate the amorphous silicon layer, and expose the surface to a polluting atmosphere such as the air! By successively depositing a pl-doped amorphous silicon layer without fail, ohmic contact can be formed over the entire surface of the semiconductor element with high reliability. 1 Effect of the invention In the MIS type transistor shown in Fig. 2d,
When polar water molecules and the like are adsorbed to the conductor layer of the active region between the source and drain electrical connections, this has a large effect on the electrical characteristics of the syndyster, especially the dark current. In order to improve this instability, a second layer, which is also a passivation film, is used.
By introducing an insulating layer, excellent effects can be obtained on various properties (electrical characteristics, thermal stability, and temporal stability) of the MIS transistor.

In addition, the instability of ohmic contact formation due to the structural changes associated with the present invention can be solved by vapor phase etching the surface that will become the interface between the semiconductor layer and the ohmic contact formation layer to obtain a clean surface and leaving the surface in a contaminating atmosphere. By subsequently applying the ohmic contact-forming layer without exposing the
Ohmic contact can be formed over a large area with high reliability.

As is clear from the above description, the gist of the present invention can be applied to any silicon semiconductor layer other than single crystal silicon, and is applicable to microcrystalline silicon and polycrystalline silicon in addition to amorphous silicon mentioned in the examples. But there's no problem. Also the first
It goes without saying that for the second 1.1.1 edge layer, silicon oxide or silicon carbide may be used as appropriate in addition to silicon nitride.

Transistor plan view, process cross-sectional view, E゛H');'
Figures a to e are process cross-sectional views of a MIS type transistor according to an embodiment of the present invention.

1...Insulating substrate, 2...Gate metal layer, 3'...First insulating layer, 4, 4'...
...Amorphous silicon layer containing no impurities, 5,6'・
...Amorphous silicon layer containing impurities, 6...
...Opening, 7, 8...Source/drain wiring, 9...Gate wiring, 10.11...
Source/drain, 12... Concavity, 13...
...Second insulating layer, 14...Opening.

Name of agent: Patent attorney Toshio Nakao and 1 other person
11 Figure 2

Claims (1)

[Claims] (1) A step of selectively depositing a first metal layer on an insulating substrate, and sequentially applying a first insulating layer, an impurity-free non-single crystal silicon layer, and a second insulating layer over the entire surface. a step of depositing the metal layer, a step of forming a pair of openings in the second insulating layer overlapping a portion of the first metal layer, a step of vapor phase etching, and a step of exposing the main surface after the etching to a contaminating atmosphere. The non-single-crystal silicon layer containing impurities on the entire surface is
ν-containing process and impurity-containing process including the opening.
・Non-containing crystalline silicon layer and impurity-free sun/moon, l
A non-single crystal silicon layer consisting of 17 layers of l'l crystal silicon.
a step of forming an island shape, a step of sequentially depositing a second metal layer completely containing a non-single crystal silicon layer containing impurities on the opening, and using the second metal layer as a mask. Second
1. A method for manufacturing an insulating coat type transistor, comprising a step of removing a non-single crystal silicon layer containing impurities on an insulating layer. (2) The first insulating layer, the impurity-free non-single-crystal silicon layer, and the second insulating layer are deposited continuously without being exposed to the atmosphere. A method for manufacturing an insulated gate transistor according to item 1.