JP3388076B2 - Method for manufacturing staggered thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] TECHNICAL FIELD OF THE INVENTIONBookThe invention is particularly applicable to liquid crystal displays.
Thin Film Tr
ansistor (TFT) and its manufacturing method, and
Liquid crystal display device. [0002] 2. Description of the Related Art Conventionally, active liquid crystal display elements have been used.
Thus, thin film transistors are widely used. inside that
Gate electrode before source / drain electrode formation
Mass production of so-called inverted staggered thin film transistors
Have been. However, in reverse staggered thin film transistors,
When forming a channel protective film, shorten the channel length.
There was a problem that it was difficult to remove. Also the channel
If a protective film is not formed,
It is necessary to make the thickness of the fac
You. This is the case when forming a channel protective film.
The value is at least five times the thickness of the semiconductor. In this case,
Self-alignment with gate electrode by backside exposure from plate side
There was a problem that flaws and in-plane variations in luminance occurred. On the other hand, the shape of source / drain electrodes
A so-called staggered thin film in which a gate electrode is formed after formation
Transistors are smaller than inverted staggered thin film transistors.
Channel length can be shortened, and the manufacturing process can be shortened.
It has the advantages of However, staggered thin film transistors
Source / drain contact regions in
In addition, it is more easily oxidized than the semiconductor layer formed thereon.
As a result, before the semiconductor layer is formed, the source
A natural oxide film is formed on the drain contact region,
It is difficult to obtain good ohmic characteristics at the interface
won. Accordingly, Japanese Patent Publication No. 6-22244 discloses
Is phosphorus (P) as a source / drain contact region.
Ohmic contact layer containing Si and source / drain electrodes
By forming between the body layer, the source / drain
Ohmic contact between electrode and semiconductor layer formed on it
Staggered thin-film transistor tried to improve
Is disclosed. The thin film disclosed in the above publication
FIG. 3 shows the process of manufacturing the transistor. First, as shown in FIG.
On which transparent substrate 51, indium oxide (Indium Tin O
A transparent conductive film 52 of xide (ITO) is formed. Then figure
As shown in FIG. 3B, the transparent conductive film 52 is
And patterned in the shape of an island.
And a drain electrode 53b are formed. Subsequently, as shown in FIG.
Plate 51, source electrode 53a, and drain electrode 53b
A phosphorus (P) -containing layer 54 is formed on each of the surfaces. This resource
Layer 54 is formed by plasma CVD (plasma chemical vapor deposition).
Phase growth method). That is, the transparent substrate 51 is
A substrate temperature of 0 ° C. to 300 ° C._ThreeAl gas
Gon gas diluted to 5000ppm, 10cc / min speed
At a pressure of 10^Two20W high circumference in Torr atmosphere
Doping with plasma power for several minutes
Plate 51, source electrode 53a, and drain electrode 53b
Is diffused on each surface of the substrate to form a phosphorus-containing layer 54.
You. [0008] The phosphorus-containing layer 54 is formed as described above.
After that, for example, as shown in FIG.
The semiconductor layer 55 made of silicon is formed by a plasma CVD method.
Is formed. At this time, the phosphorus in the phosphorus-containing layer 54
The semiconductor layer 55 diffuses into the semiconductor layer 55, and the semiconductor layer 55 and the source electrode
53a and the entire contact surface with the drain electrode 53b.
Therefore, the ohmic contact layers 56 and 57 containing phosphorus
-Each is formed as a drain contact region. Further, a silicon nitride film is formed on the semiconductor layer 55.
The gate insulating film 58 made of silicon is formed by plasma CVD.
It is formed continuously without breaking the vacuum of the device. Even better
Forming a gate electrode 59 on the gate insulating film 58;
Then, a predetermined pattern is formed by etching. [0010] Thereafter, as shown in FIG.
A protective film 60 made of silicon nitride is formed, and a thin film transistor is formed.
The transistor 61 is completed. [0011] However, in the above publication,
In the configuration, the source / drain contact area
The low conductivity of the mic contact layers 56 and 57
As the resistance of the ohmic contact layers 56 and 57 increases,
The on-current decreases. Also, the source electrode 53a, the drain
Phosphorus slightly remains on the transparent substrate 51 between the electrodes 53b.
Therefore, there is a problem that the leak current increases. The present invention has been made to solve the above problems.
The purpose of the
Good ohmic characteristics between the semiconductor region and
Leaks between the source and drain electrodes
Thin film transistor with excellent characteristics
In addition to providing the manufacturing method, the thin film transformer having excellent characteristics is provided.
An object of the present invention is to provide a liquid crystal display device using a transistor. [0013] According to the first aspect of the present invention, there is provided a switch according to the present invention.
The manufacturing method of the tag type thin film transistor solves the above problem.
To form source and drain electrodes
Forming a first semiconductor film to which impurities are added,
Source / drain by patterning conductor film
Source / drain contact areas electrically connected to electrodes
Forming a region, and forming the source / drain contact region.
Area was exposed to hydrogen plasma at a substrate temperature of 350 ° C.
After that, without breaking the vacuum, the source / drain contact area
Forming a second semiconductor layer on the region, and forming the second semiconductor layer on the second semiconductor layer.
Patterning a body layer and a gate insulating film on it
Forming a metal film on it, and patterning
Forming a gate electrode by etching.
It is characterized by. According to the above configuration, the source / drain capacitor
Contact area is electrically connected to source / drain electrodes
It is formed as follows. This source / drain contour
The contact region is doped with impurities, for example, n⁺Amor
Patterning of the first semiconductor film made of fac silicon
Formed. The above-mentioned source / drain capacitor containing impurities
The tact area is susceptible to natural oxidation, and
A native oxide film is formed on the drain / drain contact area.
You. However, the above source / drain contact
By exposing the surface of the region to hydrogen plasma, natural oxidation
Oxygen atoms in the film are reduced by the hydrogen plasma. This
As a result, formed on the source / drain contact area
The natural oxide film thus removed is removed. Then apply vacuum
A second layer is formed on the source / drain contact region without breaking.
Semiconductor layer is formed, followed by a gate insulating film
And a gate electrode are formed. As described above, the hydrogen plasma treatment
The natural oxide film on the source / drain contact area
The semiconductor layer is removed without breaking the vacuum.
Source / drain contact area.
At the interface between the source / drain contact region and the semiconductor layer.
Ohmic contact is significantly improved. Further, in addition to the above, the above configuration is
As before, source / drain contact regions and semiconductor layers
Does not diffuse phosphorus at the interface with
Conventional source / drain due to phosphorus
The leakage current between the electrodes is naturally eliminated. For the above reasons, the above configuration
If the source and drain resistance can be reduced,
In both cases, the resistance between the source and drain electrodes can be increased.
Current leakage between source and drain electrodes
Can be significantly reduced. Also, this conclusion
As a result, the on-current of the thin film transistor can be increased.
And a thin film transistor with good characteristics can be obtained.. [0020] DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment]Book BRIEF DESCRIPTION OF THE DRAWINGS FIG.
FIG. 1 is a cross-sectional view showing a manufacturing process of a transistor.
1 will be described. First, as shown in FIG.
On the plate 1, about 1 tantalum (Ta) is sputtered.
A 50 nm film is formed and patterned into an island shape to form a light shielding film
Form 2 Next, the patterned light shielding film 2 is
Silicon oxide (SiO 2) by sputtering to cover
_Two) Is formed to a thickness of about 250 nm, and the insulating film 3 is formed. Subsequently, as shown in FIG.
Indium oxide (Indi oxide) is formed on the edge film 3 by sputtering.
um Tin Oxide; ITO)
A film is formed and patterned to form a pixel electrode 4.
Then, a sputtering is performed on the insulating film 3 and the pixel electrodes 4.
A tantalum (Ta) film is formed to a thickness of about 200 nm with a ring, and
Patterning the source and drain electrodes 5a and 5b.
To form Next, in FIG.
D (Chemical Vapor Deposition) device, pressure 110
Pa, RF power 150W, substrate temperature 350 ° C
And PH_ThreeContaining 0.5% (SiH_Four) 200s
ccm and hydrogen (H_Two) Using 2000 sccm
As a first semiconductor film to which a pure substance is added, a conductivity of about 1.
0x10^-3(Ω · cm)^-1N⁺Type amorphous silicon
Is formed. Then, the above n⁺Type amorphous silicon
Dry-etching and patterning into islands
The drain / drain contact regions 6a and 6b are formed. This
As a result, the source / drain contact regions 6a, 6b
Are electrically connected to the source / drain electrodes 5a and 5b.
Will be. Next, an in-line type plasma CVD apparatus
In the first reaction chamber, hydrogen (H_Two) 2000scc
m, pressure 80Pa, RF power 300W, substrate temperature 35
Under the condition of 0 ° C., the source / drain contact region 6a,
6b is exposed to hydrogen plasma for 10 minutes,
Perform the processing. As a result, the source / drain contour
In the native oxide film formed on the contact regions 6a and 6b
The atoms are reduced by the hydrogen plasma, and this natural oxide film
Will be removed. Subsequently, without breaking the vacuum in the first reaction chamber.
Then, the substrate is transported to the second reaction chamber. This second
In the reaction chamber, as the second semiconductor layer, an i-type amorphous
A silicon film is formed to a thickness of about 50 nm. Film formation conditions at this time
Is pressure 80 Pa, RF power 150 W, substrate temperature 35
At 0 ° C., plasma CVD (plasma chemical vapor deposition)
Silane (SiH)_Four) 200sccm and water
Elementary (H_Two) 2000 sccm is used. Then above
The i-type amorphous silicon is formed in the source contact region 6
a to the drain contact region 6b.
Turning, as shown in FIG. 1C, the semiconductor layer 7 is
Form. On top of that, silicon nitride (Si_ThreeN
_Four) Is deposited to a thickness of about 250 nm, and as shown in FIG.
A gate insulating film 8 is formed. The film formation condition is a pressure of 130P.
a, RF power 1000W, substrate temperature 250 ° C,
Silane (SiH)_Four) 150 scc
m and ammonia (NH_Three) 200 sccm and nitrogen
(N_Two) 2000 sccm. Subsequently, as shown in FIG.
Titanium (Ti) on the gate insulating film 8 by sputtering
A 200 nm film and pattern it to form a gate electrode.
The pole 9 is formed. Thereafter, as shown in FIG.
Silicon nitride (Si) so as to cover the_ThreeN_Four)
A protective film 10 is formed by forming a film having a thickness of about 250 nm. At this time
The film forming conditions were as follows: pressure 130 Pa, RF power 1000
W, substrate temperature 250 ° C., plasma CVD
Run (SiH_Four) 150 sccm and ammonia (NH
_Three) 200 sccm and nitrogen (N_Two) 2000sccm
And are used. Thus, a staggered thin-film transistor
Data 11 is completed. Although not shown, the thin film transistor
Star 11, color filter and black matrix
And bonded to the opposing substrate with
A liquid crystal panel is obtained by injecting and dividing liquid crystal.
It is. An integrated circuit for driver is mounted on this liquid crystal panel.
By attaching, the liquid crystal module is completed. With the above configuration, the channel length is 5 μm,
The staggered thin film transformer of the present invention having a channel width of 15 μm.
The transistor 11 has an on current of 1.0 μA and an off current of 0.5 μA.
A value of pA or less has been obtained. By the way, sauce dress
Perform hydrogen plasma treatment on the surface of the in-contact area
First, break the vacuum inside the reaction chamber and then form the semiconductor layer.
In the conventional case, the on-current is controlled by the thin film transistor 1 of the present invention.
1/10 or less, and the variation varies from element to element.
Was seen. This is because the vacuum is broken once when forming the semiconductor layer.
And apply a photoresist to pattern the semiconductor layer
The source / drain contact region and the semiconductor layer
This is because an oxide film is formed at the interface with the substrate. Therefore, the present invention, as described above,
The source / drain contact region 6 is formed by performing a
a, remove the natural oxide film formed on 6b, and
After that, the semiconductor layer 7 is formed without breaking the vacuum in the reaction chamber.
Therefore, the source / drain contact regions 6a and 6b and the half
Good ohmic contact at the interface with the conductor layer 7
To obtain a thin film transistor 11 having good electrical characteristics.
it can. Before performing the above-described hydrogen plasma treatment,
The source / drain contact regions 6a and 6b
The formed natural oxide film is coated with BHF (buffered hydrofluoric acid;
HF: H_TwoO = 1: 10) for 1 minute
To remove some natural oxide film in advance.
To shorten the time of subsequent hydrogen plasma treatment
It is also possible. In the first embodiment, the glass substrate 1
A light-shielding film 2 and an insulating film 3 are formed on the
The star 11 has been completed.
Without forming the edge film 3, the thin film transistor 11 was manufactured.
Also, the same effects as those of the present invention can be obtained. [Embodiment 2] Next, another embodiment of the present invention relates to a staggered type.
FIG. 2 is a cross-sectional view showing a manufacturing process of the thin film transistor.
Hereinafter, the manufacturing process will be described with reference to FIG. First, as shown in FIG.
Tantalum (Ta) is sputtered on the plate 21 by sputtering.
Deposit 150nm film and pattern it into island shape to shield light
A film 22 is formed. Next, the patterned light shielding film
Silicon oxide by sputtering to cover 22
(SiO_Two) Is formed to about 250 nm, and an insulating film 23 is formed.
I do. Subsequently, as shown in FIG.
Indium oxide (In) is formed on the edge film 23 by sputtering.
dium Tin Oxide (ITO) transparent conductive film of about 100 nm
A film is formed and patterned to form a pixel electrode 24.
You. Then, on the insulating film 23 and the pixel electrode 24,
Sputtering tantalum (Ta) to about 200 nm
Film and pattern it to form source / drain electrodes 2
5a and 25b are formed. Next, in FIG.
Pressure in the first reaction chamber of the plasma CVD apparatus
a, RF power 150W, substrate temperature 350 ° C,
PH_ThreeContaining 0.5% (SiH_Four) 200scc
m and hydrogen (H_Two) 2000 sccm and impurities
Is added as a first semiconductor film having a conductivity of about 1.0 ×
10^-3(Ω · cm)^-1N⁺Type amorphous silicon
A film is formed to a thickness of 40 nm. Subsequently, the substrate is placed in a second without breaking the vacuum.
Conveyed to the reaction chamber, pressure 80Pa, RF power 150W,
At a substrate temperature of 350 ° C., silane (SiH_Four) 200
sccm and hydrogen (H_Two) Using 2000 sccm
The above n⁺I-type semiconductor layer on amorphous silicon
To form an i-type amorphous silicon film having a thickness of 30 nm.
I do. Note that n⁺Type amorphous silicon is a natural acid
The natural oxide film is readily formed by exposure to air.
Is formed on the surface of the i-type amorphous silicon.
The recon is n⁺Natural compared to amorphous silicon
Hard to oxidize. Thereafter, the above n⁺Type amorphous silicon
And i-type amorphous silicon by dry etching
Patterned in island shape, source / drain contact area
The regions 26a and 26b and the i-type semiconductor layer 27 are formed. This
As a result, the source / drain contact regions 26a, 26
b is electrically connected to the source / drain electrodes 25a and 25b.
And the i-type semiconductor layer 27 is connected to the source / drain
The tact regions 26a and 26b have the same shape and coincide with each other.
Will be piled up. Next, natural oxidation on the i-type semiconductor layer 27 is performed.
The membrane is treated with BHF (buffered hydrofluoric acid; HF: H_TwoO = 1:
Removed by wet etching for 1 minute using 10)
Then, immediately after that, the substrate is placed in an in-line plasma CV.
Introduce to D device. And, as the second semiconductor layer, i-type
Amorphous silicon is deposited to a thickness of about 50 nm. At this time
The film forming conditions were as follows: pressure 80 Pa, RF power 150 W, base
At a plate temperature of 350 ° C., silane is
(SiH_Four) 200 sccm and hydrogen (H_Two) 2000
sccm. Then, the i-type amorphous silicon
Recon from the source contact region 26a to the drain
Patterning in an island shape over the contact region 26b,
As shown in FIG. 2C, a semiconductor layer 28 is formed. Further, silicon nitride (Si)_ThreeN
_Four) Is deposited to a thickness of about 250 nm, and as shown in FIG.
A gate insulating film 29 is formed. The film formation condition is a pressure of 130.
Pa, RF power 1000W, substrate temperature 350 ° C,
Silane (SiH) by plasma CVD_Four) 150sc
cm and ammonia (NH_Three) 200 sccm and nitrogen
(N_Two) 2000 sccm. Subsequently, as shown in FIG.
Titanium (T) is formed on the insulating film 29 by sputtering.
i) is deposited to a thickness of 200 nm,
The electrode 30 is formed. Thereafter, as shown in FIG.
Silicon nitride (Si) so as to cover the_ThreeN_Four)
Is formed to a thickness of about 250 nm to form a protective film 31. This and
The deposition conditions were as follows: pressure 130 Pa, RF power 1000
W, substrate temperature 250 ° C., plasma CVD
Run (SiH_Four) 150 sccm and ammonia (NH
_Three) 200 sccm and nitrogen (N_Two) 2000sccm
And are used. Thus, a staggered thin-film transistor
Tab 32 is completed. Although not shown, the thin film transistor
Star 32, color filter and black matrix
And bonded to the opposing substrate with
A liquid crystal panel is obtained by injecting and dividing liquid crystal.
It is. An integrated circuit for driver is mounted on this liquid crystal panel.
By attaching, the liquid crystal module is completed. With the above configuration, the channel length is 5 μm,
The staggered thin film transformer of the present invention having a channel width of 15 μm.
The on-state current is 0.9 μA and the off-state current is 0.5
A value of pA or less has been obtained. By the way, sauce dress
I-type semiconductor layer 2 on in-contact regions 26a and 26b
The on-state current in the conventional case in which No. 7 is formed is the thin film of the present invention.
Less than 1/10 of the transistor 32
And variation was observed. This is when the semiconductor layer is formed
Break the vacuum once, apply photoresist, and remove the semiconductor layer.
When patterning, the source / drain contact area
Oxide film is formed at the interface between the region and the semiconductor layer
It is. Therefore, the present invention, as described above,
It is difficult to oxidize on the drain contact regions 26a and 26b.
I-type semiconductor layer 27 made of i-type amorphous silicon
Are continuously formed without breaking the reaction chamber vacuum,
Turning, so the source / drain contact area
Suppress formation of natural oxide film on 26a, 26b
Can be As a result, via the i-type semiconductor layer 27
Source / drain contact regions 26a, 26b and semiconductor
Ohmic contact with the body layer 28 is improved. Accordingly
As a result, the on-current of the thin film transistor 32 increases,
The thin film transistor 32 having good properties can be obtained. Further, the thin film transformer manufactured in the second embodiment
In the transistor 32, the i-type semiconductor layer 27 is not formed.
ON current is improved compared to conventional thin film transistors
This thin film transistor 32 is used in a liquid crystal display.
10.4 inch VGA (Video Graphics A
rray) can improve the aperture ratio,
The display can be brightened. Also, the on-current
Increase of 17 inches of 128
Engineering work with 0x3x1024 picture elements
It is possible to manufacture liquid crystal displays for stations.
Wear. In the second embodiment, the glass substrate 2
A light shielding film 22 and an insulating film 23 are formed on
Although the transistor 32 is completed, the light shielding film 22
And the thin film transistor 32 without forming the insulating film 23.
Can produce the same effect as the present invention. In the first and second embodiments, the source
In the drain contact regions 6a, 6b, 26a, 26b
n⁺Type amorphous silicon, but not necessarily
However, it is not limited to this. Source / drain above
The contact regions 6a, 6b, 26a, 26b are made of SiG
e_x(0 ≦ x ≦ 1), SiC_x(0 ≦ x ≦ 1), Si_Three
N_x(0 ≦ x ≦ 4) or SiO_x(0 ≦ x ≦ 2)
Consisting of an amorphous semiconductor or a microcrystalline semiconductor,
Of course, the same effects as those of the present invention can be obtained. For example, the above source / drain contacts
In regions 6a, 6b, 26a, 26b, a conductivity of about 1.0 ×
10^-3(Ω · cm)^-1N⁺Type amorphous silicon
No, conductivity about 1.0 (Ωcm)^-1N⁺Type microcrystal
When silicon is used, the thin film transistors 11 and 32
The ON currents are 1.2 μA and 1.1 μA, respectively.
n⁺Than when using amorphous silicon
It increased by about 20%. The semiconductor layer in which the channel is formed is
And an appropriate mixture of silicon and other materials as described above.
The use of morphus alloy makes it suitable for liquid crystal module applications.
A combined thin film transistor can be manufactured. As in the conventional case, the band gap is about 1.7.
eV amorphous silicon source / drain
When used in the contact area, electrons are valenced when irradiated with light.
Excited from electron band to conduction band, thin film transistor
Off current increased. As described above, another element is added to silicon.
SiC_x, Si_ThreeN_x, SiO_xSo, the band gap
Can be controlled from about 1.7 eV to 2.1 eV.
You. If the band gap is large, the thin film transformer
Electrons shift from valence band to conduction band even when light is irradiated to the transistor
It is not excited and the off-current hardly increases. Accordingly
Liquid crystal module for projection using strong light
The picture element is small as in the
If you also want to suppress the off-state current, silicon
Inject pure material and use amorphous alloy as above
It becomes more suitable. In addition, SiGe_xIn case of
Can be controlled from about 1.7 eV to 1.4 eV.
Wear. When the band gap is narrowed like this, it is weak to light.
However, there is an advantage that the thin film transistor can be driven at a low voltage.
is there. Therefore, for the reasons described above, silicon
Amorphous semiconductor or microcrystalline semiconductor
The liquid crystal module is controlled by controlling the band gap.
Manufacturing thin film transistors that are suitable for
Can be. The semiconductor layer in which this channel is formed
Amorphous alloy with the same band gap as
By using it for the source / drain contact area.
Interface does not become heterojunction and ohmic contact
There is a merit that it becomes easy to take. In the first and second embodiments, the semiconductor layer
7, the i-type semiconductor layer 27 and the semiconductor layer 28
Recon is used, but it is not necessarily limited to this
There is no. The above semiconductor layer 7, i-type semiconductor layer 27, semiconductor
Layer 28 is made of S, as described above, with the addition of another element to silicon.
iGe_x(0 ≦ x ≦ 1), SiC_x(0 ≦ x ≦ 1), S
i_ThreeN_x(0 ≦ x ≦ 4) or SiO_x(0 ≦ x ≦
2) an amorphous semiconductor or a microcrystalline semiconductor
Of course, the same effects as those of the present invention can be obtained. [0058] According to the present invention, a staggered thin film tiger is provided.
As described above, the transistor manufacturing method
Forming an electrode, and a first half doped with impurities.
Forming a conductor film and patterning the semiconductor film.
The source / source connected more electrically to the source / drain electrode
Forming a drain contact region;
The drain contact region is exposed to water at a substrate temperature of 350 ° C.
After exposing to source plasma, the source
Forming a second semiconductor layer on the rain contact region
And a step of patterning the second semiconductor layer.
Forming a gate insulating film on top of and a metal film on top
Form gate electrodes by patterning
And a step of performing Therefore, the source / drain contact
Since the region is exposed to hydrogen plasma, the source / drain
The natural oxide film on the tact region is removed. And vacuum
The second semiconductor layer is formed thereon without breaking
The source / drain contact region and the second semiconductor layer
Ohmic contact at the interface with the substrate is significantly improved.
Also, as in the conventional case, the source / drain contact region
Does not diffuse phosphorus at the interface between the first semiconductor layer and the second semiconductor layer,
Conventional source / drain electrodes caused by this phosphorus
There is no leak current between them. Therefore, for the reasons described above,
According to this configuration, the source and drain resistances are reduced.
And increase the resistance between the source and drain electrodes.
Leakage current between the source and drain electrodes
Can be significantly reduced than before. Ma
As a result, the on-current of the thin film transistor is increased.
To obtain thin film transistors with good characteristics
At the same time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a step of manufacturing a staggered thin film transistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a step of manufacturing a staggered thin film transistor according to another embodiment. FIG. 3 is a cross-sectional view illustrating a manufacturing process of a conventional thin film transistor. [Description of Reference Numerals] 5a Source electrode 5b Drain electrode 6a Source contact region 6b Drain contact region 7 Semiconductor layer 8 Gate insulating film 9 Gate electrode 25a Source electrode 25b Drain electrode 26a Source contact region 26b Drain contact region 27 i-type semiconductor layer 28 Semiconductor Layer (second semiconductor layer) 29 Gate insulating film 30 Gate electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-232673 (JP, A) JP-A-6-61198 (JP, A) JP-A-5-198814 (JP, A) (58) Investigation Field (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (1)

(57) [Claim 1] A step of forming a source / drain electrode;
Forming a first semiconductor film to which an impurity is added, and forming a source / drain contact region electrically connected to a source / drain electrode by patterning the semiconductor film; Exposing the substrate to hydrogen plasma at a substrate temperature of 350 ° C., forming a second semiconductor layer on the source / drain contact region without breaking vacuum, and patterning the second semiconductor layer A method for producing a staggered thin film transistor, comprising: a step of forming a gate insulating film thereon; and a step of forming a gate electrode by forming and patterning a metal film thereon .