KR100816563B1 - A method for manufacturing thin film transistor - Google Patents
A method for manufacturing thin film transistor Download PDFInfo
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- KR100816563B1 KR100816563B1 KR1020010054517A KR20010054517A KR100816563B1 KR 100816563 B1 KR100816563 B1 KR 100816563B1 KR 1020010054517 A KR1020010054517 A KR 1020010054517A KR 20010054517 A KR20010054517 A KR 20010054517A KR 100816563 B1 KR100816563 B1 KR 100816563B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 claims abstract description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 239000010408 film Substances 0.000 description 14
- 239000010410 layer Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
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Abstract
본 발명은 정상 스택형 박막 트랜지스터의 공정을 단순화하고, 특성을 향상시킬 수 있는 박막 트랜지스터 제조방법에 관한 것으로, 정상 스택형 구조의 박막 트랜지스터에 있어서, 유리기판상에 제 1 마스크를 이용하여 픽셀전극을 형성하는 단계와, 상기 픽셀전극과 선택적으로 오버랩되도록 제 2 마스크를 이용하여 소오스/드레인 전극 및 비정질 실리콘층을 형성하는 단계와, 상기 비정질 실리콘층상에 레진을 증착한 후, 제 3 마스크를 이용하여 액티브층을 정의하는 단계와, 상기 레진상에 제 4 마스크를 이용하여 게이트 전극을 형성하는 단계를 포함한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor which can simplify the process of a normal stacked thin film transistor and improve its characteristics. In the thin film transistor having a normal stacked structure, a pixel electrode is formed by using a first mask on a glass substrate. Forming a source / drain electrode and an amorphous silicon layer using a second mask to selectively overlap with the pixel electrode, depositing a resin on the amorphous silicon layer, and then using a third mask Defining an active layer, and forming a gate electrode on the resin using a fourth mask.
Description
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 정상 스택형 구조의 박막 트랜지스터 제조방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of manufacturing a thin film transistor having a normal stacked structure, according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 유리기판 102a : 픽셀전극101:
103a : 소오스/드레인 전극 104 : n+ 비정질 실리콘103a: source / drain electrode 104: n + amorphous silicon
105 : 비정질 실리콘층 106 : 레진105: amorphous silicon layer 106: resin
107a : 게이트 전극107a: gate electrode
본 발명은 박막 트랜지스터 제조방법에 관한 것으로, 특히 정상 스택형 박막 트랜지스터의 공정을 단순화하고, 특성을 향상시킬 수 있는 박막 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor capable of simplifying a process and improving characteristics of a normal stacked thin film transistor.
근래에 고품위 TV(high definition TV : HDTV) 등의 새로운 첨단 영상기기가 개발됨에 따라 평판 표시기에 대한 요구가 대두되고 있다. Recently, with the development of new high-tech video devices such as high definition TVs (HDTVs), there is a demand for flat panel displays.
LCD는 평판 표시기의 대표적인 기술로써 ELD(Electro Luminescence Display), VFD(Vacuum Fluorescence Display), PDP(Plasma Display Panel) 등이 해결하지 못한 저전력화, 고속화 등의 문제를 가지고 있지 않다.LCD is a representative technology of flat panel display and does not have problems such as low power and high speed which ELD (Electro Luminescence Display), VFD (Vacuum Fluorescence Display) and PDP (Plasma Display Panel) cannot solve.
이와 같은 LCD는 크게 수동형과 능동형의 두 가지 형태로 나누어지는데, 능동형 LCD는 각 화소 하나 하나를 박막트랜지스터와 같은 능동소자가 제어하도록 되어 있어 속도, 시야각 그리고 대조비(contrast)에 있어서, 수동형 LCD보다 훨씬 뛰어나 100만 화소 이상의 해상도를 필요로 하는 HDTV에 가장 적합한 표시기로 사용되고 있다. 이에 따라, TFT의 중요성이 부각되면서 이에 대한 연구개발이 심화되고 있다.These LCDs are divided into two types, passive and active. Active LCDs are controlled by active elements such as thin film transistors so that each pixel is controlled in terms of speed, viewing angle, and contrast. It is used as the best indicator for HDTV that requires excellent resolution of 1 million pixels or more. Accordingly, as the importance of TFTs is highlighted, R & D on them is intensifying.
현재, LCD 등에서 화소전극의 선택적 구동을 위해 전기적 스위칭 소자로 사용되는 TFT에 대한 연구개발은 수율 향상 및 생산성 개선에 의한 제조 코스트의 절감에 초점을 맞추어 TFT의 구조개선, 비정질 또는 다결정 실리콘의 특성향상, 전극의 오옴성 접촉저항 및 단선/단락 방지 등에 집중되고 있다. 이중, 비정질 실리콘 TFT의 기술은 대면적, 저가격, 양산성을 이유로 더 많은 연구가 이루어지고 있다.Currently, research and development on TFTs, which are used as electrical switching elements for selective driving of pixel electrodes in LCDs, focus on improving the yield and productivity, and thus improving the structure of TFTs and improving the characteristics of amorphous or polycrystalline silicon. It is focused on ohmic contact resistance of electrodes and prevention of disconnection / short circuit. Of these, more research is being conducted on the technology of amorphous silicon TFT because of its large area, low cost, and mass productivity.
일반적으로 TFT의 구조는 소오스와 게이트가 한 평면상에 놓이는 코플레너 (coplanear)형과 다른 평면상에 놓이는 스택(staggered)형의 두 종류가 있는데, 다결정 실리콘 TFT는 코플레너형 구조이고, 비정질 실리콘 TFT는 대부분이 스택형이다.In general, there are two types of TFT structures: a coplanar type in which a source and a gate are in one plane, and a staggered type in a different plane. TFTs are mostly stacked.
여기서, 상기 스택형 TFT는 게이트가 소오스와 드레인의 밑에 놓인 역 스택형(invertede staggered)이라고 불리우는 바텀 게이트(bottom gate)형과 게이트가 소오스와 드레인 보다 위에 있는 정상 스택형(normal staggered)이라고 불리우는 탑 게이트(top gate)형으로 구별할 수 있다.Here, the stacked TFT has a bottom gate type called an invertede staggered under the source and drain and a top called normal staggered with the gate above the source and drain. It can be distinguished into a top gate type.
이중에서, 상기 바텀 게이트형은 힐락(Hillock) 문제로 인해 알루미늄 단일 레이어를 사용할 수 없지만 탑 게이트형은 알루미늄 단일 레이어를 사용할 수 있어, 메탈 (metal) 선택의 폭이 넓어졌다는 장점이 있다. 그리고 바텀 게이트형일 때는 단차에 의한 문제점 때문에 두께를 높일 수 없었지만 탑 게이트형은 단차 문제가 없어 두께를 증가시킬 수 있다. 따라서, 선폭을 줄여 고정세화가 가능하고 대화면에 적용이 용이하다.Among these, the bottom gate type cannot use a single layer of aluminum due to the problem of Hilllock, but the top gate type can use a single layer of aluminum, which has the advantage of wider metal selection. In the case of the bottom gate type, the thickness cannot be increased because of the problem due to the step difference, but the top gate type can increase the thickness because there is no step problem. Therefore, the line width can be reduced and high definition is possible, and it is easy to apply to a big screen.
또한, 탑 게이트형은 바텀 게이트형에 비해 마스크 수를 감소시킬 수 있으므로 제조단가를 줄일 수 있고, 채널 에치(channel etch)시 데미지(damage)를 고려하지 않아도 되므로 비정질 실리콘의 두께를 감소시켜 누설전류(leakage current)를 줄일 수 있다.In addition, since the top gate type can reduce the number of masks compared to the bottom gate type, the manufacturing cost can be reduced, and the damage of the amorphous silicon is reduced because the thickness of the amorphous silicon is not necessary because channel damage is not required. (leakage current) can be reduced.
그러나, 정상 스택형이라고 불리우는 탑 게이트형은 비정질 실리콘을 증착한 후, 절연막으로 사용하는 실리콘 질화막(SiNX)을 증착하는데 이때 실리콘 질화막의 증착조건이 하부에 있는 비정질 실리콘막에 결함을 주게된다.However, the top gate type, called a normal stack type, deposits amorphous silicon and then deposits a silicon nitride film (SiN X ) used as an insulating film. At this time, the deposition conditions of the silicon nitride film cause defects in the amorphous silicon film below.
즉, 비정질 실리콘 이후 공정에 CVD 장비에 의한 게이트 절연막 증착시 비정질 실리콘에 손상을 주기 때문에 TFT 특성을 저하시킨다.That is, the TFT characteristics are deteriorated because the silicon is damaged after deposition of the gate insulating film by the CVD equipment in the process after the amorphous silicon.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로, 게이트 절연막으로 레진(regin)을 사용하여 정상 스택형이라고 불리우는 탑 게이트형의 공정을 단순화하고, 특성을 향상시킬 수 있는 박막 트랜지스터의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, using a resin as a gate insulating film (regin) to simplify the process of the top gate type called the normal stack type, and to improve the characteristics of a thin film transistor The purpose is to provide a method of manufacturing.
상기 목적을 달성하기 위한 본 발명의 박막 트랜지스터의 제조방법은, 정상 스택형 구조의 박막 트랜지스터에 있어서, 유리기판상에 제 1 마스크를 이용하여 픽셀전극을 형성하는 단계와, 상기 픽셀전극과 선택적으로 오버랩되도록 제 2 마스크를 이용하여 소오스/드레인 전극 및 비정질 실리콘층을 형성하는 단계와, 상기 비정질 실리콘층상에 레진을 증착한 후, 제 3 마스크를 이용하여 액티브층을 정의하는 단계와, 상기 레진상에 제 4 마스크를 이용하여 게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a pixel electrode on a glass substrate using a first mask in a thin film transistor having a normal stacked structure, and selectively overlapping the pixel electrode. Forming a source / drain electrode and an amorphous silicon layer using a second mask, depositing a resin on the amorphous silicon layer, and then defining an active layer using a third mask; And forming a gate electrode using the fourth mask.
또한, 상기 레진상에 형성되는 게이트 전극은 저온으로 증착하는 것을 특징으로 하는 것이 바람직하다.In addition, the gate electrode formed on the resin is preferably characterized in that the deposition at a low temperature.
그리고, 상기 게이트 전극은 Al, AlNd, Mo, Cr중 어느 하나를 선택하여 사용하고, 그 상하부에 Mo를 적층하여 사용하는 것이 바람직하다.The gate electrode may be selected from any one of Al, AlNd, Mo, and Cr, and may be used by laminating Mo above and below.
이하, 본 발명의 박막 트랜지스터 제조방법은 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a thin film transistor of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c은 본 발명의 일실시예에 따른 정상 스택형 구조의 박막 트랜지스터 제조방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a thin film transistor having a normal stacked structure according to an embodiment of the present invention.
본 발명의 일실시예에 따른 정상 스택형 구조의 박막 트랜지스터 제조방법은, 도 1a에 도시한 바와 같이, 유리기판(101)상에 투명전극층(102)을 증착하고, 제 1 마스크을 이용한 식각공정을 통해 픽셀전극(102a)을 형성한다. 이때, 상기 투명전극층(102)은 ITO 또는 IZO를 사용한다.In the method of manufacturing a thin film transistor having a normal stacked structure according to an embodiment of the present invention, as illustrated in FIG. 1A, a transparent electrode layer 102 is deposited on a
그다음, 상기 픽셀전극(102a)을 포함한 기판(101) 전면에 소오스/드레인 전극용 금속막(103)을 증착하고, 상기 소오스/드레인 전극용 금속막(103)상에 n+ 비정질 실리콘층(104)을 증착한 후, 제 2 마스크을 이용한 식각공정을 통해 소오스/드레인 전극용 금속막(103)과 n+ 비정질 실리콘층(104)을 패터닝하여 소오스/드레인 전극(103a)을 형성한다. 이때, 상기 소오스/드레인 전극(103a)중 어느 한 전극은 상기 픽셀전극(102a)과 오버랩되어 연결된다.Then, a source / drain electrode metal film 103 is deposited on the entire surface of the
이어서, 도 1b에 도시한 바와 같이, 상기 n+ 비정질 실리콘층(104)상에 비정질 실리콘층(105)을 증착하고, 상기 비정질 실리콘층(105)상에 레진(106)을 증착한다. 그리고 제 3 마스크를 이용한 식각공정을 통해 상기 비정질 실리콘층(105) 및 레진(106)을 패터닝하여 액티브층을 정의한다.Subsequently, as shown in FIG. 1B, an
그다음, 도 1c에 도시한 바와 같이, 액티브층이 정의된 상기 레진(106)상에 게이트 전극용 금속막(107)을 저온 증착하고, 제 4 마스크를 이용한 식각공정을 통해 선택적으로 패터닝하여 게이트 전극을 형성한다. 이때, 상기 게이트 전극용 금속막(107)은 Al, AlNd, Mo, Cr중 어느 하나를 선택하여 사용하고, 그 상하부에 Mo를 적층하여 사용한다.Next, as shown in FIG. 1C, the gate
여기서, 상기 레진(106) 현상시 하드 베이크(Hard bake) 온도가 130℃ 이상이 되면 레진 특성이 변하기 때문에 좋은 유전율을 가지고 있으면서도 절연막으로 사용하기 어렵다. 그러나 정상 스택형은 이후 공정진행 온도가 낮기 때문에 효과적이다.Here, when the hard bake temperature is 130 ° C. or more during the development of the
이상에서 설명한 바와 같이, 본 발명의 박막 트랜지스터 제조방법에 의하면, 유전특성이 좋은 레진을 정상 스택형에 사용하므로 게이트 절연막을 CVD로 증착할 때 비정질 실리콘에 입히는 손상을 없앨 수 있으므로 특성을 향상시킬 수 있다.As described above, according to the method of manufacturing the thin film transistor of the present invention, since the resin having good dielectric properties is used in the normal stack type, the damage to amorphous silicon when the gate insulating film is deposited by CVD can be eliminated, thereby improving the characteristics. have.
또한, 역 스택형에 비해 마스크 공정 수를 감소시킬 수 있어 제작비용을 감소시킬 수 있고, 레진을 사용함으로써 절연막 증착 공정 및 식각공정이 불필요하므로 공정을 단순화시킬 수 있다.In addition, the number of mask processes can be reduced compared to the inverse stack type, and manufacturing cost can be reduced, and the use of resin can simplify the process because an insulating film deposition process and an etching process are unnecessary.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09162411A (en) * | 1995-12-07 | 1997-06-20 | Sharp Corp | Staggered thin film transistor and its manufacturing method and liquid crystal display device |
| KR20010058180A (en) * | 1999-12-24 | 2001-07-05 | 박종섭 | Method of manufacturing tft-lcd |
| KR20010082851A (en) * | 2000-02-21 | 2001-08-31 | 구본준, 론 위라하디락사 | method for fabricating array substrate for x-ray detector |
| KR20020066573A (en) * | 2001-02-12 | 2002-08-19 | 엘지.필립스 엘시디 주식회사 | Array Panel used for In-Plane Switching mode Liquid crystal display device and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09162411A (en) * | 1995-12-07 | 1997-06-20 | Sharp Corp | Staggered thin film transistor and its manufacturing method and liquid crystal display device |
| KR20010058180A (en) * | 1999-12-24 | 2001-07-05 | 박종섭 | Method of manufacturing tft-lcd |
| KR20010082851A (en) * | 2000-02-21 | 2001-08-31 | 구본준, 론 위라하디락사 | method for fabricating array substrate for x-ray detector |
| KR20020066573A (en) * | 2001-02-12 | 2002-08-19 | 엘지.필립스 엘시디 주식회사 | Array Panel used for In-Plane Switching mode Liquid crystal display device and method for fabricating the same |
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