JPH0282578A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH0282578A JPH0282578A JP63234020A JP23402088A JPH0282578A JP H0282578 A JPH0282578 A JP H0282578A JP 63234020 A JP63234020 A JP 63234020A JP 23402088 A JP23402088 A JP 23402088A JP H0282578 A JPH0282578 A JP H0282578A
- Authority
- JP
- Japan
- Prior art keywords
- gate insulating
- thin film
- insulating film
- ecr plasma
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000010408 film Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 9
- 239000001257 hydrogen Substances 0.000 claims abstract description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 230000007547 defect Effects 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 229910004205 SiNX Inorganic materials 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000001704 evaporation Methods 0.000 abstract 3
- 241000206607 Porphyra umbilicalis Species 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 6
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 239000000370 acceptor Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はアクティブマトリックス方式の液晶デイスプレ
ィや、イメージセンサや３次元集積回路などに応用され
る薄膜トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor applied to active matrix liquid crystal displays, image sensors, three-dimensional integrated circuits, and the like.
従来の薄膜トランジスタは、例えばＪＡＰＡＮＤＩＳＰ
ＬＡＹ ’８６の１９８６年ｐ１９６〜ｐ１９９に示
される様な構造であった。この構造を一般化して、その
概要を第２図に示す、 （ａ）図は主視図であり（ｂ）
図はＡＡ’における断面図である。ガラス、石英、サフ
ァイア等の絶縁基板２０１上に、ドナーあるいは、アク
セプタとなる不純物を添加した多結晶シリコン薄膜から
成るソース電極２０２及びドレイン電極２０３が形成さ
れている。これに接して、ソース電極２０４とドレイン
電極２０５が設けられており、更にソース電極２０２及
びドレイン電極２０３の上側で接し両者を結ぶように多
結晶シリコン薄膜から成る半導体層２０６が形成されて
いる。これらを被覆するようにゲート絶縁膜２０７が熱
ＣＶＤ法により形成されている。更にこれに接しゲート
電極２０８が設けられている。Conventional thin film transistors are, for example, JAPANDISP
It had a structure as shown in LAY '86, 1986, pages 196-199. This structure is generalized and its outline is shown in Figure 2. (a) Figure is the main view, (b)
The figure is a cross-sectional view at AA'. A source electrode 202 and a drain electrode 203 are formed on an insulating substrate 201 made of glass, quartz, sapphire, etc., which are made of a polycrystalline silicon thin film doped with impurities to serve as donors or acceptors. A source electrode 204 and a drain electrode 205 are provided in contact with this, and a semiconductor layer 206 made of a polycrystalline silicon thin film is further formed in contact with the upper side of the source electrode 202 and the drain electrode 203 to connect them. A gate insulating film 207 is formed by thermal CVD to cover these. Furthermore, a gate electrode 208 is provided in contact with this.
しかし、従来の薄膜トランジスタは次のような問題点を
有していた。However, conventional thin film transistors have the following problems.
熱ＣＶＤ法により基板の温度を４００℃に保持しゲート
絶縁膜を形成するため、基板として＃７０５９（コーニ
ング社製）を使用した場合、ゲーｉ・絶縁膜の熱膨張係
数が約８ｘｌＯ−’と小さいのに対し、＃７０５９基板
は４６ｘｌＯ−’と大きい為、ゲート絶縁膜形成後基板
の反り、変形、ゲート絶縁膜のひび割れ等が生じ、薄膜
トランジスタの欠陥の原因となっていた。又基板を大型
化した場合、上記の現象が顕著に見られ基板の大型化の
大きな妨げとなっていた。Since the gate insulating film is formed by maintaining the substrate temperature at 400°C using the thermal CVD method, when #7059 (manufactured by Corning Corporation) is used as the substrate, the thermal expansion coefficient of the gate insulating film is approximately 8xlO-'. In contrast, the #7059 substrate has a large size of 46xlO-', which causes warpage and deformation of the substrate after formation of the gate insulating film, cracks in the gate insulating film, etc., and causes defects in thin film transistors. Furthermore, when the size of the substrate is increased, the above-mentioned phenomenon becomes noticeable and becomes a major hindrance to increasing the size of the substrate.
又熱ＣＶＤ法によりゲート絶縁膜を形成すると形成され
た絶縁膜の膜質が悪く、薄膜トランジスタの表面基Ｒ密
度が約１ ｘ １０”ａｍ−”と大きく。Furthermore, when a gate insulating film is formed by thermal CVD, the quality of the formed insulating film is poor, and the surface group R density of the thin film transistor is as large as about 1 x 10 "am-".
信頼性を著しく低化させていた。Reliability was significantly lowered.
熱ＣＶＤ法は、基板をセットする治具や、チャンバーに
付着したＳ ｉ Ｏｔの膜質が悪く、容易にはく継して
パーティクルが発生し、形成したゲート絶縁膜にピンホ
ールが生じ、薄膜トランジスタの欠陥の原因となってい
た。In the thermal CVD method, the film quality of SiOt adhering to the jig for setting the substrate and the chamber is poor, and it easily peels off, generating particles, causing pinholes in the formed gate insulating film, and causing damage to thin film transistors. This caused the defect.
本発明は、このような問題点を解決するものであり、そ
の目的とするところは、信頼性の高い薄膜トランジスタ
を大面積にわたり、低欠陥で提供することにある。The present invention is intended to solve these problems, and its purpose is to provide a highly reliable thin film transistor over a large area with fewer defects.
本発明の薄膜トランジスタは、ゲート絶縁膜を形成する
前に、水素ＥＣＲプラズマを照射し、真空を保ちゲート
絶縁膜をＥＣＲプラズマＣＶＤ法で形成したことを特徴
とする。The thin film transistor of the present invention is characterized in that, before forming the gate insulating film, hydrogen ECR plasma is irradiated, a vacuum is kept, and the gate insulating film is formed by ECR plasma CVD.
以下実施例に基づいて、本発明の詳細な説明する。第１
図に本発明による薄膜トランジスタの製造方法を示す。The present invention will be described in detail below based on Examples. 1st
The figure shows a method for manufacturing a thin film transistor according to the present invention.
第１図１０１に示す様に、ガラス、石英、サファイア等
の絶縁基板１０１上にドナーあるいはアクセプタとなる
不純物を添加した多結晶シリコン、非晶質シリコン等の
シリコン薄膜から成るソース電極１０２及びドレイン電
極１０３を減圧ＣＶＤ法、プラズマＣＶＤ法等のＣＶＤ
法により形成する。その膜厚は５００〜５０００Ａが望
ましい。As shown in FIG. 1 101, a source electrode 102 and a drain electrode are made of silicon thin films such as polycrystalline silicon, amorphous silicon, etc. doped with impurities to serve as donors or acceptors on an insulating substrate 101 made of glass, quartz, sapphire, etc. 103 by CVD such as low pressure CVD or plasma CVD
Formed by law. The film thickness is preferably 500 to 5000A.
次に多結晶シリコンあるいは非晶質シリコン等のシリコ
ン薄膜から成る半導体層１０４を減圧ＣＶＤ法、プラズ
マＣＶＤ法等のＣＶＤ法、蒸着法により形成する。その
膜厚は２０００Ａ以下が望ましい０次に金属、透明導電
膜等から成るソース配線１０５及びドレイン配線１０６
をスパッタ法あるいは蒸着法により形成する。Next, a semiconductor layer 104 made of a silicon thin film such as polycrystalline silicon or amorphous silicon is formed by a CVD method such as a low pressure CVD method or a plasma CVD method, or a vapor deposition method. The source wiring 105 and the drain wiring 106 are made of zero-order metal, transparent conductive film, etc. whose film thickness is preferably 2000A or less.
is formed by sputtering or vapor deposition.
次に第１図（ｂ）に示す様に水ｊｌｅＥｃＲプラズマを
照射する。使用した装置の概略を第３図に示す、主要部
は、プラズマ室３０３と試料室３１０で構成され、プラ
ズマ室３０３に石英窓３１１を通して、周波数７．４５
ＧＨｚのマイクロ波３０７が外周の磁気コイル３０５に
より磁界が供給できる。プラズマ室内でマイクロ波と磁
界の相互作用で発生したＥＣＲプラズマとイオン流３０
４は発散磁界によって試料室３１０へ輸送され、絶縁基
板３０１上に照射される。マイクロ波のパワーを６２０
Ｗ、ガスライン３０６より５０ＩＣＣＭの水素ガスを供
給し、圧力１．５ｘｌＯ−’Ｔｏｒｒで２分間水＊ＥＣ
Ｒプラズマを照射した。水素ＥＣＲプラズマの照射によ
り、半導体層を成すシリコン薄膜は約２５Ａ／ｍｉｎの
速さでエツチングされた。Next, water jleEcR plasma is irradiated as shown in FIG. 1(b). The outline of the apparatus used is shown in Fig. 3.The main part consists of a plasma chamber 303 and a sample chamber 310.
A magnetic field of GHz microwave 307 can be supplied by a magnetic coil 305 on the outer periphery. ECR plasma and ion flow generated by the interaction of microwaves and magnetic fields in a plasma chamber 30
4 is transported to the sample chamber 310 by a divergent magnetic field and irradiated onto the insulating substrate 301. Microwave power 620
W, 50 ICCM of hydrogen gas is supplied from the gas line 306, and water*EC is heated for 2 minutes at a pressure of 1.5xlO-'Torr.
R plasma was irradiated. By irradiating the hydrogen ECR plasma, the silicon thin film forming the semiconductor layer was etched at a rate of about 25 A/min.
ｌＸｌ０−’Ｔｏｒｒ以下の高真空を保持したまま第１
図（Ｃ）に示す様にＥＣＲプラズマＣＶＤ法によりＳ
ｉＯｔ＋ Ｓ ｉＮ ｘ等のゲート絶縁膜１１１を形
成する。水＊ＥＣＲプラズマを照射後高真空を保持した
ままゲート絶縁膜を形成するため、同一の装置で引き続
き処理した。マイクロ波のパワーを６００ Ｗ、 ガ
スライン３０６より１５５ｃａｎの酸素ガス、ガスライ
ン３０８より６５ｃｃｒｌのＳｉＨ４ガスを供給した。While maintaining a high vacuum of less than lXl0-'Torr,
As shown in Figure (C), S
A gate insulating film 111 such as iOt+SiNx is formed. After irradiation with water*ECR plasma, processing was continued using the same apparatus in order to form a gate insulating film while maintaining a high vacuum. Microwave power was 600 W, 155 can of oxygen gas was supplied from gas line 306, and 65 ccrl of SiH4 gas was supplied from gas line 308.
この時の圧力はｅ、ｏｘｉ。The pressure at this time is e, oxi.
−’Ｔ ｏ ｒ ｒで形成速度は約６７０ Ａ ／ ｍ
ｉ ｎであった。試料室３０２に固定された基板３０
１は高活性プラズマ１０９とイオン流の衝撃効果により
低温で良質の膜が得られる。又ＳｉＮｘを形成する場合
ガスライン３０６より窒素ガスを供給すればよい、ＥＣ
Ｒプラズマ装置を２室構造とし、水素ＥＣＲプラズマ照
射とゲート絶縁膜形成を連続して別々の試料室で処理で
きる構造の装置を用いても全く同一の結果が得られる。-'T o r r and the formation rate is about 670 A/m
It was in. Substrate 30 fixed in sample chamber 302
In No. 1, a high-quality film can be obtained at low temperature due to the impact effect of the highly active plasma 109 and ion flow. In addition, when forming SiNx, nitrogen gas may be supplied from the gas line 306.
Exactly the same results can be obtained even if the R plasma apparatus has a two-chamber structure in which hydrogen ECR plasma irradiation and gate insulating film formation can be performed successively in separate sample chambers.
次に第１図（ｄ）に示す様に金属、透明導電膜より成る
ゲート電極１１２をスパッタ法、蒸着法により形成する
。Next, as shown in FIG. 1(d), a gate electrode 112 made of metal or a transparent conductive film is formed by sputtering or vapor deposition.
この様に製造された薄膜トランジスタは、水素ＥＣＲプ
ラズマ照射により半導体層の表面をエツチングするため
清浄な表面が得られ、更に高真空を維持したまま引き続
き１０−’Ｔｏｒｒ台でゲート絶縁膜を形成するため、
半導体層とゲート絶縁膜の界面に不純物等が付着するこ
とがなく、表面電荷密度を熱ＣＶＤ法の１／１０以下の
小さな値とすることｉｓでき、その結果薄膜トランジス
タの信頼性を大幅に向上できる。In the thin film transistor manufactured in this way, the surface of the semiconductor layer is etched by hydrogen ECR plasma irradiation to obtain a clean surface, and the gate insulating film is subsequently formed at a level of 10-'Torr while maintaining a high vacuum. ,
Impurities etc. do not adhere to the interface between the semiconductor layer and the gate insulating film, and the surface charge density can be reduced to a value less than 1/10 of the thermal CVD method, resulting in a significant improvement in the reliability of thin film transistors. .
又、基板の温度を加熱することなく、ゲート絶縁膜を形
成できるため、基板に熱膨張係数の大きいガラス基板を
用いた場合、形成されたゲート絶縁膜とガラス基板の熱
膨張係数の差が問題となることがなく基板の反り、変形
、ゲート絶縁膜のひび割れ等は生じない。In addition, since the gate insulating film can be formed without heating the substrate, if a glass substrate with a large thermal expansion coefficient is used as the substrate, the difference in thermal expansion coefficient between the formed gate insulating film and the glass substrate will be a problem. There is no warping or deformation of the substrate, cracking of the gate insulating film, etc.
又、効率よく、反応ガスを分解し膜を形成するため試料
室３１０の壁面等にはほとんど膜が付着することがなく
、原理的にパーティクルの発生は少なく、ピンホールの
ないゲート絶縁膜が容易に得られる。In addition, since the reaction gas is efficiently decomposed and a film is formed, there is almost no film adhering to the walls of the sample chamber 310, and in principle, fewer particles are generated, making it easy to form a gate insulating film without pinholes. can be obtained.
本発明の薄膜トランジスタの特性を第４図に示す、横軸
はゲート電圧Ｖａｓ、 縦軸はドレイン電流Ｉｏの対
数値である。ドレイン電圧Ｖｌｌは４Ｖ、 チャネル
長チャネル幅ともに１０μｍである。半導体層には多結
晶シリコンを用いその膜厚は２００人、ゲート絶縁膜は
５ｉｎｓを用いての膜厚は１５００人である。破線は従
来の熱ＣＶＤ法によりゲート絶縁膜を形成した薄膜トラ
ンジスタ、実線は本発明のＥＣＲプラズマＣＶＤにより
形成した薄膜トランジスタである。第４図から明らかな
様に表面電荷密度が減少したため、ゲート電圧Ｏｖでの
ドレイン電極Ｉｓが約４桁小さくなり、サブスレショル
ド領域での立上りも急峻となり特性が向上している。こ
の結果液晶デイスプレィに応用した場合低電圧駆動が可
能となり、コントラスト比の大きい高画質のデイスプレ
ィが実現できる。The characteristics of the thin film transistor of the present invention are shown in FIG. 4, where the horizontal axis is the gate voltage Vas and the vertical axis is the logarithm of the drain current Io. The drain voltage Vll is 4V, and both the channel length and channel width are 10 μm. The semiconductor layer is made of polycrystalline silicon and has a thickness of 200 mm, and the gate insulating film is 5 inches thick and has a thickness of 1500 mm. The broken line represents a thin film transistor whose gate insulating film was formed by the conventional thermal CVD method, and the solid line represents a thin film transistor formed by the ECR plasma CVD method of the present invention. As is clear from FIG. 4, since the surface charge density has decreased, the drain electrode Is at the gate voltage Ov has become smaller by about four orders of magnitude, and the rise in the subthreshold region has become steeper, improving the characteristics. As a result, when applied to a liquid crystal display, low-voltage driving becomes possible, and a high-quality display with a large contrast ratio can be realized.
イメージセンサや３次元集積回路へ応用した場合、低電
圧駆動、低消費電力が実現できる。When applied to image sensors and three-dimensional integrated circuits, low voltage drive and low power consumption can be achieved.
本発明は次のようなすぐれた効果を有する。 The present invention has the following excellent effects.
第１に、薄膜トランジスタの表面電荷密度を小さくでき
、信頼性を大幅に向上できる。First, the surface charge density of the thin film transistor can be reduced, and reliability can be significantly improved.
第２に、ゲート絶縁膜とガラス基板の熱膨張係数の差が
問題となることがなく、基板の反り、変形ゲート絶縁膜
のひび割れ等の発生はなく、大面積にわたり欠陥の少な
い薄膜トランジスタを形成できる。Second, the difference in thermal expansion coefficient between the gate insulating film and the glass substrate does not become a problem, and there is no warping of the substrate or cracking of the deformed gate insulating film, making it possible to form thin film transistors with fewer defects over a large area. .
第３にＥＣＲプラズマＣＶＤ法は原理的にパーティクル
の発生が少なく、ピンホール等の欠陥のないゲート絶縁
膜が容易に得られ、薄膜トランジスタの低欠陥化が実現
できる。Thirdly, the ECR plasma CVD method generates few particles in principle, and a gate insulating film without defects such as pinholes can be easily obtained, making it possible to reduce the number of defects in thin film transistors.
第４に、薄膜トランジスタの電気特性が向上し、低電圧
駆動が可能で高コントラスト比の液晶デイスプレィが実
現できる。Fourth, the electrical characteristics of thin film transistors are improved, and a liquid crystal display that can be driven at low voltage and has a high contrast ratio can be realized.
以上のように、本発明の薄膜トランジスタは数多くの優
れた効果を有するものであり、その応用範囲は、デイス
プレィ用のアクティブマトリックス基板やその周辺回路
、イメージセンサ、３次元集積回路など多岐にわたる。As described above, the thin film transistor of the present invention has many excellent effects, and its application range is wide-ranging, including active matrix substrates for displays, peripheral circuits thereof, image sensors, and three-dimensional integrated circuits.
第１図（ａ）〜（ｄ）は本発明の薄膜トランジスタの製
造方法を示した断面図
第２図（ａ）（ｂ）は従来の薄膜トランジスタの構造を
示しくａ）は上視図、 （ｂ）は断面図第３図はＥＣＲ
プラズマＣＶＤ装置の概略図第４図は薄膜トランジスタ
の特性を示すグラフ１０１．２０１，３０１・・・絶縁
基板１０２．２０２・・・ソース電極
１０３．２０３・・・ドレイン電極
１０４．２０６・・・半導体層
１０５．２０４・・・ソース配線
１０８．２０５・・・ドレイン配線
１１１．２０７・・・ゲート絶縁膜
１０７・・・水＊ＥＣＲプラズマ
１０９・・・高活性プラズマ
１０８．３０４・・・イオン流
１１２．２０８・・・ゲート電極
３０３・・・プラズマ室
３０５・・・磁気コイル
３０６．３０８・・・ガスライン
３０７・・・マイクロ波
３０９・・・真空排気
３１０・・・試料室
３１１・・・石英窓
出願人 セイコーエプソン株式会社
代理人 弁理士 上櫛 雅誉 他１名
（α）
（ｂ）1(a) to 1(d) are cross-sectional views showing the method of manufacturing a thin film transistor of the present invention. FIGS. 2(a) and 2(b) show the structure of a conventional thin film transistor. (a) is a top view; (b) ) is a cross-sectional view. Figure 3 is an ECR.
A schematic diagram of a plasma CVD apparatus. FIG. 4 is a graph showing the characteristics of thin film transistors. 105.204...Source wiring 108.205...Drain wiring 111.207...Gate insulating film 107...Water*ECR plasma 109...Highly active plasma 108.304...Ion flow 112. 208... Gate electrode 303... Plasma chamber 305... Magnetic coil 306, 308... Gas line 307... Microwave 309... Vacuum exhaust 310... Sample chamber 311... Quartz window Applicant Seiko Epson Co., Ltd. Agent Patent attorney Masayoshi Uekushi and 1 other person (α) (b)
Claims (1)
程と、チャネル部を成す半導体層を形成する工程と、ゲ
ート絶縁膜を形成する工程と、ゲート電極を形成する工
程を含む薄膜トランジスタの製造方法において、該ゲー
ト絶縁膜を形成する前に、水素電子サイクロトロン共鳴
プラズマ（以下水素ＥＣＲプラズマと呼ぶ）を照射し、
真空を保ち該ゲート絶縁膜を電子サイクロトロン共鳴Ｃ
ＶＤ法（以下ＥＣＲプラズマＣＶＤと呼ぶ）で形成した
ことを特徴とする薄膜トランジスタの製造方法。In a method for manufacturing a thin film transistor, the method includes forming a source electrode and a drain electrode on an insulating substrate, forming a semiconductor layer forming a channel portion, forming a gate insulating film, and forming a gate electrode, Before forming the gate insulating film, hydrogen electron cyclotron resonance plasma (hereinafter referred to as hydrogen ECR plasma) is irradiated,
Keep the vacuum and apply electron cyclotron resonance C to the gate insulating film.
A method for manufacturing a thin film transistor, characterized in that it is formed by a VD method (hereinafter referred to as ECR plasma CVD).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63234020A JP3055782B2 (en) | 1988-09-19 | 1988-09-19 | How to manufacture thin film transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63234020A JP3055782B2 (en) | 1988-09-19 | 1988-09-19 | How to manufacture thin film transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0282578A true JPH0282578A (en) | 1990-03-23 |
| JP3055782B2 JP3055782B2 (en) | 2000-06-26 |
Family
ID=16964302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63234020A Expired - Lifetime JP3055782B2 (en) | 1988-09-19 | 1988-09-19 | How to manufacture thin film transistors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3055782B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5254480A (en) * | 1992-02-20 | 1993-10-19 | Minnesota Mining And Manufacturing Company | Process for producing a large area solid state radiation detector |
| US5336361A (en) * | 1990-03-23 | 1994-08-09 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing an MIS-type semiconductor device |
| US5401685A (en) * | 1992-12-30 | 1995-03-28 | Hyundai Electronics Industries Co., Ltd. | Method for hydrogenating thin film transistor by using a spin-on-glass film |
| US5534445A (en) * | 1991-01-30 | 1996-07-09 | Minnesota Mining And Manufacturing Company | Method of fabricating a polysilicon thin film transistor |
| US5637512A (en) * | 1990-11-16 | 1997-06-10 | Seiko Epson Corporation | Method for fabricating a thin film semiconductor device |
| US6177302B1 (en) | 1990-11-09 | 2001-01-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using multiple sputtering chambers |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893243A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Improvement of polysilicon thin film semiconductor |
| JPS6271276A (en) * | 1985-09-24 | 1987-04-01 | Mitsubishi Electric Corp | Manufacture of thin film transistor |
| JPS62172732A (en) * | 1986-01-24 | 1987-07-29 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS6342175A (en) * | 1986-08-07 | 1988-02-23 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin film transistor |
| JPS63129632A (en) * | 1986-11-20 | 1988-06-02 | Sumitomo Electric Ind Ltd | Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formation |
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1988
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893243A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Improvement of polysilicon thin film semiconductor |
| JPS6271276A (en) * | 1985-09-24 | 1987-04-01 | Mitsubishi Electric Corp | Manufacture of thin film transistor |
| JPS62172732A (en) * | 1986-01-24 | 1987-07-29 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS6342175A (en) * | 1986-08-07 | 1988-02-23 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin film transistor |
| JPS63129632A (en) * | 1986-11-20 | 1988-06-02 | Sumitomo Electric Ind Ltd | Pattern formation of insulating film and formation of gate electrode of field-effect transistor utilizing said formation |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5336361A (en) * | 1990-03-23 | 1994-08-09 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing an MIS-type semiconductor device |
| US6261877B1 (en) | 1990-09-11 | 2001-07-17 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing gate insulated field effect transistors |
| US6177302B1 (en) | 1990-11-09 | 2001-01-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using multiple sputtering chambers |
| US6566175B2 (en) | 1990-11-09 | 2003-05-20 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing gate insulated field effect transistors |
| US5637512A (en) * | 1990-11-16 | 1997-06-10 | Seiko Epson Corporation | Method for fabricating a thin film semiconductor device |
| US5534445A (en) * | 1991-01-30 | 1996-07-09 | Minnesota Mining And Manufacturing Company | Method of fabricating a polysilicon thin film transistor |
| US5254480A (en) * | 1992-02-20 | 1993-10-19 | Minnesota Mining And Manufacturing Company | Process for producing a large area solid state radiation detector |
| US5525527A (en) * | 1992-02-20 | 1996-06-11 | Minnesota Mining And Manufacturing Company | Process for producing a solid state radiation detector |
| US5818053A (en) * | 1992-02-20 | 1998-10-06 | Imation Corp. | Multi-module solid state radiation detector with continuous photoconductor layer and fabrication method |
| US5942756A (en) * | 1992-02-20 | 1999-08-24 | Imation Corp. | Radiation detector and fabrication method |
| US6262421B1 (en) | 1992-02-20 | 2001-07-17 | Imation Corp. | Solid state radiation detector for x-ray imaging |
| US5401685A (en) * | 1992-12-30 | 1995-03-28 | Hyundai Electronics Industries Co., Ltd. | Method for hydrogenating thin film transistor by using a spin-on-glass film |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3055782B2 (en) | 2000-06-26 |
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