JPH06101478B2 - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereofInfo
- Publication number
- JPH06101478B2 JPH06101478B2 JP3193285A JP3193285A JPH06101478B2 JP H06101478 B2 JPH06101478 B2 JP H06101478B2 JP 3193285 A JP3193285 A JP 3193285A JP 3193285 A JP3193285 A JP 3193285A JP H06101478 B2 JPH06101478 B2 JP H06101478B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor thin
- film
- photoresist
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 77
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000010408 film Substances 0.000 claims description 68
- 239000004065 semiconductor Substances 0.000 claims description 48
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 230000001681 protective effect Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 23
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、アクティブマトリクス表示装置等に用いられ
る，非晶質シリコンや多結晶シリコンなどの半導体薄膜
を用いた絶縁ゲート型薄膜トランジスタで特に半導体薄
膜が極めて薄い構造とその容易な製造方法に関する。Description: TECHNICAL FIELD The present invention relates to an insulated gate thin film transistor using a semiconductor thin film such as amorphous silicon or polycrystalline silicon used in an active matrix display device or the like, and particularly to a semiconductor thin film. Relates to an extremely thin structure and an easy manufacturing method thereof.
絶縁膜基盤上にゲート電極を設け，極めて薄い半導体薄
膜とゲート電極とをほぼ同一の平面形状にした薄膜トラ
ンジスタの構造によって，遮光不要，低いソース・チャ
ンネル間，ドレイン・チャンネル間抵抗を得るととも
に,2回のマスク工程でも製造可能ならしめるものであ
る。その結果，液晶表示装置用などの薄膜トランジスタ
が高歩留り，低コストで得られる。The structure of a thin film transistor in which a gate electrode is provided on an insulating film substrate, and the extremely thin semiconductor thin film and the gate electrode have substantially the same plane shape, does not require light shielding, and has low source-channel and drain-channel resistance. It would be possible if the mask can be manufactured by a single mask process. As a result, thin film transistors for liquid crystal display devices and the like can be obtained at high yield and at low cost.
半導体薄膜とくに非晶質シリコンを用いた薄膜トランジ
スタは，低温で大面積に製作できるので，ガラスとうの
安価な絶縁基板が使用でき，液晶表示装置やイメージセ
ンサー等に応用されつつある。しかし，非晶質シリコン
は光によって導電率が大きく変化するので，薄膜トラン
ジスタ製作においては遮光を行う必要があり，工程数が
多い欠点があった。非晶質シリコンの光導電率を低下す
る一方法として，非晶質シリコン膜厚を極めて薄くする
ことがあるが，従来の構造では製作が困難であった。以
下に第２図を用いて従来技術の問題点を説明する。第２
図は，一般的に用いられる逆スタガー構造薄膜トランジ
スタの断面図である。薄膜トランジスタは，絶縁基板１
の上のゲート電極2,ゲート絶縁膜3,その上の半導体薄膜
（例えば非晶質シリコン膜）4,非晶質シリコン膜４の両
端に設けられたソース電極5,ドレイン電極６からなり，
必要に応じフィールド絶縁膜９が形成されている。非晶
質シリコン膜４とソース電極５或いはドレイン電極６の
界面には低抵抗半導体膜７が形成されている。非晶質シ
リコン膜が殆ど光に感じない厚さである500オングトロ
ーム以下になると，次のような問題が生じる。フィール
ド絶縁膜９にソース，ドレイン電極用開孔を設ける際，
非晶質シリコン膜４が充分なストッパーとならず，ゲー
ト絶縁膜３にピンホールを生じやすく，ゲートとソー
ス，ドレイン間耐圧不良の原因になっていた。また，従
来の場合，非晶質シリコン膜４と低抵抗半導体膜７は連
続的に形成されていないので，非晶質シリコン膜４と低
抵抗半導体膜７の界面に酸化膜が出来やすくソース，ド
レイン部の接触不良が起きやすかった。その他の問題点
として，従来構造では製作工程数が多く（例えば第２図
の例では４回のマスク工程が必要）高歩留り化や低コス
ト化が充分達成できなかった。Since a thin film transistor using a semiconductor thin film, especially amorphous silicon, can be manufactured in a large area at a low temperature, an inexpensive insulating substrate such as glass can be used, and it is being applied to liquid crystal display devices and image sensors. However, since the conductivity of amorphous silicon is greatly changed by light, it is necessary to shield the light when manufacturing a thin film transistor, and there is a drawback that the number of steps is large. One way to reduce the photoconductivity of amorphous silicon is to make the amorphous silicon film extremely thin, but it was difficult to manufacture with the conventional structure. The problems of the prior art will be described below with reference to FIG. Second
The figure is a cross-sectional view of a commonly used inverted staggered thin film transistor. The thin film transistor is an insulating substrate 1
A gate electrode 2, a gate insulating film 3, a semiconductor thin film (for example, an amorphous silicon film) 4 thereon, a source electrode 5 and a drain electrode 6 provided at both ends of the amorphous silicon film 4,
A field insulating film 9 is formed if necessary. A low resistance semiconductor film 7 is formed on the interface between the amorphous silicon film 4 and the source electrode 5 or the drain electrode 6. When the thickness of the amorphous silicon film is less than 500 angstrom, which is almost invisible to light, the following problems occur. When forming openings for source and drain electrodes in the field insulating film 9,
The amorphous silicon film 4 does not function as a sufficient stopper, and pinholes are easily generated in the gate insulating film 3, which causes a failure in breakdown voltage between the gate, the source, and the drain. Further, in the conventional case, since the amorphous silicon film 4 and the low resistance semiconductor film 7 are not continuously formed, an oxide film is easily formed at the interface between the amorphous silicon film 4 and the low resistance semiconductor film 7, and the source, Poor contact at the drain was likely to occur. As another problem, in the conventional structure, the number of manufacturing steps is large (for example, four mask steps are required in the example of FIG. 2), and high yield and cost reduction cannot be sufficiently achieved.
そこで，この発明は，従来のこのような欠点を解決する
ためになされたもので，第一の目的は極めて薄い半導体
薄膜を用いたときでも，製造しやすい薄膜トランジスタ
の構造を提供し，第二の目的は製造工程数が大幅に減少
できる薄膜トランジスタの構造を提供することである。
第三の目的は，本発明の薄膜トランジスタに最も適した
製造方法を提示し，総合目的として高歩留り，低コス
ト，大面積化が容易な薄膜トランジスタと製造方法を提
供するものである。Therefore, the present invention has been made in order to solve the conventional drawbacks described above, and a first object thereof is to provide a structure of a thin film transistor which is easy to manufacture even when an extremely thin semiconductor thin film is used. The purpose is to provide a structure of a thin film transistor in which the number of manufacturing steps can be significantly reduced.
A third object is to present a manufacturing method most suitable for the thin film transistor of the present invention, and to provide a thin film transistor and a manufacturing method which are high in yield, low in cost, and easy to increase in area as a general purpose.
上記問題点を解決するために，この発明は，半導体薄膜
や低抵抗半導体薄膜の膜厚を極めて薄くし，絶縁基板を
透明とし，裏面からの入射光で自己整合的なマスク合わ
せを行い低抵抗半導体薄膜，半導体薄膜をなどを選択除
去する。In order to solve the above problems, the present invention makes a semiconductor thin film and a low resistance semiconductor thin film extremely thin, makes an insulating substrate transparent, and performs self-aligned mask alignment with incident light from the back surface to achieve a low resistance. Selectively remove semiconductor thin film, semiconductor thin film, etc.
上記のように，半導体薄膜や低抵抗半導体薄膜の膜厚を
極めて薄くすると，大部分の光は半導体薄膜や低抵抗半
導体薄膜を殆ど透過するので，フォトレジストを塗布
後，絶縁基盤の裏面から露光，現像して形成したフォト
レジストの平面形状をマスクとして，半導体薄膜や低抵
抗半導体薄膜を選択除去できるので，マスク合わせの工
程を大幅に減らすことができる。As described above, when the semiconductor thin film or the low resistance semiconductor thin film is made extremely thin, most of the light is transmitted through the semiconductor thin film or the low resistance semiconductor thin film, so after the photoresist is applied, the back surface of the insulating substrate is exposed. Since the semiconductor thin film and the low resistance semiconductor thin film can be selectively removed using the planar shape of the developed photoresist as a mask, the mask alignment process can be significantly reduced.
第１図に，本発明による薄膜トランジスタの一構造例
を，アクティブマトリクス液晶表示装置に適用した例を
示す。第１図（ａ）は本発明の薄膜トランジスタの平面
図である。第１図（ｂ）は第１図（ａ）のＡ−Ａ′線に
沿った断面図である。本発明を非晶質シリコンを用いる
例で説明すれば，薄膜トランジスタはガラス等の透明絶
縁膜基板１の上に形成された導電膜からなるゲート電極
２とその上のゲート絶縁膜3,ゲート絶縁膜の上に形成さ
れた非晶質シリコン膜4,非晶質シリコン膜４とその両端
で接するソース電極５とドレイン電極６からなる。ソー
ス電極５とドレイン電極６は低抵抗半導体薄膜７と透明
導電膜８の二層膜からなる。特徴的なことはゲート電極
２と非晶質シリコン膜４がゲート電極延在部を含めほぼ
同一形状の島状領域２として形成されている点と透明導
電膜８の一部の端が低抵抗半導体薄膜７の一部の端とほ
ぼ一致している点である。第１図（ａ）の平面図から明
らかなように，パターニングは原則的に２種のみであ
る。FIG. 1 shows an example in which one structural example of the thin film transistor according to the present invention is applied to an active matrix liquid crystal display device. FIG. 1 (a) is a plan view of the thin film transistor of the present invention. FIG. 1B is a sectional view taken along the line AA ′ of FIG. To explain the present invention with an example using amorphous silicon, a thin film transistor is a gate electrode 2 made of a conductive film formed on a transparent insulating film substrate 1 such as glass, and a gate insulating film 3 and a gate insulating film 3 formed thereon. It is composed of an amorphous silicon film 4, an amorphous silicon film 4 formed on the upper surface, and a source electrode 5 and a drain electrode 6 which are in contact with each other at both ends. The source electrode 5 and the drain electrode 6 are composed of a two-layer film including a low resistance semiconductor thin film 7 and a transparent conductive film 8. A characteristic is that the gate electrode 2 and the amorphous silicon film 4 are formed as an island-shaped region 2 having substantially the same shape including the gate electrode extension portion and a part of the transparent conductive film 8 has a low resistance. This is a point that substantially coincides with a part of the edge of the semiconductor thin film 7. As is clear from the plan view of FIG. 1 (a), there are basically only two types of patterning.
第３図には，本発明による薄膜トランジスタの製造方法
を，第１図の本発明の薄膜トランジスタに適用した例を
示す。FIG. 3 shows an example in which the method of manufacturing a thin film transistor according to the present invention is applied to the thin film transistor of the present invention shown in FIG.
第３図（ａ）は，ガラス，石英等の透明絶縁基板１の上
に導電膜10を堆積し，フォトレジスト11を選択的にパタ
ーニングした状態を示す。導電膜10としてCr,Mo,W,Al,A
u等の金属膜あるいはこれらの多層膜を用いた例を示し
た。FIG. 3A shows a state in which the conductive film 10 is deposited on the transparent insulating substrate 1 made of glass, quartz or the like, and the photoresist 11 is selectively patterned. Cr, Mo, W, Al, A as the conductive film 10
An example using a metal film such as u or a multilayer film of these is shown.
第３図（ｂ）は、フォトレジスト11をマスクとして導電
膜10を選択的にパターニングしてゲート電極２を形成し
た後、ゲート絶縁膜3,非晶質シリコン膜4,低抵抗半導体
薄膜７を連続的に堆積し，その上にフォトレジスト12を
塗布し，透明絶縁基板１の裏面からゲート電極２をマス
クとして露光，現像してパターニングした状態を示す。
ゲート絶縁膜3,半導体薄膜4,低抵抗半導体薄膜７は例え
ばプラズマCVD法により，二酸化シリコン膜（または窒
化シリコン膜など），非晶質シリコン膜，不純物をドー
プした非晶質シリコン膜と連続的に堆積される。なお、
半導体薄膜４、低抵抗半導体薄膜７の厚みは、それぞれ
500オングストローム以下、300オングストローム以下に
形成することが好ましい。FIG. 3B shows that after the conductive film 10 is selectively patterned using the photoresist 11 as a mask to form the gate electrode 2, the gate insulating film 3, the amorphous silicon film 4, and the low resistance semiconductor thin film 7 are formed. A state is shown in which the layers are successively deposited, a photoresist 12 is applied thereon, and the back surface of the transparent insulating substrate 1 is exposed and developed using the gate electrode 2 as a mask and developed to be patterned.
The gate insulating film 3, the semiconductor thin film 4, and the low-resistance semiconductor thin film 7 are continuously formed by a plasma CVD method, for example, with a silicon dioxide film (or a silicon nitride film), an amorphous silicon film, and an impurity-doped amorphous silicon film. Be deposited on. In addition,
The thicknesses of the semiconductor thin film 4 and the low resistance semiconductor thin film 7 are respectively
It is preferably formed to 500 angstroms or less, and 300 angstroms or less.
第３図（ｃ）は，フォトレジスト12をマスクとして，不
純物をドープした非晶質シリコン膜，非晶質シリコン膜
を選択的にパターニングした後，透明導電膜８を堆積し
た後フォトレジスト13を塗布し，第二のパターニングを
した状態を示す。透明導電膜８はスパッタ法,CVD法など
で堆積されたインジウム・スズ酸化物等からなる。第３
図（ｃ）のフォトレジスト13をマスクとして透明導電膜
８を選択的にパターニングすると第１図に示す本発明の
薄膜トランジスタ装置が完成する。In FIG. 3C, the amorphous silicon film doped with impurities and the amorphous silicon film are selectively patterned using the photoresist 12 as a mask, the transparent conductive film 8 is deposited, and then the photoresist 13 is removed. The state where the second patterning is applied is shown. The transparent conductive film 8 is made of indium tin oxide or the like deposited by a sputtering method, a CVD method or the like. Third
By selectively patterning the transparent conductive film 8 using the photoresist 13 of FIG. 1C as a mask, the thin film transistor device of the present invention shown in FIG. 1 is completed.
第４図（ａ），（ｂ）には，薄膜トランジスタ上に保護
膜を形成する場合の，本発明の製造方法の一実施例を示
す。FIGS. 4 (a) and 4 (b) show an embodiment of the manufacturing method of the present invention when a protective film is formed on a thin film transistor.
第４図（ａ）は，第１図で示す薄膜トランジスタ装置の
上にポリイミドなどの絶縁性保護膜14を塗布または堆積
し，その上にフォトレジスト15を塗布し，透明絶縁基板
１の裏面からゲート電極２をマスクとして露光，現像し
てパターニングした状態を示す。FIG. 4 (a) shows that the insulating protective film 14 such as polyimide is applied or deposited on the thin film transistor device shown in FIG. 1 and the photoresist 15 is applied thereon, and the gate is applied from the back surface of the transparent insulating substrate 1. A state where the electrode 2 is used as a mask for exposure, development and patterning is shown.
第４図（ｂ）は，フォトレジスト15をマスクとして絶縁
性保護膜14を選択的に形成した状態を示す。絶縁性保護
膜14の平面形状は，ゲート電極２とほぼ同じなることは
図から明らかである。FIG. 4B shows a state in which the insulating protective film 14 is selectively formed using the photoresist 15 as a mask. It is clear from the drawing that the planar shape of the insulating protective film 14 is almost the same as that of the gate electrode 2.
以上に説明した第３図（ａ），（ｂ），（ｃ）第４図
（ａ），（ｂ）の本発明の実施例では，絶縁性保護膜14
の選択的形成を含めて２回のマスク工程で製造できるの
で製造歩留りと製造コストを大幅に向上できる。また，
半導体薄膜４と低抵抗半導体薄膜12は同一装置内で連続
的に堆積できるので，二層の間に絶縁膜が出来にくく，
良好な電気的接触が実現できる。In the embodiment of the present invention shown in FIGS. 3 (a), (b) and (c) and FIGS. 4 (a) and (b) described above, the insulating protective film 14 is used.
The manufacturing yield and the manufacturing cost can be significantly improved because the manufacturing can be performed in two mask steps including the selective formation of Also,
Since the semiconductor thin film 4 and the low resistance semiconductor thin film 12 can be continuously deposited in the same device, it is difficult to form an insulating film between the two layers,
Good electrical contact can be achieved.
以上のように，本発明によれば極めて薄い半導体薄膜を
用いて，薄膜トランジスタが容易に製作でき，工程数も
非常に少ない。アクティブマトリクス液晶表示装置を例
にとれば，従来の４〜６回のマスク工程が２回にでき，
マスク低減と高歩留り化が達成される。極薄の半導体薄
膜を用いるので，遮光が不要な上に，ソースとドレイン
間のチャンネル間抵抗が減少して，オン電流の大きな薄
膜トランジスタが得られる利点がある。As described above, according to the present invention, a thin film transistor can be easily manufactured using an extremely thin semiconductor thin film, and the number of steps is very small. Taking an active matrix liquid crystal display device as an example, the conventional mask process of 4 to 6 times can be performed twice,
Mask reduction and high yield are achieved. Since an ultrathin semiconductor thin film is used, there is an advantage that a thin film transistor having a large on-current can be obtained because light resistance is unnecessary and the resistance between channels between the source and drain is reduced.
本半導体薄膜を主にアクティブマトリクス液晶表示装置
を例に述べたが，他の薄膜トランジスタ装置例えば薄膜
トランジスタ集積回路，イメージセンサー，薄膜トラン
ジスタを撮像や画像装置等にも適用できる。また半導体
薄膜として非晶質シリコンを例にとって説明したが多結
晶シリコン，ビームアニールされた薄膜半導体や他の材
料にも適用可能である。Although the present semiconductor thin film has been mainly described by taking the active matrix liquid crystal display device as an example, other thin film transistor devices such as a thin film transistor integrated circuit, an image sensor, and a thin film transistor can be applied to an imaging device or an image device. Although amorphous silicon has been described as an example of the semiconductor thin film, it can be applied to polycrystalline silicon, a beam annealed thin film semiconductor, and other materials.
本発明により，薄膜トランジスタの低コスト化が可能に
なるので，更に応用範囲が拡がり工業的価値が高い。According to the present invention, the cost of the thin film transistor can be reduced, so that the application range is further expanded and the industrial value is high.
第１図（ａ）は本発明による薄膜トランジスタの平面
図，第１図（ｂ）は第１図（ａ）のＡ−Ａ′線に沿った
断面図，第２図は従来の薄膜トランジスタの構造を示す
断面図，第３図（ａ）乃至（ｃ）は本発明の製造方法を
示す工程順断面図である。第４図（ａ）と（ｂ）は本発
明の他の製造方法を示す工程順断面図である。 １……透明絶縁基板 ２……ゲート電極 ３……ゲート絶縁膜 ４……非晶質シリコン膜 ５……ソース電極 ６……ドレイン電極 ７……低抵抗半導体薄膜 ８……透明導電膜 11,12,13,15……フォトレジスト 14……絶縁性保護膜FIG. 1 (a) is a plan view of a thin film transistor according to the present invention, FIG. 1 (b) is a cross-sectional view taken along the line AA ′ of FIG. 1 (a), and FIG. 2 shows the structure of a conventional thin film transistor. The sectional views shown in FIGS. 3A to 3C are sectional views in order of steps showing the manufacturing method of the present invention. FIGS. 4A and 4B are sectional views in order of the steps, showing another manufacturing method of the present invention. 1 ... Transparent insulating substrate 2 ... Gate electrode 3 ... Gate insulating film 4 ... Amorphous silicon film 5 ... Source electrode 6 ... Drain electrode 7 ... Low resistance semiconductor thin film 8 ... Transparent conductive film 11, 12,13,15 …… Photoresist 14 …… Insulating protective film
Claims (5)
されたゲート電極と、該ゲート電極上に形成されたゲー
ト絶縁膜と、該ゲート絶縁膜上に形成された半導体薄膜
と、該半導体薄膜上に互いに離間して形成されたソース
電極とドレイン電極とからなる薄膜トランジスタにおい
て、 前記ゲート電極と半導体薄膜とがゲート電極とほぼ同一
の平面形状に形成されたことを特徴とする薄膜トランジ
スタ。1. A transparent insulating substrate, a gate electrode formed on the transparent insulating substrate, a gate insulating film formed on the gate electrode, a semiconductor thin film formed on the gate insulating film, A thin film transistor comprising a source electrode and a drain electrode formed on a semiconductor thin film and spaced apart from each other, wherein the gate electrode and the semiconductor thin film are formed in substantially the same plane shape as the gate electrode.
膜と低抵抗半導体薄膜とからなることを特徴とする特許
請求の範囲第１項記載の薄膜トランジスタ。2. The thin film transistor according to claim 1, wherein the source and drain electrodes are composed of a transparent conductive film and a low resistance semiconductor thin film.
膜で、かつ、平面的に重畳して覆われていることを特徴
とする特許請求の範囲第１項または第２項記載の薄膜ト
ランジスタ。3. The thin film transistor according to claim 1, wherein the surface is covered with a protective film having substantially the same shape as that of the gate electrode, and is planarly overlapped. .
るゲート電極を選択的に形成する第１工程と、 （ｂ）ゲート絶縁膜、半導体薄膜、低抵抗半導体薄膜を
順次連続して堆積する第２工程と、 （ｃ）フォトレジストを塗布した後、透明絶縁基板の裏
面から露光、現像して形成したフォトレジストの平面形
状をマスクとして、前記低抵抗半導体薄膜と半導体薄膜
を選択除去する第３工程と、 （ｄ）透明導電膜を形成する第４工程と、 （ｅ）前記透明導電膜と低抵抗半導体薄膜の不要部を少
なくとも除去する第５工程とからなることを特徴とする
薄膜トランジスタの製造方法。4. A first step of selectively forming a gate electrode made of a first conductive film on a transparent insulating substrate, and (b) a gate insulating film, a semiconductor thin film, and a low-resistance semiconductor thin film are successively formed. And (c) after applying the photoresist, the low resistance semiconductor thin film and the semiconductor thin film are selected using the planar shape of the photoresist formed by exposing and developing from the back surface of the transparent insulating substrate as a mask. A third step of removing, a (d) fourth step of forming a transparent conductive film, and (e) a fifth step of removing at least an unnecessary portion of the transparent conductive film and the low resistance semiconductor thin film. Method of manufacturing thin film transistor.
るゲート電極を選択的に形成する第１工程と、 （ｂ）ゲート絶縁膜、半導体薄膜、低抵抗半導体薄膜を
順次連続して堆積する第２工程と、 （ｃ）フォトレジストを塗布した後、透明絶縁基板の裏
面から露光、現像して形成したフォトレジストの平面形
状をマスクとして、前記低抵抗半導体薄膜と半導体薄膜
を選択除去する第３工程と、 （ｄ）透明導電膜を堆積する第４工程と、 （ｅ）前記透明導電膜と低抵抗半導体薄膜の不要部を少
なくとも除去する第５工程と、 （ｆ）表面保護用絶縁膜を形成する第６工程と、 （ｇ）フォトレジストを塗布後、透明絶縁基板の裏面か
ら露光、現像して形成したフォトレジストの平面形状を
マスクとして、前記表面保護用絶縁膜を選択除去する第
７工程とからなることを特徴とする薄膜トランジスタの
製造方法。5. A first step of selectively forming a gate electrode made of a first conductive film on a transparent insulating substrate, and (b) a gate insulating film, a semiconductor thin film, and a low resistance semiconductor thin film are successively formed. And (c) after applying the photoresist, the low resistance semiconductor thin film and the semiconductor thin film are selected using the planar shape of the photoresist formed by exposing and developing from the back surface of the transparent insulating substrate as a mask. A third step of removing, (d) a fourth step of depositing a transparent conductive film, (e) a fifth step of removing at least an unnecessary portion of the transparent conductive film and the low-resistance semiconductor thin film, (f) surface protection Step 6 of forming an insulating film for photoresist, and (g) selecting the surface insulating film by using the planar shape of the photoresist formed by applying photoresist and exposing and developing from the back surface of the transparent insulating substrate as a mask. 7th to remove A method of manufacturing the thin film transistor characterized by comprising a degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3193285A JPH06101478B2 (en) | 1985-02-20 | 1985-02-20 | Thin film transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3193285A JPH06101478B2 (en) | 1985-02-20 | 1985-02-20 | Thin film transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61191072A JPS61191072A (en) | 1986-08-25 |
| JPH06101478B2 true JPH06101478B2 (en) | 1994-12-12 |
Family
ID=12344742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3193285A Expired - Lifetime JPH06101478B2 (en) | 1985-02-20 | 1985-02-20 | Thin film transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101478B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142868A (en) * | 1986-12-05 | 1988-06-15 | Sharp Corp | Thin-film transistor |
| JPS63137479A (en) * | 1986-11-29 | 1988-06-09 | Sharp Corp | Thin-film transistor |
| US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
| US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
| US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
| US5032883A (en) * | 1987-09-09 | 1991-07-16 | Casio Computer Co., Ltd. | Thin film transistor and method of manufacturing the same |
| JP3172841B2 (en) * | 1992-02-19 | 2001-06-04 | 株式会社日立製作所 | Thin film transistor, method of manufacturing the same, and liquid crystal display device |
-
1985
- 1985-02-20 JP JP3193285A patent/JPH06101478B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61191072A (en) | 1986-08-25 |
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