JPS63137479A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To keep OFF and ON resistances constant, and to increase the area of a display unit by forming a gate insulating layer, an a-Si semiconductor film having a shape that the semiconductor film is self-aligned with a gate electrode and a contact film onto the gate electrode consisting of an opaque metal and shaping a protective insulating film between the semiconductor film and the contact film. CONSTITUTION:A gate electrode 2 composed of Ta, etc., is laminated onto an insulating substrate 1. A gate insulating layer 3, an a-Si semiconductor layer 4 and a protective insulating film 5 are laminated onto the whole surface. An N<+> type a-Si layer 6A and a positive type photo-resist layer 10A are laminated onto the film 5. Exposure is executed from the substrate 1 side, and a resist 10 having a shape that the resist 10 is self-joined with the electrode 2 is shaped onto the layer 6A, using the gate electrode 2 as a photo-mask. Layers 6A, 4A are etched, employing the resist 10 as a mask, and an N<+> type a-Si layer 6B having a shape that the layer 6B is self-aligned with the electrode 2 and the active layer 4 are formed. The resist 10 is removed. A metal 8A and a resist layer 11 are laminated onto the whole surface, and the layers 8A, 6B are etched, using the layer 11 as a mask to form a source region 6, a drain region 7, a source electrode 8 and a drain electrode 9.

Description

Detailed Description of the Invention (a) Industrial Application Field This invention relates to a thin film transistor using a semiconductor film made of amorphous silicon, and in particular to a thin film transistor used for back lighting when used as a display device in combination with a liquid crystal panel. The present invention relates to a technique for preventing a decrease in off resistance of

(B) Prior Art Today, research and practical use are actively being carried out on large-capacity display devices in which thin film transistors are arranged in a matrix on an insulating substrate such as glass, and are combined with a liquid crystal or the like. Especially a-
WJI using 3+ (amorphous silicon) semiconductor film
I transistors are viewed as promising because they can use inexpensive glass as an insulating substrate and can be made to have a large area.

Now, the conventional 1at-transistor T" using the a73i semiconductor film has the structure as shown in FIG.
is wider than that corresponding to the gate electrode 2a, and the active m4a
and n forming the source region 6a and drain region 7a.
◆ No consideration was given to the thickness of the amorphous silicon semiconductor film. Note that 8a and 9a are a source electrode and a drain electrode, respectively.

(c) Problems to be Solved by the Invention When a display device is constructed and used by combining the thin film transistor Tr with a liquid crystal, a backlight is placed on the glass plate side that is the insulating substrate 1a. At this time, the thin film transistor Tr is set to 0"
In this state (a negative voltage is applied to the gate electrode 2a), carriers are generated in a portion of the active JI 4a that is not self-aligned with the gate electrode 2a, resulting in a decrease in off resistance.

One way to solve this problem is to reduce the thickness of the active layer 4a made of an a-3i semiconductor film. Incidentally, when the thickness of the active layer 4a is set to 100 Å or less, no effect of backlighting is observed on the active layer 114a. However, if the thickness of the active layer 4a is made thinner to a certain extent,
A problem arises in that the resistance in the on state becomes high.

Another possible method is to prevent the generation of carriers by forming a light shield. However, forming a light shield increases the number of manufacturing steps, resulting in poor yield and high cost.

Furthermore? 11! The transistor Tr is configured such that the active layer 4a is located at a corresponding portion on the gate insulating layer 3a and the gate electrode 2
A possible method is to use a configuration that has the same shape as a. However, if a thin film transistor is formed using normal mask alignment so as to have this configuration, alignment errors, side etching, etc. must be taken into account, and the size of the thin film transistor becomes large. Therefore, if the size of the thin film transistor is large, the aperture ratio in the display device will decrease, and the load capacitance between the gate and drain will increase, and as a result, the original purpose of increasing the area of the display device cannot be strongly expected. .

This invention was made in view of the above circumstances, and when a display device is constructed and used in combination with a liquid crystal, the off resistance and on resistance are ensured at predetermined values, the cost does not increase, and The present invention provides a thin film transistor that can be used to increase the area of a display device.

(D) Means for Solving the Problems This invention forms a resist by exposure using an opaque metal gate electrode as a mask, and etches using this resist as a mask to form an active layer, a source region, and a drain region. In addition, the thin film transistor has a protective insulating film interposed between the active layer and the source and drain regions.

The detailed structure is such that a gate electrode made of an opaque metal is laminated on an insulating substrate, a gate insulating layer is further laminated on the gate electrode and the surface of the insulating substrate, and a thickness is an amorphous silicon semiconductor film and an amorphous silicon contact film, both of which are 100 Å or more and whose total film thickness is 100 OA or less, are laminated with a contour shape that is self-aligned with the gate electrode, and the amorphous silicon semiconductor film and the amorphous silicon contact film are A thin film transistor characterized in that a protective insulating film is interposed between the amorphous silicon contact film to separate the amorphous silicon contact film into a source region and a drain region, and a source electrode and a drain electrode are connected to the source region and the drain region, respectively. be.

(e) Operation A shape that is self-aligned with the gate electrode of the active layer can be easily obtained by etching using a resist formed by light from the insulating substrate side and a positive photoresist as a mask.

(f) Examples This invention will be described in detail based on the examples shown in FIGS. 1 to 8, but the invention is not limited thereby.

The structure of the WIII transistor T is as shown in FIG. 1, where 1 is an insulating substrate, 2 is a gate electrode, 3 is a gate insulating layer, 4 is an active layer, 5 is a protective insulating film, 6 is a source region, and 7 is a In the drain region, 8 is a source electrode, and 9 is a drain electrode.

The insulating substrate 1 is a glass plate with a thickness of about 11Ill. The gate electrode 2 is made of Ta, Cr, Mo, AR, or W and is opaque. The active layer 4 is made of an a-3i film, and uses the resist 10 obtained by irradiating the positive photoresist layer with light from the insulating substrate 1 side, leaving only the portion corresponding to the gate electrode 2 as a mask. By etching, it has a shape that is self-aligned with the gate electrode 2. The source region 6 and drain region 7 are n◆ type a −8i Ii! by phosphorus doping. The electrode 8 and drain electrode 9 form an ohmic contact with the source electrode 8 and the drain electrode 9. The source electrode 8 and the drain electrode 9 are formed from extra-sized films.

The thickness of the active layer 4 is 200 to 300 layers. The protective insulating film 5 is located on the active layer 4, and both ends thereof are located slightly toward the center of the active layer 4 and are narrower than the gate electrode 2. The protective insulating film 5 is 3! 3 Made of N4 or Ag2O3 and has a thickness of 1,000 to 1. a (2000 people). In addition, the source region 6 and the drain region 7 are n◆ type a-8i.
The thickness of the contact layer of the membrane is 100~500 (200~
300) is included. These values ensure that the on-state resistance is below a predetermined value, and that the positive photoresist layer 10A for forming the active layer 4 is irradiated with light from the insulating substrate 1 side in an effective manner. This is a value determined experimentally. Note that this experimentally determined value has a wide range, and the active layer 4
Thickness and jl+type a-8i II! If the thickness of both 5A is 100A or more and the total thickness of both is 1000A or less, the specified MI! ! A transistor T is obtained.

The thin film transistor T of the present invention is configured as described above, and when used in combination with a liquid crystal to configure a display device (not shown), even if light is irradiated from the insulating substrate 1 side, the active layer 4 No carriers are generated in the OFF state, so the OFF resistance does not decrease in the OFF state. That is, the experimental results are as described below. The active IF4 has a thickness of 200 mm and a size of 10 μlll x 12 μm! When the transistor T is used in combination with a liquid crystal to form a display device, when the source-drain voltage Vso is 10 V, the illuminance is 1 from the insulating substrate 1 side.
I shows the relationship between the current 1d flowing in the drain region 6 and the voltage between the gate and drain when irradiated with light of 04Lx.
d-VG, the characteristic curve was as shown by C1 in FIG. Incidentally, the I d -ve characteristic curve when there is no light irradiation from the insulating substrate 1 side is C2, and the I d -V characteristic curve when light with an illuminance of jo'Lx is irradiated from the insulating substrate 1a side in the conventional example. The other characteristic curve was C3. VG9
An improvement in the OFF characteristics is clearly observed between -20V and -3V.

Moreover, since the active layer 4 has a thickness above a certain level, the On resistance does not become high in the on state. Furthermore, since the formation of the active layer 4 is carried out using the resist 9 having a shape that is self-aligned to the gate electrode 2 as a mask by the light from the insulating substrate 1 side and the positive photoresist layer 9A, the thin film transistor T is Manufacturing is simple and does not become complicated, and the size does not increase.

A method for manufacturing the thin film transistor T will be described below. A gate electrode 2 of a desired shape is laminated on an insulating substrate 1 made of a glass plate using a metal such as Ta (third
(see diagram).

A gate insulating layer 3 is formed on the entire surface of the insulating substrate 1 on the side where the gate electrode 2 is laminated by the plasma CVD method, and an a-8i semiconductor layer 4 with a thickness of 200 layers is formed on the gate insulating layer 3.
Stack A. In addition, a protective insulating film 5 is laminated on a portion of the a-8i semiconductor 114A corresponding to the gate electrode 2 in a pattern that goes inside the gate electrode 2 (see FIG. 4).

A phosphorus-doped n4 type a-51 layer 5A with a thickness of 200 OA is laminated on the a-3i semiconductor layer 4A and the protective insulating film 6, and a positive photoresist layer 10A is further laminated on the n'' type a-3i layer 5A. (See Figure 5).

The gate electrode 2 is exposed from the insulating substrate 1 side and is opaque.
is used as a photomask to form an n' type a-8i
A resist 10 having a shape self-aligned with the gate electrode 2 is formed on the 1I5A (see FIG. 6). At this time, since the total thickness of the n♦ type a-3i layer 6A and the a-8i semiconductor layer 4A is 100 OA or less, light acts effectively on the positive type photoresist layer 10°A.

Using resist 10 as a mask, type n4 a-3i1i6
A and a-8i semiconductor layers 4A are etched to form an n'+ type a-8i layer 6 in a shape that is self-aligned with the gate electrode 2.
B and active layer 4 are formed. Thereafter, the resist 10 is removed (see FIG. 7).

A metal layer 8A is laminated on the side metal layer on the side where the n÷ type a-3i layer 6B is located, and a 7-otoresist 11 is laminated on the upper part of the metal layer 8A excluding the central part of the n÷ type a-3i layer 6B. (8th
(see diagram).

Using this photoresist 10 as a mask, the metal layer 8A and n♦ type a-8i layer 6B are etched to form a source region 6, a drain region 7, a source electrode 8, and a drain region 9. After that, the photoresist 11 is removed (the first
(see diagram).

(G) Effects of the Invention In the present invention, when used in combination with a liquid crystal as a display device, a negative voltage is applied to the gate electrode. Even in the H state, generation of carriers from the active layer is prevented, and the OFF resistance is maintained at a predetermined value, and the resistance does not increase in the ON state, and the manufacturing process is complicated and the yield is low. This is a thin film transistor that does not increase the cost because there is no thin film transistor, and also does not have a problem in increasing the area of the display device because the size does not increase.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the configuration of one embodiment of the present invention, Fig. 2 is an explanatory diagram showing the characteristics of this embodiment and the conventional example, and Figs.
The figure is a structural explanatory diagram showing the manufacturing process of this embodiment, and FIG. 9 is a diagram corresponding to FIG. 1 of the subordinate memo. T...Wiff! Transistor, 1...
・Insulating substrate, 2...gate electrode, 4...
...active layer, 6...source region, 7.
...Drain region, 10...Resist. Fig. 1 Fig. 2 Fig. 7 Fig. 8 Fig. 9 r

Claims (1)

[Claims] 1. A gate electrode made of an opaque metal is laminated on an insulating substrate, a gate insulating layer is further laminated on the gate electrode and the surface of the insulating substrate, and on the gate insulating layer, An amorphous silicon semiconductor film and an amorphous silicon contact film, each having a thickness of 100 Å or more and a total thickness of 1000 Å or less, are laminated in a contour shape that is self-aligned with the gate electrode, and the amorphous silicon semiconductor film and the amorphous silicon contact film are laminated with a contour shape that is self-aligned with the gate electrode. A protective insulating film is interposed between the amorphous silicon contact film to separate the amorphous silicon contact film into a source region and a drain region, and a source electrode and a drain electrode are connected to the source region and the drain region, respectively. Thin film transistor.