JPH0323429A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPH0323429A JPH0323429A JP1157364A JP15736489A JPH0323429A JP H0323429 A JPH0323429 A JP H0323429A JP 1157364 A JP1157364 A JP 1157364A JP 15736489 A JP15736489 A JP 15736489A JP H0323429 A JPH0323429 A JP H0323429A
- Authority
- JP
- Japan
- Prior art keywords
- film
- light shielding
- passivation
- semiconductor film
- amorphous silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000002161 passivation Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 85
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 13
- 239000012535 impurity Substances 0.000 abstract description 11
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 150000002739 metals Chemical class 0.000 abstract 1
- 229920006268 silicone film Polymers 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- WUPHOULIZUERAE-UHFFFAOYSA-N 3-(oxolan-2-yl)propanoic acid Chemical compound OC(=O)CCC1CCCO1 WUPHOULIZUERAE-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052980 cadmium sulfide Inorganic materials 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- -1 monobuten Chemical compound 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業−Ｌの利用分野
本発明は、絶縁基板上にゲート電極、ゲート絶縁膜、半
導体膜、ソース電極並びにドレイン電極を積層形成して
なる所謂逆スタガー型の薄膜トランジスタ（ＴＰＴと称
する）に関する。Detailed Description of the Invention (a) Field of Application of Industry-L The present invention relates to a so-called inverted stagger type device in which a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode are stacked on an insulating substrate. The present invention relates to thin film transistors (referred to as TPT).
（ｏ）従来の技術
近年、アモルファスシリコンや多結晶シリコンなどの非
結晶半導体を用いたＴＰＴが開発され、アクティブマト
リクス型液晶表示装置の画素単位毎に表示ｔ極に画素信
号を供給するためのスイッチングＪ’Ｆ−として実用化
されている（特開昭６２−３７９６６の）。(o) Conventional technology In recent years, TPTs using non-crystalline semiconductors such as amorphous silicon and polycrystalline silicon have been developed, and switching for supplying pixel signals to the display t-pole for each pixel of active matrix liquid crystal display devices has been developed. It has been put into practical use as J'F- (Japanese Patent Application Laid-Open No. 62-37966).
このようなＴＰＴの半導体部分が受光するとこれに敏感
も反応して抵抗値が低下してスイッチング↑、Ｙ性が変
化するため、強力なバックライトを用いる光透過型の液
晶テレビにアクティブマトリクス型液晶表示装置を採用
する場合には、各ＴＰＴを遮光するための遮光対策が不
可欠である。When the semiconductor part of such a TPT receives light, it reacts sensitively to the light and its resistance value decreases, causing switching ↑ and Y properties to change. Therefore, active matrix type liquid crystal is used in light transmission type liquid crystal TVs that use a strong backlight. When employing a display device, it is essential to take measures to shield each TPT from light.
このため、一般にＴＰＴのチャンネル側の遮光はゲー｝
−１極で、バックチャンネル側の遮光は新たな遮光膜で
実現している。For this reason, generally the light shielding on the channel side of TPT is
-1 pole, light shielding on the back channel side is achieved with a new light shielding film.
しかしながら、このような従米のＴＦＴのパｌクチャン
ネル側の遮光膜の形戒には煩雑な戊膜工程が必要になり
、ＴＰＴ、さらには液晶表示装置の製造歩留まりの低下
を招くことになる。However, shaping the light shielding film on the PARK channel side of such conventional TFTs requires a complicated film process, which leads to a decrease in the manufacturing yield of TPTs and furthermore, liquid crystal display devices.
（ハ）発明が解決しようとする課題
本発明は上述の従来のＴＦ丁の欠点に鑑みてなされたも
のであり、或膜工程の簡略化が図れる遮光膜形状を備え
たＴＰＴを提供するものである。(c) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned drawbacks of the conventional TF film, and provides a TPT having a light-shielding film shape that can simplify the film process. be.
（二）課題を解決するための手段
本発ＩＪＩの逆スタガー型ＴＰＴは、バックチャンネル
側のパシベイション膜と遮光膜とを同一パターンに吠形
したものである。(2) Means for Solving the Problems The inverted staggered TPT of IJI according to the present invention has a passivation film and a light shielding film on the back channel side shaped in the same pattern.
（ホ）作用
本発明のＴＰＴによれば、バックチャンネル側のパシベ
イション膜と遮光膜と全同一パターンに戊形したので、
同一マスクで形成できるので、製造Ｔ程の簡略化が図れ
る。(E) Function According to the TPT of the present invention, since the passivation film and the light shielding film on the back channel side are all shaped in the same pattern,
Since they can be formed using the same mask, the manufacturing process can be simplified to the same extent as T.
（へ）実施例
第１図に本発明のＴＰＴの一実施例の構成を示す断面図
、第２図（ａ）〜（ｆ）に第１図のＴＰＴの製這Ｌ程順
断面図を示す。(f) Example Fig. 1 is a sectional view showing the configuration of an embodiment of the TPT of the present invention, and Figs. 2 (a) to (f) are sectional views showing the manufacturing process of the TPT in Fig. 1. .
第１図のＴＰＴは、ガラス基板ｌＯ上、ゲート電極ｌ、
ゲート絶縁膜２、半導体膜３、ソース電極７並びにドレ
イン電極８を積層形成した逆スタガー型をなし、半導体
膜３上にパシベイション膜４と遮光膜５とが積層ＩＩ威
されている。なお、半樽体膜３とソース電極７並びにド
レイン電極８との間には燐などの不純物が導入されたオ
ーミックコンタクトのための不純物半導体膜６が介在し
ており、この不純物半導体膜６の一部が上記遮光膜５−
Ｅに残存している。The TPT in FIG. 1 has a gate electrode l on a glass substrate lO,
It has an inverted staggered structure in which a gate insulating film 2, a semiconductor film 3, a source electrode 7, and a drain electrode 8 are laminated, and a passivation film 4 and a light shielding film 5 are laminated on the semiconductor film 3. Note that an impurity semiconductor film 6 containing an impurity such as phosphorus for ohmic contact is interposed between the half-barrel film 3 and the source electrode 7 and drain electrode 8. The part is the light shielding film 5-
remains in E.
斯る本発明のＴＰＴが特徴とするところは、上記パシベ
イシ３冫ｌＩＩ４と遮光膜５とが同一パターンで形成さ
れたところにある。但し、図では特徴的に表しているよ
うに、パシベイション膜４はサイドエノチング効果によ
り遮光膜５より若干パターンサイズが小さくなっている
。The TPT of the present invention is characterized in that the passivation layer 3 and the light shielding film 5 are formed in the same pattern. However, as characteristically shown in the figure, the pattern size of the passivation film 4 is slightly smaller than that of the light shielding film 5 due to the side etching effect.
以Ｆに上述の第１図の本発明ＴＰＴを第２図を用いて製
造工程順に説明する。Hereinafter, the TPT of the present invention shown in FIG. 1 will be explained in the order of manufacturing steps using FIG. 2.
（１）第２図（ａ）に示す如く、ガラス基板１０上にク
ロムなどの金属からなるゲートｔ極ｌを形處する。(1) As shown in FIG. 2(a), a gate pole l made of a metal such as chromium is formed on a glass substrate 10.
（ Ｉ１ ）同図（ｂ）に示す如く、ゲート絶縁膜・２
となる窒化シリコンなどの絶縁物質膜、半導体膜３とな
るアモルファスシリコン膜、パシベイション膜４となる
窒化シリコンなどの絶縁物質膜、及び逼光膜５となる金
属膜を全面に順次戊膜する。(I1) As shown in the same figure (b), the gate insulating film 2
An insulating material film such as silicon nitride to become the semiconductor film 3, an amorphous silicon film to become the semiconductor film 3, an insulating material film such as silicon nitride to become the passivation film 4, and a metal film to become the light blocking film 5 are successively deposited over the entire surface.
（Ｉｌ１）同図（ｃ）に示す如く、同一レジストをマス
クとして、最上の金属膜、その下層の絶縁物質膜を順次
エッチングして遮光膜５とパシベイション膜４とを同一
パターンに戊形する。但し、第２層のバシベイション膜
４の工・／チング時に、この膜４のサイドエッチングに
より、遮光膜５に若干のオーバーハングが生じる。(Il1) As shown in FIG. 2C, the uppermost metal film and the underlying insulating material film are sequentially etched using the same resist as a mask to form the light shielding film 5 and the passivation film 4 into the same pattern. However, when etching/etching the second layer vacillation film 4, a slight overhang occurs in the light shielding film 5 due to side etching of this film 4.
（［Ｖ）同図（ｄ）に示す如く、不純物半導体膜６とな
るアモルファスシリコンに燐を導入したＮ型アモルファ
スシリコン膜を全面に積層する。これニヨって、半導体
膜３となるアモルファスシリコン膜上のみならず、遮光
膜５上にもこのＮ型アモルファスシリコン膜が堆積され
る。([V) As shown in FIG. 6(d), an N-type amorphous silicon film in which phosphorus is introduced into amorphous silicon, which will become the impurity semiconductor film 6, is laminated over the entire surface. Accordingly, this N-type amorphous silicon film is deposited not only on the amorphous silicon film that will become the semiconductor film 3 but also on the light shielding film 5.
（Ｖ）同図（ｅ）に示す如く、上記Ｎ型アモルファスシ
リコン膜とアモルファスシリコン膜とを同時にエッチン
グすることによって、不純物半導体ＩＩ！ ６と半導体
膜３とを得る。この際、前記工程で不純物半導体膜６は
パシベイション膜４の端部で段差切れをしているため、
チャンネル部の不純物半導体膜６をエッチングする必要
はない。(V) As shown in (e) of the same figure, by simultaneously etching the N-type amorphous silicon film and the amorphous silicon film, the impurity semiconductor II! 6 and a semiconductor film 3 are obtained. At this time, since the impurity semiconductor film 6 is cut off at the end of the passivation film 4 in the above step,
There is no need to etch the impurity semiconductor film 6 in the channel portion.
（Ｖｌ）同図（ｆ）に示す如く、アルミニウムなどの金
属からなるソース電極７、並びにドレイン電極８を形戊
する。(Vl) As shown in FIG. 4(f), a source electrode 7 and a drain electrode 8 made of metal such as aluminum are formed.
以Ｌの工程で、上記パシベイション膜４と遮光膜５とが
同一パターンで形戊さｈｆ：ＴＦＴが得られる。In the following steps, an hf:TFT is obtained in which the passivation film 4 and the light shielding film 5 are formed in the same pattern.
第３図（ａ）（ｂ）は第２図（ｄ）の工程に引き続いて
行わｔＬるＬ記第２図と異なる他の実施例の工程を示す
断面図であり、以下に工程を述べる。FIGS. 3(a) and 3(b) are cross-sectional views showing steps of another embodiment different from those shown in FIG. 2, which are performed subsequent to the steps shown in FIG. 2(d), and the steps will be described below.
（Ｖ゛）第３図（ａ）に示す如く、第２図（ｄ）に引き
続いて、Ｘ型アモルファスシリコン膜上にソース電極７
並びにドレインｔＶｉ８となる金属膜を積層する。(V゛) As shown in FIG. 3(a), following FIG. 2(d), a source electrode 7 is placed on the X-type amorphous silicon film.
Also, a metal film that will become the drain tVi8 is laminated.
（ Ｖｌ ’ ）同図（ｂ）に示す如く、同一レジスト
をマスクに、上記金属膜とＮ型アモルファスシリコン膜
並び（こア七ノレファスシリコ冫・膜を同一パターンに
エッチングして、ソース電極７並びにドレイン電極８、
不純物半導体膜６、及び半導体膜３が形成される。二の
場合、上記パシベイション膜４．Ｌの遮光膜５、不純物
半導体膜６のさらに上層に金属膜が残存するため、パシ
ベイション膜４の膜厚をソース電極７並びにドレイン電
極８の金属膜厚よりｑく設定することで、これによる段
差切れを利用してソースｔ極７ドレインｔ極８間の短絡
事故を防止できる。また、ソース電極７並びにドレイン
電悔８と不純物半導体膜６とはパシベイション膜・１に
より段差切れをしているため、これらをチャンレル部か
ら除去する必要はない。(Vl') As shown in Figure (b), using the same resist as a mask, the metal film and the N-type amorphous silicon film are etched into the same pattern to form the source electrode 7 and the drain. electrode 8,
Impurity semiconductor film 6 and semiconductor film 3 are formed. In case 2, the passivation film 4. Since a metal film remains above the L light shielding film 5 and the impurity semiconductor film 6, the thickness of the passivation film 4 is set to be q greater than the metal film thickness of the source electrode 7 and drain electrode 8, thereby reducing the level difference caused by this. By using the cut, it is possible to prevent a short circuit accident between the source t-pole 7 and the drain t-pole 8. Further, since the source electrode 7, the drain electrode 8, and the impurity semiconductor film 6 are separated by the passivation film 1, there is no need to remove them from the channel portion.
以上の上程で本発明ＴＰＴが得られる。The TPT of the present invention can be obtained through the above steps.
−Ｌ述の各実施例のＴＰＴにおいて、ゲート電極１、ソ
ース電極７並びにドレイン電桶８の電極材科としては、
Ｌ記の実施例の他、金、チタン、モノブデン、タンタル
、ニッケル、クロム、タングステン、シリサイド等があ
り、またこれらの多層膜が利用できる。また、遮光膜５
としては、金属の池染色樹脂膜等あらゆる不透明材科が
用いられる。さらに、ゲート絶縁膜２、パシベイション
膜１としては窒化シリコンの他にも、酸化シリコン等の
絶縁性の金属酸化物を利用できる。さらに、半導体膜３
としては、アモルファスシリコンの池多結晶シリコン、
硫化カドミウム、テルル等も使用できる。- In the TPT of each embodiment described above, the electrode materials of the gate electrode 1, source electrode 7, and drain electrode 8 are as follows:
In addition to the embodiments listed in L, gold, titanium, monobuten, tantalum, nickel, chromium, tungsten, silicide, etc. can be used, and multilayer films of these can also be used. In addition, the light shielding film 5
All opaque materials such as metal pond-dyed resin membranes can be used as the material. Furthermore, as the gate insulating film 2 and the passivation film 1, insulating metal oxides such as silicon oxide can be used in addition to silicon nitride. Furthermore, the semiconductor film 3
as amorphous silicon, polycrystalline silicon,
Cadmium sulfide, tellurium, etc. can also be used.
（ト）発明の効果
本発明の逆スタガー型のＴＰＴは、バンクチャンネル側
の半導体膜上のパシベイション膜と遮光膜とを同一パタ
ーンで戊形したものであるので、同一マスクで両１漠を
簡単に形戊できるため，製遣歩留まＩ）の向上が図れる
。(G) Effects of the Invention In the inverted staggered TPT of the present invention, the passivation film and the light shielding film on the semiconductor film on the bank channel side are shaped in the same pattern, so both can be easily formed using the same mask. Since it can be shaped into
第１図は本発明のＴＰＴの一実施例の断面図、第２図（
ａ）乃至（ｆ）は第１図の本発明ＴＰＴの製造［程を示
す断面図、第３図（ａ ）（ｂ ）は本発明ＴＰＴの他
の実施例の工程断面図である。
１・・・ゲート電極、２・・・ゲート絶縁膜、３・・・
半導体膜、４・・・パシベイション膜、５・・・遮光膜
、６・・・不純物半導体膜、７・・・ソース電極、８・
・・ドレインｔ極、ｌＯ・・・ガラス基板。Figure 1 is a sectional view of one embodiment of the TPT of the present invention, and Figure 2 (
3A to 3F are cross-sectional views showing the manufacturing process of the TPT of the present invention shown in FIG. 1... Gate electrode, 2... Gate insulating film, 3...
Semiconductor film, 4... Passivation film, 5... Light shielding film, 6... Impurity semiconductor film, 7... Source electrode, 8...
...Drain t pole, lO...Glass substrate.
Claims (1)
膜、ソース電極並びにドレイン電極を積層形成してなる
逆スタガー型の薄膜トランジスタにおいて、半導体膜上
にパシベイション膜と遮光膜とを同一パターンで成形し
たことを特徴とする薄膜トランジスタ。(1) In an inverted staggered thin film transistor in which a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode are stacked on an insulating substrate, a passivation film and a light shielding film are formed in the same pattern on the semiconductor film. A thin film transistor characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1157364A JPH0323429A (en) | 1989-06-20 | 1989-06-20 | Thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1157364A JPH0323429A (en) | 1989-06-20 | 1989-06-20 | Thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0323429A true JPH0323429A (en) | 1991-01-31 |
Family
ID=15648044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1157364A Pending JPH0323429A (en) | 1989-06-20 | 1989-06-20 | Thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0323429A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08292450A (en) * | 1995-04-24 | 1996-11-05 | Nec Corp | Liquid crystal display device |
| JPH0943632A (en) * | 1995-05-19 | 1997-02-14 | Nec Corp | Thin film transistor array |
| EP0915027A1 (en) | 1997-11-10 | 1999-05-12 | Taihei Paper Manufacturing Co.,LTD. | Container closure system with inner seal in cap |
| JP2007072447A (en) * | 2005-08-12 | 2007-03-22 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and method for manufacturing the same |
| JP4703923B2 (en) * | 2001-09-28 | 2011-06-15 | 能美防災株式会社 | Smoke detector smoke tester |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63215078A (en) * | 1987-03-04 | 1988-09-07 | Nippon Sheet Glass Co Ltd | Manufacture of thin film transistor |
-
1989
- 1989-06-20 JP JP1157364A patent/JPH0323429A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63215078A (en) * | 1987-03-04 | 1988-09-07 | Nippon Sheet Glass Co Ltd | Manufacture of thin film transistor |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08292450A (en) * | 1995-04-24 | 1996-11-05 | Nec Corp | Liquid crystal display device |
| JPH0943632A (en) * | 1995-05-19 | 1997-02-14 | Nec Corp | Thin film transistor array |
| EP0915027A1 (en) | 1997-11-10 | 1999-05-12 | Taihei Paper Manufacturing Co.,LTD. | Container closure system with inner seal in cap |
| US6277478B1 (en) | 1997-11-10 | 2001-08-21 | Taihei Paper Manufacturing | Container closure system with inner seal in cap |
| JP4703923B2 (en) * | 2001-09-28 | 2011-06-15 | 能美防災株式会社 | Smoke detector smoke tester |
| JP2007072447A (en) * | 2005-08-12 | 2007-03-22 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and method for manufacturing the same |
| US7576359B2 (en) | 2005-08-12 | 2009-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for manufacturing the same |
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