JPH04326769A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a TFT having a channel protective film having excellent element characteristics such as mobility, etc. CONSTITUTION:In a thin film transistor having an active layer 45 formed on a light transmission insulating board 21, source and drain electrodes 49 arranged oppositely through a channel protective film 41 in contact with the layer 45 through a contact layer 47, and a gate electrode 25 arranged on a lower part of the layer 45 through gate insulating films 27, 29, an end of the electrode 25 is tapered.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, and more particularly to an inverted staggered thin film transistor having a channel protection film.

0002

2. Description of the Related Art In recent years, active matrix liquid crystal display devices using thin film transistors (TFTs) as switching elements have attracted attention. This is because by using an inexpensive glass substrate, it is possible to realize a panel display with a large screen, high definition, and high image quality at low cost. FIG. 11 shows a cross-sectional view of a conventional inverted staggered TFT.

[0003] To explain this according to the manufacturing process, first,
An opaque metal thin film is deposited on a transparent insulating substrate 1, and this opaque metal thin film is patterned by photolithography using a photomask to form a gate electrode 3.

Next, on the transparent insulating substrate 1 on which the gate electrode 3 is formed, a first insulating film which becomes the gate insulating film 5, an amorphous silicon (a-Si) film which becomes the active layer 7, After sequentially forming a second insulating film that will become the channel protective film 9, a positive photoresist is applied to the entire surface.

Next, a photoresist pattern is formed by backside exposure using the gate electrode 3 as a mask, and then a second insulating film is patterned using this photoresist pattern as a mask. Then, a channel protective film 9 is formed. Next, an n+ a-Si film, which will become the contact layer 11, and a so-
A metal film that will become the drain electrode 13 is sequentially deposited. Finally, these films are patterned to form contact layer 1.
1. The source/drain electrodes 13 are formed to complete the basic structure of the TFT.

In the TFT obtained by the method described above, since the channel protection film 9 is formed in a self-aligned manner with the gate electrode 3, variations in device characteristics caused by misalignment of masks are suppressed.

However, fortunately, the channel protective film 9 is formed in a self-aligned manner with the gate electrode 3, and the dimension of the channel protective film 9 in the channel length direction is set to be the same as that of the gate electrode 3 in the channel length direction. Since it is difficult to make the contact layer shorter than the dimensions, it is difficult to widen the junction between the active layer 7 and the contact layer 11 on the gate electrode, which has a large effect on device characteristics, and it is difficult to obtain large on-current and mobility. It was difficult.

[0008]

[Problems to be Solved by the Invention] As mentioned above, in a TFT provided with a conventional channel protective film, the junction surface between the active layer on the gate electrode and the contact layer is narrow, and device characteristics such as on-current and mobility are affected. There was a problem with that.

The present invention has been made in consideration of the above circumstances, and its object is to provide a TFT having a channel protective film with good electrical characteristics and a method for manufacturing the same.

0010

[Means for Solving the Problems] The gist of the thin film transistor of the present invention is that the end of the gate electrode is tapered to provide a wide bonding surface between the active layer on the gate electrode and the contact layer.
The reason is that it has made manufacturing easier.

That is, in order to achieve the above object, the thin film transistor of the present invention has an active layer formed on a substrate, which is in contact with the active layer via a contact layer, and is opposed to the active layer via a channel protective film. In a thin film transistor having a source and a drain electrode disposed in the same manner as the active layer, and a gate electrode disposed under the active layer with a gate insulating film interposed therebetween, the gate electrode has a tapered end. - It is characterized by being equipped with a top electrode.

The gist of the method for manufacturing a thin film transistor of the present invention is that the end of the gate electrode is tapered to allow more light to pass through the resist on the gate electrode. That is, in order to achieve the above object, the method for manufacturing a thin film transistor of the present invention includes the following steps:

A step of forming a gate electrode with a tapered end on a transparent substrate; and a step of sequentially depositing a gate insulating film, an active layer, and a channel protective film on the substrate. , after applying a resist on the channel protective film, forming a resist pattern by irradiating the resist with light from the back side of the substrate; and patterning the channel protective film using the resist pattern as a mask. - a step of depositing a contact layer on the substrate and patterning the contact layer and the active layer; depositing a conductive film on the substrate and then patterning the conductive film and the contact layer; The method is characterized by comprising a step of patterning the layer and forming source/drain electrodes.

[0014]

[Operation] In the thin film transistor of the present invention, since the end of the gate electrode is tapered, the contact layer and the active layer deposited on the end of the gate electrode are bonded to each other due to the dependence on the base. Because the plane is inclined, the active layer is more affected by the electric field of the source and drain electrodes than when the junction plane between the active layer and the contact layer on the edge of the gate electrode is perpendicular. The area becomes wider and more carriers are generated. Therefore, device characteristics such as on-current and mobility are improved.

Furthermore, in the method for manufacturing a thin film transistor of the present invention, since the gate electrode with tapered ends is used as a mask, the light emitted from the back surface of the substrate is transmitted through the ends of the gate electrode. The light is diffracted and irradiated onto the resist on the gate electrode, and is repeatedly reflected between the insulating film serving as a channel protection film and the gate electrode, and is irradiated onto the resist on the gate electrode.

As a result, compared to when the end of the gate electrode is parallel to the substrate, the exposed region extends further into the resist, and therefore the region is greatly affected by the electric field of the source/drain electrode. A wide active layer is formed, and more carriers are generated. Therefore, device characteristics such as on-current and mobility are improved.

[0017]

Embodiments Hereinafter, embodiments will be described with reference to the drawings. 1 to 7 show cross-sectional views of the manufacturing process of a TFT according to an embodiment of the present invention. Initially, as shown in Figure 1,
Approximately 300 nm thick on a transparent insulating substrate 21 such as a glass substrate.
A MoTa alloy film 23 of m thickness is deposited.

Next, as shown in FIG. 2, the MoTa alloy film 23 is patterned with active molecules generated by microwave discharge using isotropic etching, for example, CF4 gas or O2 gas, to form a tapered shape. A gate electrode 25 is formed. Note that the taper angle due to this etching, that is, the angle θ of the end surface of the gate electrode 3 with respect to the transparent insulating substrate 21
was approximately 30°.

Next, as shown in FIG. 3, a first gate insulating film 27 made of a silicon oxide film with a thickness of about 350 nm and a first gate insulating film 27 with a thickness of about 50 nm are formed on the transparent insulating substrate 1 using the CVD method. A second gate insulating film 29 made of a silicon nitride film, an a-Si film 31 with a thickness of about 50 nm to serve as an active layer, and a silicon nitride film 33 with a thickness of about 200 nm to serve as a channel protection film are sequentially deposited.

Next, as shown in FIG. 4, silicon nitride film 3 is
After applying a positive type photoresist 35 on the substrate 3 using spin coating or the like, the photoresist 35 is exposed by irradiating ultraviolet rays 37 from the back side of the transparent substrate 1 for 1 minute using a 3kW ultra-high pressure mercury lamp. .

Next, as shown in FIG.
5 to form a photoresist pattern 39, the silicon nitride film 33 is patterned using this photoresist pattern 39 as a mask to form a channel protective film 4.
form 1. After this, the photoresist pattern 39 is removed. Note that it is preferable to define the dimension in the channel width direction by performing normal exposure (double exposure) by mask alignment after backside exposure.

Next, as shown in FIG. 6, an n+ a-Si film 4 with a thickness of approximately 50 nm or more is formed to serve as a contact layer over the entire surface of the substrate.
After depositing the active layer 45, the second gate insulating film 29, the a-Si film 31, and the n+ a-Si film 43 are patterned at once.

Finally, after forming a contact hole for taking out the gate electrode, a laminated film of Mo and Al is deposited on the entire surface of the substrate as shown in FIG. - The basic structure of the TFT is completed by patterning the Si film 43 to form a contact layer 47 and source/drain electrodes 49. Note that a passivation film is formed using a pixel electrode, a silicon nitride film, or the like, if necessary.

Further, the contact layer 47 is made of n+ a-Si
Instead of forming a film by depositing it, plasma doping, ion implantation, etc. are used to add n to the a-Si film that will become the active layer 45.
It may also be formed by adding type impurity atoms. At this time, a
-Since the Si film is sloped, it has the advantage that n-type impurity atoms can be easily added to the sidewall portion. Furthermore, instead of forming the source/drain electrodes 49 by mask alignment, the source/drain electrodes 49 may be formed by self-alignment.

In the TFT obtained by the manufacturing method described above, the dimension of the channel protective film 41 in the channel length direction is shorter than that of a conventional TFT, so that it is greatly affected by the electric field of the source/drain electrode 49. The channel protective film 41 becomes wider, and device characteristics such as on-current and mobility are improved. This will be explained in more detail using FIG. 8. FIG. 8 shows the ultraviolet rays 37 at the end of the gate electrode 25 in FIG.
FIG.

The ultraviolet rays 37 emitted from the back surface of the transparent insulating substrate 21 basically do not irradiate the photoresist 35 on the gate electrode 25, but if the end of the gate electrode 25 is tapered. Because of its shape, it causes diffraction at its ends and wraps around inside the gate electrode 25. As a result, ultraviolet rays 37 are
The photoresist 35 on the edge of the gate electrode 25 is also irradiated.

Further, a part of the diffracted ultraviolet rays 37 is transmitted to the interface between the first gate insulating film 27 and the second gate insulating film 29, and the second gate insulating film 29 and a - After being reflected at the interface with the Si film 31, the interface between the a-Si film 31 and the silicon nitride film 33, or the interface between the silicon nitride film 33 and the photoresist 35, it is reflected again at the gate electrode 25 and the gate - The photoresist 35 on the end of the gate electrode 25 is irradiated, or the photoresist 35 on the end of the gate electrode 25 is irradiated by repeating such reflection.

Therefore, the exposed portion A of the photoresist 35 extends further inside the gate electrode 25 than in the conventional case, making it possible to form a photoresist pattern 39 with a shorter dimension in the channel length direction, thereby reducing the contact length. ΔL, that is, the dimension of the junction surface between the active layer 45 and the contact layer 47 on the end of the gate electrode 25 along the channel length direction can be made longer.

As a result, the portion of the active layer 45 that is greatly affected by the electric field of the source/drain electrode 49 becomes wider and more carriers are generated, so that device characteristics such as on-current and mobility are improved. Ru. In particular, the n of the contact layer 47
+ a-Si layer, a-Si layer of active layer 45, n+ a-Si/a-S due to n+ a-Si layer induced by electric field
The effect of reducing the contact resistance of the i/n+a-Si junction is significant.

Moreover, in the TFT of this example, a-Si
Since the thin second gate insulating film 29 provided between the film 31 and the first gate insulating film 27 acts as an optical buffer layer, reflection of the ultraviolet light 37 is moderately suppressed. Overexposure can be prevented.

Furthermore, in the TFT manufacturing method of this embodiment,
The contact length ΔL could be set to about 0.5 μm with good reproducibility, and by adjusting the exposure time of the photoresist 35, the contact length ΔL could be controlled within a range of 1 μm.

[0032] Furthermore, in the TFT configured in this way,
Since the end of the gate electrode 25 is tapered, the bonding surface between the active layer 45 and the contact layer 47 also partially becomes tapered due to the dependence on the underlying layer.

As a result, the active layer 45 and the contact layer 47
Compared to when the bonding surface with the active layer 45 is a uniform plane,
The effective bonding surface between the contact layer 47 and the contact layer 47 is widened, and device characteristics are improved.

FIG. 9 is a characteristic diagram showing the relationship between contact length ΔL and mobility. In the figure, σ1 and σ2 are the TF obtained by the manufacturing method of this example and the conventional manufacturing method, respectively.
The range of variation in the contact length ΔL of T is shown. As can be seen from this figure, the mobility decreases rapidly when the contact length ΔL becomes less than a certain value ΔL0. Accordingly, in the conventional manufacturing method, the contact length ΔL may be less than ΔL0, resulting in defective TFTs being manufactured and a decrease in yield. Furthermore, in the conventional manufacturing method, there is a large variation in the contact length ΔL, so when such a TFT is used in a liquid crystal display device, a problem arises in that the image quality deteriorates. On the other hand, in the manufacturing method of this embodiment, the contact length ΔL
can be reliably made larger than ΔL0, and variations can be reduced.

[0035] Therefore, a TFT with sufficiently large mobility
is manufactured reliably and yields are improved. Further, by using such a TFT, a high-quality liquid crystal display device can be obtained.

Note that the present invention is not limited to the embodiments described above. For example, in the above embodiment, the taper angle θ of the gate electrode 25 was set to about 30°, but a similar effect can be obtained if it is 45° or less. Further, in the above embodiment, the gate electrode 25 was formed into a tapered shape with a curvature of zero, but as shown in FIG. Good too. In this case, the gate electrode 2
Although the amount of light diffracted at the ends of the second embodiment is reduced compared to the previously described embodiment, the same effect can be obtained.

Further, in the above embodiment, the gate insulating film has a two-layer structure, but it may have a single-layer structure or a multi-layer structure of three or more layers. In the case of a multilayer structure, contrary to the above embodiment, the gate insulating film on the substrate side is an insulating film with a high dielectric constant, such as a metal oxide film or an oxidized (anodized, etc.) film for the gate electrode. You may also use

Furthermore, an undercoat layer may be provided between the transparent insulating substrate 21 and the gate electrode 25. At this time, if the refractive index between the first gate insulating film 27 and the undercoat layer is made to be approximately the same, reflection of ultraviolet rays 37 at the interface between the gate insulating film 27 and the undercoat layer can be suppressed. can. For example, by using a silicon oxide film as the undercoat layer in the same way as the first gate insulating film 27, ultraviolet rays 37
can reduce reflections. In addition, various modifications can be made without departing from the gist of the present invention.

[0039]

Effects of the Invention As described in detail above, according to the present invention, the active layer portion that is greatly affected by the electric field of the source/drain electrodes is widened, so channel protection with excellent on-current, mobility, etc. A TFT with a film can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a first manufacturing process of a TFT according to an embodiment of the present invention.

FIG. 2 is a sectional view of a second manufacturing process of a TFT according to an embodiment of the present invention.

FIG. 3 is a sectional view of a third manufacturing process of a TFT according to an embodiment of the present invention.

FIG. 4 is a sectional view of a fourth manufacturing process of a TFT according to an embodiment of the present invention.

FIG. 5 is a sectional view of a fifth manufacturing process of a TFT according to an embodiment of the present invention.

FIG. 6 is a sectional view of a sixth manufacturing process of a TFT according to an embodiment of the present invention.

FIG. 7 is a sectional view of a seventh manufacturing process of a TFT according to an embodiment of the present invention.

FIG. 8 is a diagram showing the optical path of ultraviolet light at the end of the gate electrode in FIG. 4;

FIG. 9 is a diagram showing the relationship between mobility and source contact length.

FIG. 10 is a diagram showing a tapered gate electrode with curvature.

FIG. 11 is a cross-sectional view of a TFT with a conventional channel protective film.

[Explanation of symbols]

21... Transparent insulating substrate, 23... MoTa alloy film, 25...
Gate electrode, 27... First gate insulating film, 29... Second gate insulating film, 31... a-Si film, 33... Silicon nitride film, 35... Photoresist, 37... Ultraviolet light, 39 ...Photoresist pattern, 41...Channel protective film, 43...n
+ a-Si film, 45... active layer, 47... contact layer,
49...Source/drain electrode.

Claims (2)

[Claims] 1. An active layer formed on a substrate; source and drain electrodes contacting the active layer via a contact layer and facing each other via a channel protective film; 1. A thin film transistor having a gate electrode disposed below a layer with a gate insulating film interposed therebetween, wherein the gate electrode has a tapered end. 2. A step of forming a gate electrode with a tapered end on a transparent substrate, and sequentially depositing a gate insulating film, an active layer, and a channel protective film on the substrate. a step of applying a resist on the channel protective film and then irradiating the resist with light from the back side of the substrate to form a resist pattern; and applying the resist pattern to the channel protective film using the resist pattern as a mask. After depositing a contact layer on the substrate, patterning the contact layer and the active layer; After depositing a conductive film on the substrate, patterning the conductive film. A method for manufacturing a thin film transistor, comprising the step of patterning the contact layer to form source/drain electrodes.